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path: root/bfd/elfnn-riscv.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-05bfd/riscv: prepare to handle bare metal core dump creationAndrew Burgess1-2/+82
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-17/+17
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-2/+3
2021-02-17RISC-V: PR27200, allow the first input non-ABI binary to be linked with any one.Nelson Chu1-14/+16
2021-01-15RISC-V: Fixed the indent that caused by the previous commits accidentally.Nelson Chu1-1/+1
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu1-109/+108
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-2/+2
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-49/+49
2021-01-06RISC-V: Implement support for big endian targets.Marcus Comstedt1-33/+74
2021-01-05RISC-V: Ouput __global_pointer$ as dynamic symbol when generating dynamic PDE.Nelson Chu1-0/+9
2021-01-04RISC-V: Fix the merged orders of Z* extension for linker.Nelson Chu1-34/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-01RISC-V: Support to add implicit extensions.Nelson Chu1-9/+12
2020-11-21RISC-V: Relax PCREL to GPREL while doing other relaxations is dangerous.Nelson Chu1-13/+18
2020-10-16RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place.Nelson Chu1-7/+39
2020-10-16RISC-V: Support GNU indirect functions.Nelson Chu1-47/+678
2020-09-03RISC-V: Minor cleanup and typos when merging elf attributes.Nelson Chu1-12/+12
2020-09-03RISC-V: Report warnings rather than errors for the mis-matched ISA versions.Nelson Chu1-32/+39
2020-09-03RISC-V: Improve the error message for the mis-matched ISA versions.Kito Cheng1-1/+1
2020-08-31PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra1-3/+3
2020-08-28RISC-V: Treat R_RISCV_CALL and R_RISCV_CALL_PLT as the same in check_relocs.Nelson Chu1-9/+10
2020-08-25elf_hash_table_id accessAlan Modra1-2/+3
2020-07-30elf: Add sym_cache to elf_link_hash_tableH.J. Lu1-4/+1
2020-06-23ELF: Add _bfd_elf_add_dynamic_tagsH.J. Lu1-45/+1
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-11/+36
2020-06-22RISC-V: Don't assume the priv attributes are in order when handling them.Nelson Chu1-37/+36
2020-06-05RISC-V: The object without priv spec attributes can be linked with any object.Nelson Chu1-2/+38
2020-06-03ELF: Consolidate maybe_set_textrelH.J. Lu1-28/+2
2020-06-03ELF: Copy dyn_relocs in _bfd_elf_link_hash_copy_indirectH.J. Lu1-31/+0
2020-06-03ELF: Consolidate readonly_dynrelocsH.J. Lu1-19/+2
2020-06-01ELF: Move dyn_relocs to struct elf_link_hash_entryH.J. Lu1-21/+15
2020-05-21Replace "if (x) free (x)" with "free (x)", bfdAlan Modra1-3/+2
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-1/+5
2020-05-14RISC-V: Add elfNN_riscv_mkobject to initialize RISC-V tdata.Nelson Chu1-0/+9
2020-05-01PR25900, RISC-V: null pointer dereferenceAlan Modra1-5/+6
2020-02-26Indent labelsAlan Modra1-3/+3
2020-02-19bfd_size_type to size_tAlan Modra1-2/+2
2020-01-22RISC-V: Change -march parsing.Jim Wilson1-63/+83
2020-01-06RISC-V: Fix weak function call reloc overflow on llvm build.Jim Wilson1-3/+6
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-12RISC-V: Fix ld relax failure with calls and align directives.Jim Wilson1-3/+10
2019-10-17RISC-V: Report unresolved relocation error via linker's callback function.Jim Wilson1-17/+46
2019-09-20RISC-V: Optimize lui and auipc relaxations for undefweak symbol.Jim Wilson1-27/+116
2019-09-19bfd_section_* macrosAlan Modra1-6/+5
2019-08-31RISC-V: Fix linker problems with tls copy relocs.Jim Wilson1-0/+14
2019-08-30RISC-V: Force linker error exit after unresolvable reloc.Jim Wilson1-1/+4
2019-08-28RISC-V: Fix a gp relaxation reloc overflow error.Jim Wilson1-7/+10
2019-08-15RISC-V: Fix lui relaxation issue with code at address 0.Jim Wilson1-2/+14
2019-08-01RISC-V: Fix lui relax failure with relro.Jim Wilson1-2/+7
2019-06-24RISC-V: Enable lui relaxation for CODE and MERGE sections.Jim Wilson1-10/+46