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path: root/bfd/elfnn-aarch64.c
AgeCommit message (Expand)AuthorFilesLines
2016-05-28Return void from linker callbacksAlan Modra1-19/+11
2016-05-23Enable R_AARCH64_NONE for 64-bit code.Jim Wilson1-4/+2
2016-05-13Set dynamic tag VMA and size from dynamic section when possibleAlan Modra1-1/+2
2016-05-11[AArch64] Remove redundant tls relax in elfNN_aarch64_final_link_relocateJiong Wang1-13/+3
2016-05-03[AArch64] Also puts value in place for R_AARCH64_RELATIVEJiong Wang1-1/+7
2016-04-11Properly handle dynamic reloc against normal symbolH.J. Lu1-0/+1
2016-03-07[AArch64] Create .got section if _GLOBAL_OFFSET_TABLE_ referencedJiong Wang1-0/+16
2016-02-26[BFD][AARCH64]Fix MOVW_SABS_G(0,1,2) relocation overflow check.Renlin Li1-3/+3
2016-02-24Revert "ABS32"Renlin Li1-15/+3
2016-02-24ABS32Renlin Li1-3/+15
2016-02-22[AArch64] Remove redundant calculation of plt stub destination for veneerJiong Wang1-16/+3
2016-02-09Add a more helpful warning message to explain why some AArch64 relocations ca...Nick Clifton1-4/+31
2016-02-09Revert "Add a more helpful warning message to explain why some AArch64 reloca...Walfred Tedeschi1-31/+4
2016-02-09Add a more helpful warning message to explain why some AArch64 relocations ca...Nick Clifton1-4/+31
2016-01-21[AArch64] Relax long branch veneer insertion for non STT_FUNC symbolJiong Wang1-6/+19
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-11-12Revert "[LD][AARCH64]Add TLSIE relaxation support under large memory model."Marcus Shawcroft1-51/+2
2015-10-29Add support for AArch64 CloudABI binaries.Ed Schouten1-0/+19
2015-10-02[LD][AARCH64]Add TLSIE relaxation support under large memory model.Renlin Li1-2/+51
2015-10-02[LD][AARCH64]Add TLSDESC support for large memory model.Renlin Li1-3/+102
2015-10-02[GAS][AARCH64]Add TLSDESC large memory model support.Renlin Li1-1/+1
2015-10-02[BFD][AARCH64]Add TLSGD relaxation support under large memory model.Renlin Li1-0/+60
2015-10-02[BFD][AARCH64]Create GOT section for TLSLE_MOVW_TPREL_G(1, 1_NC, 2).Renlin Li1-0/+3
2015-10-02[Binutils][AARCH64]Add TLS IE large memory support.Renlin Li1-28/+38
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.Renlin Li1-0/+5
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.Renlin Li1-0/+16
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support.Renlin Li1-0/+14
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support.Renlin Li1-0/+16
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC Support.Renlin Li1-0/+7
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC Support.Renlin Li1-0/+15
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 Support.Renlin Li1-0/+7
2015-10-02[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 Support.Renlin Li1-0/+15
2015-10-02[LD][AARCH64]Add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 Support.Renlin Li1-0/+72
2015-10-02[BFD][AARCH64]Refactor to facilitate further large memory model support patches.Renlin Li1-4/+12
2015-10-01[BFD][AARCH64]Emit single AARCH64_MAP_INSN symbol for the whole plt.Renlin Li1-35/+1
2015-09-20Add --no-dynamic-linker option to ld, for static PIE useRich Felker1-1/+1
2015-09-09[AArch64] Sort IS_AARCH64_TLS_RELAX_RELOC in alphabetic orderJiong Wang1-8/+8
2015-09-09[AArch64] Relax TLS local dynamic traditional into local executableJiong Wang1-0/+53
2015-08-31Make asection->id and asection->index unsignedAlan Modra1-2/+2
2015-08-19[AArch64][6/6] LD support TLSLD load/store relocation typesJiong Wang1-0/+16
2015-08-19[AArch64][5/6] GAS support TLSLD load/store relocation typesJiong Wang1-0/+120
2015-08-19[AArch64][4/6] LD support TLSLD move/add relocation typesJiong Wang1-0/+12
2015-08-19[AArch64][3/6] GAS support TLSLD move/add relocation typesJiong Wang1-0/+90
2015-08-19[AArch64][2/6] LD support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NCJiong Wang1-0/+2
2015-08-19[AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NCJiong Wang1-0/+15
2015-08-18[AArch64] Cleanup TLS relocation types which don't go through GOT tableJiong Wang1-37/+0
2015-08-18Add output_type to bfd_link_infoH.J. Lu1-36/+39
2015-08-11[AArch64] Improve BFD overflow warning message for -fpicJiong Wang1-0/+13
2015-08-11[AArch64]Speed up linking speed by skipping unncessary TLS reloc type checkJiong Wang1-1/+15
2015-08-11[AArch64] Long branch veneer support far symbol defined by --defsymJiong Wang1-2/+4
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