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By the look of it, git commit 39ff0b812324 broke 32-bit host
--enable-targets=all binutils builds.
/usr/local/bin/ld: ../opcodes/.libs/libopcodes.a(riscv-dis.o): in function `parse_riscv_dis_option':
/home/alan/src/binutils-gdb/opcodes/riscv-dis.c:102: undefined reference to `riscv_get_priv_spec_class'
collect2: error: ld returned 1 exit status
Makefile:925: recipe for target 'objdump' failed
The problem is that elfxx-riscv.c is not built for a 32-bit host
without --enable-64-bit-bfd or unless RISCV is given specifically as a
target. No such trimming of 64-bit only targets is done in opcodes.
One solution is to move these support functions to cpu-riscv.c, which
runs into "error: implicit declaration of function ‘xmalloc’". Now,
xmalloc is not supposed to be used in libbfd or libopcodes - it's rude
to crash out of an application that calls libbfd or libopcodes
functions without giving it a chance to deal with out-of-memory
itself. So I removed the xmalloc and instead used a fixed size
buffer. If you are worried about adding 36 bytes for the buffer to
the riscv_get_priv_spec_class_from_numbers stack frame size, then you
have no idea of the likely xmalloc + malloc stack frame size! Trying
to reduce memory usage is commendable, but in this instance
riscv_estimate_digit and malloc for a temp buffer uses a lot more
memory than a fixed max-size buffer.
* elfxx-riscv.c (struct priv_spec_t, priv_specs),
(riscv_get_priv_spec_class, riscv_get_priv_spec_class_from_numbers),
(riscv_get_priv_spec_name): Move to..
* cpu-riscv.c: ..here.
(riscv_get_priv_spec_class_from_numbers): Don't xmalloc temp buffer.
Use %u to print unsigned numbers.
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The following GDB behaviour was observed:
(gdb) x/1i 0x0001014a
0x1014a <main+8>: jal 0x10132 <foo>
(gdb) show architecture
The target architecture is set automatically (currently riscv:rv32)
(gdb) set architecture riscv:rv32
The target architecture is assumed to be riscv:rv32
(gdb) x/1i 0x0001014a
0x1014a <main+8>: 0x37e5
(gdb)
Notice that initially we can disassemble the instruction (it's a
compressed jal instruction), but after setting the architecture we can
no longer disassemble the instruction.
This is particularly puzzling as GDB initially thought the
architecture was 'riscv:rv32', but when we force the architecture to
be that, the disassembly stops working.
This issue was introduced with this commit:
commit c35d018b1a5ec604e49a807402c4205530b25ca8
Date: Mon Jan 27 15:19:30 2020 -0800
RISC-V: Fix gdbserver problem with handling arch strings.
In this commit we try to make riscv_scan handle cases where we see
architecture strings like 'riscv:rv32imc' (for example). Normally
this wouldn't match as bfd_default_scan requires an exact match, so we
extended riscv_scan to ignore trailing characters.
Unfortunately the default riscv arch is called 'riscv', is 64-bit,
and has its mach type set to 0, which I think is intended to pair with
code is riscv-dis.c:riscv_disassemble_insn that tries to guess if we
are 32 or 64 bit.
What happens then is that 'riscv:rv32' is first tested against 'riscv'
using bfd_default_scan, this doesn't match, we then compare this to
'riscv', but allowing trailing characters to be ignored, this matches,
and our 'riscv:rv32' matches against the default (64-bit)
architecture.
The solution I propose is to prevent the default architecture from
taking part in this "ignore trailing characters" extra match case,
only the more specific 'riscv:rv32' and 'riscv:rv64' get this extra
matching.
bfd/ChangeLog:
* cpu-riscv.c (riscv_scan): Don't allow shorter matches using the
default architecture.
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Maciej reported a problem found by his RISC-V gdbserver port.
warning: while parsing target description (at line 4): Target description specified unknown architecture "riscv:rv64id"
warning: Could not load XML target description; ignoring
We only have two arches defined, riscv:rv32 and riscv:rv64. Both bfd and
gdb are creating arch strings that have extension letters added to the base
architecture. The bfd_default_scan function requires an exact match, so
these strings fail to map to a bfd_arch. I think we should ignore the
extension letters in a RISC-V specific scan function.
bfd/
* cpu-riscv.c (riscv_scan): New.
(N): Change bfd_default_scan to riscv_scan.
Change-Id: I096476705e1da5cb8934c5005b1eed2a8989f7a7
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applies to the middle of the next insn.
PR 24907
binutils* objdump.c (null_print): New function.
(disassemble_bytes): Delete previous_octets local and replace with
a test of the max_reloc_offset_into_insn field of the
bfd_arch_info structure. If a reloc is a potential match for the
next insn, then perform a dummy disassembly in order to calculate
its real length.
bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn
field.
(bfd_default_arch_struct): Initialise the new field.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c: Initialise the new field.
* cpu-alpha.c: Likewise.
* cpu-arc.c: Likewise.
* cpu-arm.c: Likewise.
* cpu-avr.c: Likewise.
* cpu-bfin.c: Likewise.
* cpu-bpf.c: Likewise.
* cpu-cr16.c: Likewise.
* cpu-cr16c.c: Likewise.
* cpu-cris.c: Likewise.
* cpu-crx.c: Likewise.
* cpu-csky.c: Likewise.
* cpu-d10v.c: Likewise.
* cpu-d30v.c: Likewise.
* cpu-dlx.c: Likewise.
* cpu-epiphany.c: Likewise.
* cpu-fr30.c: Likewise.
* cpu-frv.c: Likewise.
* cpu-ft32.c: Likewise.
* cpu-h8300.c: Likewise.
* cpu-hppa.c: Likewise.
* cpu-i386.c: Likewise.
* cpu-ia64.c: Likewise.
* cpu-iamcu.c: Likewise.
* cpu-ip2k.c: Likewise.
* cpu-iq2000.c: Likewise.
* cpu-k1om.c: Likewise.
* cpu-l1om.c: Likewise.
* cpu-lm32.c: Likewise.
* cpu-m10200.c: Likewise.
* cpu-m10300.c: Likewise.
* cpu-m32c.c: Likewise.
* cpu-m32r.c: Likewise.
* cpu-m68hc11.c: Likewise.
* cpu-m68hc12.c: Likewise.
* cpu-m68k.c: Likewise.
* cpu-m9s12x.c: Likewise.
* cpu-m9s12xg.c: Likewise.
* cpu-mcore.c: Likewise.
* cpu-mep.c: Likewise.
* cpu-metag.c: Likewise.
* cpu-microblaze.c: Likewise.
* cpu-mips.c: Likewise.
* cpu-mmix.c: Likewise.
* cpu-moxie.c: Likewise.
* cpu-msp430.c: Likewise.
* cpu-mt.c: Likewise.
* cpu-nds32.c: Likewise.
* cpu-nfp.c: Likewise.
* cpu-nios2.c: Likewise.
* cpu-ns32k.c: Likewise.
* cpu-or1k.c: Likewise.
* cpu-pdp11.c: Likewise.
* cpu-pj.c: Likewise.
* cpu-plugin.c: Likewise.
* cpu-powerpc.c: Likewise.
* cpu-pru.c: Likewise.
* cpu-riscv.c: Likewise.
* cpu-rl78.c: Likewise.
* cpu-rs6000.c: Likewise.
* cpu-rx.c: Likewise.
* cpu-s12z.c: Likewise.
* cpu-s390.c: Likewise.
* cpu-score.c: Likewise.
* cpu-sh.c: Likewise.
* cpu-sparc.c: Likewise.
* cpu-spu.c: Likewise.
* cpu-tic30.c: Likewise.
* cpu-tic4x.c: Likewise.
* cpu-tic54x.c: Likewise.
* cpu-tic6x.c: Likewise.
* cpu-tic80.c: Likewise.
* cpu-tilegx.c: Likewise.
* cpu-tilepro.c: Likewise.
* cpu-v850.c: Likewise.
* cpu-v850_rh850.c: Likewise.
* cpu-vax.c: Likewise.
* cpu-visium.c: Likewise.
* cpu-wasm32.c: Likewise.
* cpu-xc16x.c: Likewise.
* cpu-xgate.c: Likewise.
* cpu-xstormy16.c: Likewise.
* cpu-xtensa.c: Likewise.
* cpu-z80.c: Likewise.
* cpu-z8k.c: Likewise.
gas * testsuite/gas/arm/pr24907.s: New test.
* testsuite/gas/arm/pr24907.d: Expected disassembly.
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bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf.
* config.bdf: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* archures.c: Add bfd_riscv_arch.
* reloc.c: Add riscv relocs.
* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
* elfnn-riscv.c: New file.
* elfxx-riscv.c: New file.
* elfxx-riscv.h: New file.
binutils* readelf.c (guess_is_rela): Add EM_RISCV.
(get_machine_name): Likewise.
(dump_relocations): Add support for riscv relocations.
(get_machine_flags): Add support for riscv flags.
(is_32bit_abs_reloc): Add R_RISCV_32.
(is_64bit_abs_reloc): Add R_RISCV_64.
(is_none_reloc): Add R_RISCV_NONE.
* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
Expect the debug_ranges test to fail.
gas * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this architecture.
* configure.in: Define a default architecture.
* configure: Regenerate.
* configure.tgt: Add entries for riscv.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
* config/tc-riscv.c: New file.
* config/tc-riscv.h: New file.
* doc/c-riscv.texi: New file.
* testsuite/gas/riscv: New directory.
* testsuite/gas/riscv/riscv.exp: New file.
* testsuite/gas/riscv/t_insns.d: New file.
* testsuite/gas/riscv/t_insns.s: New file.
ld * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this target.
* configure.tgt: Add riscv entries.
* emulparams/elf32lriscv-defs.sh: New file.
* emulparams/elf32lriscv.sh: New file.
* emulparams/elf64lriscv-defs.sh: New file.
* emulparams/elf64lriscv.sh: New file.
* emultempl/riscvelf.em: New file.
opcodes * configure.ac: Add entry for bfd_riscv_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add support for riscv.
(disassembler_usage): Likewise.
* riscv-dis.c: New file.
* riscv-opc.c: New file.
include * dis-asm.h: Add prototypes for print_insn_riscv and
print_riscv_disassembler_options.
* elf/riscv.h: New file.
* opcode/riscv-opc.h: New file.
* opcode/riscv.h: New file.
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