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path: root/bfd/cpu-powerpc.c
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2019-09-10Enhance the disassembler so that it will reliably determine whether a reloc ↵Nick Clifton1-351/+50
applies to the middle of the next insn. PR 24907 binutils* objdump.c (null_print): New function. (disassemble_bytes): Delete previous_octets local and replace with a test of the max_reloc_offset_into_insn field of the bfd_arch_info structure. If a reloc is a potential match for the next insn, then perform a dummy disassembly in order to calculate its real length. bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn field. (bfd_default_arch_struct): Initialise the new field. * bfd-in2.h: Regenerate. * cpu-aarch64.c: Initialise the new field. * cpu-alpha.c: Likewise. * cpu-arc.c: Likewise. * cpu-arm.c: Likewise. * cpu-avr.c: Likewise. * cpu-bfin.c: Likewise. * cpu-bpf.c: Likewise. * cpu-cr16.c: Likewise. * cpu-cr16c.c: Likewise. * cpu-cris.c: Likewise. * cpu-crx.c: Likewise. * cpu-csky.c: Likewise. * cpu-d10v.c: Likewise. * cpu-d30v.c: Likewise. * cpu-dlx.c: Likewise. * cpu-epiphany.c: Likewise. * cpu-fr30.c: Likewise. * cpu-frv.c: Likewise. * cpu-ft32.c: Likewise. * cpu-h8300.c: Likewise. * cpu-hppa.c: Likewise. * cpu-i386.c: Likewise. * cpu-ia64.c: Likewise. * cpu-iamcu.c: Likewise. * cpu-ip2k.c: Likewise. * cpu-iq2000.c: Likewise. * cpu-k1om.c: Likewise. * cpu-l1om.c: Likewise. * cpu-lm32.c: Likewise. * cpu-m10200.c: Likewise. * cpu-m10300.c: Likewise. * cpu-m32c.c: Likewise. * cpu-m32r.c: Likewise. * cpu-m68hc11.c: Likewise. * cpu-m68hc12.c: Likewise. * cpu-m68k.c: Likewise. * cpu-m9s12x.c: Likewise. * cpu-m9s12xg.c: Likewise. * cpu-mcore.c: Likewise. * cpu-mep.c: Likewise. * cpu-metag.c: Likewise. * cpu-microblaze.c: Likewise. * cpu-mips.c: Likewise. * cpu-mmix.c: Likewise. * cpu-moxie.c: Likewise. * cpu-msp430.c: Likewise. * cpu-mt.c: Likewise. * cpu-nds32.c: Likewise. * cpu-nfp.c: Likewise. * cpu-nios2.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-or1k.c: Likewise. * cpu-pdp11.c: Likewise. * cpu-pj.c: Likewise. * cpu-plugin.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-pru.c: Likewise. * cpu-riscv.c: Likewise. * cpu-rl78.c: Likewise. * cpu-rs6000.c: Likewise. * cpu-rx.c: Likewise. * cpu-s12z.c: Likewise. * cpu-s390.c: Likewise. * cpu-score.c: Likewise. * cpu-sh.c: Likewise. * cpu-sparc.c: Likewise. * cpu-spu.c: Likewise. * cpu-tic30.c: Likewise. * cpu-tic4x.c: Likewise. * cpu-tic54x.c: Likewise. * cpu-tic6x.c: Likewise. * cpu-tic80.c: Likewise. * cpu-tilegx.c: Likewise. * cpu-tilepro.c: Likewise. * cpu-v850.c: Likewise. * cpu-v850_rh850.c: Likewise. * cpu-vax.c: Likewise. * cpu-visium.c: Likewise. * cpu-wasm32.c: Likewise. * cpu-xc16x.c: Likewise. * cpu-xgate.c: Likewise. * cpu-xstormy16.c: Likewise. * cpu-xtensa.c: Likewise. * cpu-z80.c: Likewise. * cpu-z8k.c: Likewise. gas * testsuite/gas/arm/pr24907.s: New test. * testsuite/gas/arm/pr24907.d: Expected disassembly.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-06BFD whitespace fixesAlan Modra1-27/+27
Binutils is supposed to use tabs. In my git config I have whitespace = indent-with-non-tab,space-before-tab,trailing-space and I got annoyed enough seeing red in "git diff" output to fix the problems. * doc/header.sed: Trim trailing space when splitting lines. * aix386-core.c, * aout-adobe.c, * aout-arm.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h, * aout-tic30.c, * aoutf1.h, * aoutx.h, * arc-got.h, * arc-plt.def, * arc-plt.h, * archive.c, * archive64.c, * archures.c, * armnetbsd.c, * bfd-in.h, * bfd.c, * bfdio.c, * binary.c, * bout.c, * cache.c, * cisco-core.c, * coff-alpha.c, * coff-apollo.c, * coff-arm.c, * coff-h8300.c, * coff-i386.c, * coff-i860.c, * coff-i960.c, * coff-m68k.c, * coff-m88k.c, * coff-mcore.c, * coff-mips.c, * coff-ppc.c, * coff-rs6000.c, * coff-sh.c, * coff-stgo32.c, * coff-tic4x.c, * coff-tic54x.c, * coff-tic80.c, * coff-we32k.c, * coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * coffswap.h, * compress.c, * corefile.c, * cpu-alpha.c, * cpu-arm.c, * cpu-avr.c, * cpu-bfin.c, * cpu-cr16.c, * cpu-cr16c.c, * cpu-crx.c, * cpu-d10v.c, * cpu-frv.c, * cpu-ft32.c, * cpu-i370.c, * cpu-i960.c, * cpu-ia64-opc.c, * cpu-ip2k.c, * cpu-lm32.c, * cpu-m32r.c, * cpu-mcore.c, * cpu-microblaze.c, * cpu-mips.c, * cpu-moxie.c, * cpu-mt.c, * cpu-nios2.c, * cpu-ns32k.c, * cpu-or1k.c, * cpu-powerpc.c, * cpu-pru.c, * cpu-sh.c, * cpu-spu.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-xgate.c, * cpu-z80.c, * dwarf1.c, * dwarf2.c, * ecoff.c, * ecofflink.c, * ecoffswap.h, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h, * elf-m10200.c, * elf-m10300.c, * elf-s390-common.c, * elf-strtab.c, * elf-vxworks.c, * elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-i860.c, * elf32-i960.c, * elf32-ip2k.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c, * elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c, * elf32-m88k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-mips.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nds32.h, * elf32-nios2.c, * elf32-or1k.c, * elf32-pj.c, * elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score.h, * elf32-score7.c, * elf32-sh-symbian.c, * elf32-sh.c, * elf32-sh64.c, * elf32-sparc.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilegx.c, * elf32-tilegx.h, * elf32-tilepro.c, * elf32-tilepro.h, * elf32-v850.c, * elf32-vax.c, * elf32-wasm32.c, * elf32-xc16x.c, * elf32-xgate.c, * elf32-xgate.h, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sh64.c, * elf64-sparc.c, * elf64-tilegx.c, * elf64-tilegx.h, * elf64-x86-64.c, * elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h, * elfxx-mips.c, * elfxx-riscv.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * elfxx-x86.h, * freebsd.h, * hash.c, * host-aout.c, * hp300hpux.c, * hppabsd-core.c, * hpux-core.c, * i386aout.c, * i386linux.c, * i386lynx.c, * i386mach3.c, * i386msdos.c, * i386netbsd.c, * ieee.c, * ihex.c, * irix-core.c, * libaout.h, * libbfd-in.h, * libbfd.c, * libcoff-in.h, * libnlm.h, * libpei.h, * libxcoff.h, * linker.c, * lynx-core.c, * m68k4knetbsd.c, * m68klinux.c, * m68knetbsd.c, * m88kmach3.c, * mach-o-aarch64.c, * mach-o-arm.c, * mach-o-i386.c, * mach-o-target.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h, * merge.c, * mipsbsd.c, * mmo.c, * netbsd.h, * netbsd-core.c, * newsos3.c, * nlm-target.h, * nlm32-ppc.c, * nlm32-sparc.c, * nlmcode.h, * ns32k.h, * ns32knetbsd.c, * oasys.c, * opncls.c, * pc532-mach.c, * pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-mips.c, * pe-x86_64.c, * peXXigen.c, * pef.c, * pef.h, * pei-arm.c, * pei-i386.c, * pei-mcore.c, * pei-x86_64.c, * peicode.h, * plugin.c, * ppcboot.c, * ptrace-core.c, * reloc.c, * riscix.c, * rs6000-core.c, * section.c, * som.c, * som.h, * sparclinux.c, * sparcnetbsd.c, * srec.c, * stabs.c, * sunos.c, * syms.c, * targets.c, * tekhex.c, * trad-core.c, * vax1knetbsd.c, * vaxnetbsd.c, * verilog.c, * versados.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * wasm-module.c, * wasm-module.h, * xcofflink.c, * xsym.c, * xsym.h: Whitespace fixes. * bfd-in2.h, * libbfd.h, * libcoff.h: Regenerate.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-06-07PowerPC VLEAlan Modra1-0/+4
VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-03-05Update copyright yearsAlan Modra1-2/+1
2012-07-13 * aix386-core.c: Remove use of PTR and PARAMS macros.Nick Clifton1-6/+2
* archive.c: Likewise. * cache.c: Likewise. * cisco-core.c: Likewise. * coff-alpha.c: Likewise. * coff-apollo.c: Likewise. * coff-aux.c: Likewise. * coff-h8300.c: Likewise. * coff-h8500.c: Likewise. * coff-i386.c: Likewise. * coff-i960.c: Likewise. * coff-ia64.c: Likewise. * coff-m68k.c: Likewise. * coff-m88k.c: Likewise. * coff-mcore.c: Likewise. * coff-mips.c: Likewise. * coff-or32.c: Likewise. * coff-ppc.c: Likewise. * coff-rs6000.c: Likewise. * coff-sh.c: Likewise. * coff-sparc.c: Likewise. * coff-stgo32.c: Likewise. * coff-tic30.c: Likewise. * coff-tic4x.c: Likewise. * coff-tic54x.c: Likewise. * coff-tic80.c: Likewise. * coff-w65.c: Likewise. * cofflink.c: Likewise. * cpu-arc.c: Likewise. * cpu-cris.c: Likewise. * cpu-h8500.c: Likewise. * cpu-i960.c: Likewise. * cpu-msp430.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-rs6000.c: Likewise. * cpu-tic4x.c: Likewise. * cpu-w65.c: Likewise. * ecoff.c: Likewise. * ecofflink.c: Likewise. * elf-m10200.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cris.c: Likewise. * elf32-crx.c: Likewise. * elf32-fr30.c: Likewise. * elf32-frv.c: Likewise. * elf32-h8300.c: Likewise. * elf32-i960.c: Likewise. * elf32-m32c.c: Likewise. * elf32-m68hc11.c: Likewise. * elf32-m68hc12.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-m68k.c: Likewise. * elf32-mcore.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-vax.c: Likewise. * elf64-alpha.c: Likewise. * elf64-mmix.c: Likewise. * elf64-s390.c: Likewise. * elf64-sparc.c: Likewise. * elfnn-ia64.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * hash.c: Likewise. * hp300hpux.c: Likewise. * hppabsd-core.c: Likewise. * hpux-core.c: Likewise. * i386dynix.c: Likewise. * i386linux.c: Likewise. * i386lynx.c: Likewise. * i386mach3.c: Likewise. * i386msdos.c: Likewise. * i386os9k.c: Likewise. * irix-core.c: Likewise. * lynx-core.c: Likewise. * m68klinux.c: Likewise. * mach-o.h: Likewise. * mipsbsd.c: Likewise. * netbsd-core.c: Likewise. * nlm32-i386.c: Likewise. * osf-core.c: Likewise. * pc532-mach.c: Likewise. * pef.c: Likewise. * ppcboot.c: Likewise. * ptrace-core.c: Likewise. * reloc16.c: Likewise. * sco5-core.c: Likewise. * som.h: Likewise. * sparclinux.c: Likewise. * sparclynx.c: Likewise. * ticoff.h: Likewise. * trad-core.c: Likewise. * vms-lib.c: Likewise. * xsym.h: Likewise.
2012-05-14Add support for PowerPC VLE.James Lemke1-1/+16
2012-05-14 Catherine Moore <clm@codesourcery.com> * NEWS: Mention PowerPC VLE port. 2012-05-14 James Lemke <jwlemke@codesourcery.com> Catherine Moore <clm@codesourcery.com> bfd/ * bfd.c (bfd_lookup_section_flags): Add section parm. * ecoff.c (bfd_debug_section): Remove flag_info initializer. * elf-bfd.h (bfd_elf_section_data): Move in section_flag_info. (bfd_elf_lookup_section_flags): Add section parm. * elf32-ppc.c (is_ppc_vle): New function. (ppc_elf_modify_segment_map): New function. (elf_backend_modify_segment_map): Define. (has_vle_insns): New define. * elf32-ppc.h (ppc_elf_modify_segment_map): Declare. * elflink.c (bfd_elf_lookup_section_flags): Add return value & parm. Move in logic to omit / include a section. * libbfd-in.h (bfd_link_info): Add section parm. (bfd_generic_lookup_section_flags): Likewise. * reloc.c (bfd_generic_lookup_section_flags): Likewise. * section.c (bfd_section): Move out section_flag_info. (BFD_FAKE_SECTION): Remove flag_info initializer. * targets.c (_bfd_lookup_section_flags): Add section parm. 2012-05-14 Catherine Moore <clm@codesourcery.com> bfd/ * archures.c (bfd_mach_ppc_vle): New. * bfd-in2.h: Regenerated. * cpu-powerpc.c (bfd_powerpc_archs): New entry for vle. * elf32-ppc.c (split16_format_type): New enumeration. (ppc_elf_vle_split16): New function. (HOWTO): Add entries for R_PPC_VLE relocations. (ppc_elf_reloc_type_lookup): Handle PPC_VLE relocations. (ppc_elf_section_flags): New function. (ppc_elf_lookup_section_flags): New function. (ppc_elf_section_processing): New function. (ppc_elf_check_relocs): Handle PPC_VLE relocations. (ppc_elf_relocation_section): Likewise. (elf_backend_lookup_section_flags_hook): Define. (elf_backend_section_flags): Define. (elf_backend_section_processing): Define. * elf32-ppc.h (ppc_elf_section_processing): Declare. * libbfd.h: Regenerated. * reloc.c (BFD_RELOC_PPC_VLE_REL8, BFD_RELOC_PPC_VLE_REL15, BFD_RELOC_PPC_VLE_REL24, BFD_RELOC_PPC_VLE_LO16A, BFD_RELOC_PPC_VLE_LO16D, BFD_RELOC_PPC_VLE_HI16A, BFD_RELOC_PPC_VLE_HI16D, BFD_RELOC_PPC_VLE_HA16A, BFD_RELOC_PPC_VLE_HA16D, BFD_RELOC_PPC_VLE_SDA21, BFD_RELOC_PPC_VLE_SDA21_LO, BFD_RELOC_PPC_VLE_SDAREL_LO16A, BFD_RELOC_PPC_VLE_SDAREL_LO16D, BFD_RELOC_PPC_VLE_SDAREL_HI16A, BFD_RELOC_PPC_VLE_SDAREL_HI16D, BFD_RELOC_PPC_VLE_SDAREL_HA16A, BFD_RELOC_PPC_VLE_SDAREL_HA16D): New bfd relocations. 2012-05-14 James Lemke <jwlemke@codesourcery.com> gas/ * config/tc-ppc.c (insn_validate): New func of existing code to call.. (ppc_setup_opcodes): ..from 2 places here. Revise for second (VLE) opcode table. Add #ifdef'd code to print opcode tables. 2012-05-14 James Lemke <jwlemke@codesourcery.com> gas/ * config/tc-ppc.c (ppc_setup_opcodes): Allow out-of-order for the VLE conditional branches. 2012-05-14 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Rhonda Wittels <rhonda@codesourcery.com> gas/ * config/tc-ppc.c (PPC_VLE_SPLIT16A): New macro. (PPC_VLE_SPLIT16D): New macro. (PPC_VLE_LO16A): New macro. (PPC_VLE_LO16D): New macro. (PPC_VLE_HI16A): New macro. (PPC_VLE_HI16D): New macro. (PPC_VLE_HA16A): New macro. (PPC_VLE_HA16D): New macro. (PPC_APUINFO_VLE): New definition. (md_chars_to_number): New function. (md_parse_option): Check for combinations of little endian and -mvle. (md_show_usage): Document -mvle. (ppc_arch): Recognize VLE. (ppc_mach): Recognize bfd_mach_ppc_vle. (ppc_setup_opcodes): Print the opcode table if * config/tc-ppc.h (ppc_frag_check): Declare. * doc/c-ppc.texi: Document -mvle. * NEWS: Mention PowerPC VLE port. 2012-05-14 Catherine Moore <clm@codesourcery.com> gas/ * config/tc-ppc.h (ppc_dw2_line_min_insn_length): Declare. (DWARF2_LINE_MIN_INSN_LENGTH): Redefine. * config/tc-ppc.c (ppc_dw2_line_min_insn_length): New. * dwarf2dbg.c (scale_addr_delta): Handle values of 1 for DWARF2_LINE_MIN_INSN_LENGTH. 2012-05-14 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Rhonda Wittels <rhonda@codesourcery.com> gas/testsuite/ * gas/ppc/ppc.exp: Run new tests. * gas/ppc/vle-reloc.d: New test. * gas/ppc/vle-reloc.s: New test. * gas/ppc/vle-simple-1.d: New test. * gas/ppc/vle-simple-1.s: New test. * gas/ppc/vle-simple-2.d: New test. * gas/ppc/vle-simple-2.s: New test. * gas/ppc/vle-simple-3.d: New test. * gas/ppc/vle-simple-3.s: New test. * gas/ppc/vle-simple-4.d: New test. * gas/ppc/vle-simple-4.s: New test. * gas/ppc/vle-simple-5.d: New test. * gas/ppc/vle-simple-5.s: New test. * gas/ppc/vle-simple-6.d: New test. * gas/ppc/vle-simple-6.s: New test. * gas/ppc/vle.d: New test. * gas/ppc/vle.s: New test. 2012-05-14 James Lemke <jwlemke@codesourcery.com> include/elf/ * ppc.h (SEC_PPC_VLE): Remove. 2012-05-14 Catherine Moore <clm@codesourcery.com> James Lemke <jwlemke@codesourcery.com> include/elf/ * ppc.h (R_PPC_VLE_REL8): New reloction. (R_PPC_VLE_REL15): Likewise. (R_PPC_VLE_REL24): Likewise. (R_PPC_VLE_LO16A): Likewise. (R_PPC_VLE_LO16D): Likewise. (R_PPC_VLE_HI16A): Likewise. (R_PPC_VLE_HI16D): Likewise. (R_PPC_VLE_HA16A): Likewise. (R_PPC_VLE_HA16D): Likewise. (R_PPC_VLE_SDA21): Likewise. (R_PPC_VLE_SDA21_LO): Likewise. (R_PPC_VLE_SDAREL_LO16A): Likewise. (R_PPC_VLE_SDAREL_LO16D): Likewise. (R_PPC_VLE_SDAREL_HI16A): Likewise. (R_PPC_VLE_SDAREL_HI16D): Likewise. (R_PPC_VLE_SDAREL_HA16A): Likewise. (R_PPC_VLE_SDAREL_HA16D): Likewise. (SEC_PPC_VLE): Remove. (PF_PPC_VLE): New program header flag. (SHF_PPC_VLE): New section header flag. (vle_opcodes, vle_num_opcodes): New. (VLE_OP): New macro. (VLE_OP_TO_SEG): New macro. 2012-05-14 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Rhonda Wittels <rhonda@codesourcery.com> include/opcode/ * ppc.h (PPC_OPCODE_VLE): New definition. (PPC_OP_SA): New macro. (PPC_OP_SE_VLE): New macro. (PPC_OP): Use a variable shift amount. (powerpc_operand): Update comments. (PPC_OPSHIFT_INV): New macro. (PPC_OPERAND_CR): Replace with... (PPC_OPERAND_CR_BIT): ...this and (PPC_OPERAND_CR_REG): ...this. 2012-05-14 James Lemke <jwlemke@codesourcery.com> ld/ * ldlang.c (walk_wild_consider_section): Don't copy section_flag_list. Pass it to callback. (walk_wild_section_general): Pass section_flag_list to callback. (lang_add_section): Add sflag_list parm. Move out logic to keep / omit a section & call bfd_lookup_section_flags. (output_section_callback_fast): Add sflag_list parm. Add new parm to lang_add_section calls. (output_section_callback): Likewise. (check_section_callback): Add sflag_list parm. (lang_place_orphans): Add new parm to lang_add_section calls. (gc_section_callback): Add sflag_list parm. (find_relro_section_callback): Likewise. * ldlang.h (callback_t): Add flag_info parm. (lang_add_section): Add sflag_list parm. * emultempl/armelf.em (elf32_arm_add_stub_section): Add lang_add_section parm. * emultempl/beos.em (gld*_place_orphan): Likewise. * emultempl/elf32.em (gld*_place_orphan): Likewise. * emultempl/hppaelf.em (hppaelf_add_stub_section): Likewise. * emultempl/m68hc1xelf.em (m68hc11elf_add_stub_section): Likewise. * emultempl/mipself.em (mips_add_stub_section): Likewise. * emultempl/mmo.em (mmo_place_orphan): Likewise. * emultempl/pe.em (gld_*_place_orphan): Likewise. * emultempl/pep.em (gld_*_place_orphan): Likewise. * emultempl/ppc64elf.em (ppc_add_stub_section): Likewise. * emultempl/spuelf.em (spu_place_special_section): Likewise. * emultempl/vms.em (vms_place_orphan): Likewise. 2012-05-14 James Lemke <jwlemke@codesourcery.com> ld/testsuite/ * ld-powerpc/powerpc.exp: Create ppceabitests. * ld-powerpc/vle-multiseg.s: New. * ld-powerpc/vle-multiseg-1.d: New. * ld-powerpc/vle-multiseg-1.ld: New. * ld-powerpc/vle-multiseg-2.d: New. * ld-powerpc/vle-multiseg-2.ld: New. * ld-powerpc/vle-multiseg-3.d: New. * ld-powerpc/vle-multiseg-3.ld: New. * ld-powerpc/vle-multiseg-4.d: New. * ld-powerpc/vle-multiseg-4.ld: New. * ld-powerpc/vle-multiseg-5.d: New. * ld-powerpc/vle-multiseg-5.ld: New. * ld-powerpc/vle-multiseg-6.d: New. * ld-powerpc/vle-multiseg-6.ld: New. * ld-powerpc/vle-multiseg-6a.s: New. * ld-powerpc/vle-multiseg-6b.s: New. * ld-powerpc/vle-multiseg-6c.s: New. * ld-powerpc/vle-multiseg-6d.s: New. * ld-powerpc/powerpc.exp: Run new tests. 2012-05-14 Catherine Moore <clm@codesourcery.com> ld/ * NEWS: Mention PowerPC VLE port. 2012-05-14 Catherine Moore <clm@codesourcery.com> ld/testsuite/ * ld-powerpc/apuinfo.rd: Update for VLE. * ld-powerpc/vle-reloc-1.d: New. * ld-powerpc/vle-reloc-1.s: New. * ld-powerpc/vle-reloc-2.d: New. * ld-powerpc/vle-reloc-2.s: New. * ld-powerpc/vle-reloc-3.d: New. * ld-powerpc/vle-reloc-3.s: New. * ld-powerpc/vle-reloc-def-1.s: New. * ld-powerpc/vle-reloc-def-2.s: New. * ld-powerpc/vle-reloc-def-3.s: New. 2012-05-14 James Lemke <jwlemke@codesourcery.com> opcodes/ * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle. (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines. (vle_opcd_indices): New array. (lookup_vle): New function. (disassemble_init_powerpc): Revise for second (VLE) opcode table. (print_insn_powerpc): Likewise. * ppc-opc.c: Likewise. 2012-05-14 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Rhonda Wittels <rhonda@codesourcery.com> Nathan Froyd <froydnj@codesourcery.com> opcodes/ * ppc-opc.c (insert_arx, extract_arx): New functions. (insert_ary, extract_ary): New functions. (insert_li20, extract_li20): New functions. (insert_rx, extract_rx): New functions. (insert_ry, extract_ry): New functions. (insert_sci8, extract_sci8): New functions. (insert_sci8n, extract_sci8n): New functions. (insert_sd4h, extract_sd4h): New functions. (insert_sd4w, extract_sd4w): New functions. (insert_vlesi, extract_vlesi): New functions. (insert_vlensi, extract_vlensi): New functions. (insert_vleui, extract_vleui): New functions. (insert_vleil, extract_vleil): New functions. (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT. (BI16, BI32, BO32, B8): New. (B15, B24, CRD32, CRS): New. (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG. (DB, IMM20, RD, Rx, ARX, RY, RZ): New. (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New. (SH6_MASK): Use PPC_OPSHIFT_INV. (SI8, UI5, OIMM5, UI7, BO16): New. (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New. (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV. (ALLOW8_SPRG): New. (insert_sprg, extract_sprg): Check ALLOW8_SPRG. (OPVUP, OPVUP_MASK OPVUP): New (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New. (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New. (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New. (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New. (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New. (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New. (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New. (SE_IM5, SE_IM5_MASK): New. (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New. (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New. (BO32DNZ, BO32DZ): New. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE. (PPCVLE): New. (powerpc_opcodes): Add new VLE instructions. Update existing instruction to include PPCVLE if supported. * ppc-dis.c (ppc_opts): Add vle entry. (get_powerpc_dialect): New function. (powerpc_init_dialect): VLE support. (print_insn_big_powerpc): Call get_powerpc_dialect. (print_insn_little_powerpc): Likewise. (operand_value_powerpc): Handle negative shift counts. (print_insn_powerpc): Handle 2-byte instruction lengths.
2012-03-09include/opcode/Alan Modra1-2/+32
* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. (PPCVEC2, PPCTMR, E6500): New short names. (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC optional operands on sync instruction for E6500 target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entryies for bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ * config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500. (ppc_handle_align): Add termination nop opcode for e500mc family. * doc/as.texinfo: Document options -me5500 and -me6500. * doc/c-ppc.texi: Likewise. gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test case for e500mc family termination nops. * gas/ppc/e500mc64_nop.d: Likewise. * gas/ppc/e5500_nop.s: Likewise. * gas/ppc/e5500_nop.d: Likewise. * gas/ppc/e6500_nop.s: Likewise. * gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s: New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
2012-01-31Support arch-dependent fillH.J. Lu1-0/+21
bfd/ 2012-01-31 H.J. Lu <hongjiu.lu@intel.com> PR ld/13616 * archures.c (bfd_arch_info): Add fill. (bfd_default_arch_struct): Add bfd_arch_default_fill. (bfd_arch_default_fill): New. * configure.in: Set bfd version to 2.22.52. * configure: Regenerated. * cpu-alpha.c: Add bfd_arch_default_fill to bfd_arch_info initializer. * cpu-arc.c: Likewise. * cpu-arm.c: Likewise. * cpu-avr.c: Likewise. * cpu-bfin.c: Likewise. * cpu-cr16.c: Likewise. * cpu-cr16c.c: Likewise. * cpu-cris.c: Likewise. * cpu-crx.c: Likewise. * cpu-d10v.c: Likewise. * cpu-d30v.c: Likewise. * cpu-dlx.c: Likewise. * cpu-epiphany.c: Likewise. * cpu-fr30.c: Likewise. * cpu-frv.c: Likewise. * cpu-h8300.c: Likewise. * cpu-h8500.c: Likewise. * cpu-hppa.c: Likewise. * cpu-i370.c: Likewise. * cpu-i860.c: Likewise. * cpu-i960.c: Likewise. * cpu-ia64.c: Likewise. * cpu-ip2k.c: Likewise. * cpu-iq2000.c: Likewise. * cpu-lm32.c: Likewise. * cpu-m10200.c: Likewise. * cpu-m10300.c: Likewise. * cpu-m32c.c: Likewise. * cpu-m32r.c: Likewise. * cpu-m68hc11.c: Likewise. * cpu-m68hc12.c: Likewise. * cpu-m68k.c: Likewise. * cpu-m88k.c: Likewise. * cpu-mcore.c: Likewise. * cpu-mep.c: Likewise. * cpu-microblaze.c: Likewise. * cpu-mips.c: Likewise. * cpu-mmix.c: Likewise. * cpu-moxie.c: Likewise. * cpu-msp430.c: Likewise. * cpu-mt.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-openrisc.c: Likewise. * cpu-or32.c: Likewise. * cpu-pdp11.c: Likewise. * cpu-pj.c: Likewise. * cpu-plugin.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-rl78.c: Likewise. * cpu-rs6000.c: Likewise. * cpu-rx.c: Likewise. * cpu-s390.c: Likewise. * cpu-score.c: Likewise. * cpu-sh.c: Likewise. * cpu-sparc.c: Likewise. * cpu-spu.c: Likewise. * cpu-tic30.c: Likewise. * cpu-tic4x.c: Likewise. * cpu-tic54x.c: Likewise. * cpu-tic6x.c: Likewise. * cpu-tic80.c: Likewise. * cpu-tilegx.c: Likewise. * cpu-tilepro.c: Likewise. * cpu-v850.c: Likewise. * cpu-vax.c: Likewise. * cpu-w65.c: Likewise. * cpu-we32k.c: Likewise. * cpu-xc16x.c: Likewise. * cpu-xstormy16.c: Likewise. * cpu-xtensa.c: Likewise. * cpu-z80.c: Likewise. * cpu-z8k.c: Likewise. * cpu-i386.c: Include "libiberty.h". (bfd_arch_i386_fill): New. Add bfd_arch_i386_fill to bfd_arch_info initializer. * cpu-k1om.c: Add bfd_arch_i386_fill to bfd_arch_info initializer. * cpu-l1om.c: Likewise. * linker.c (default_data_link_order): Call abfd->arch_info->fill if fill size is 0. * bfd-in2.h: Regenerated. include/ 2012-01-31 H.J. Lu <hongjiu.lu@intel.com> PR ld/13616 * bfdlink.h (bfd_link_order): Update comments on data size. ld/ 2012-01-31 H.J. Lu <hongjiu.lu@intel.com> PR ld/13616 * emulparams/elf32_x86_64.sh: Remove NOP. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_i386_be.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * ldlang.c (zero_fill): Initialized to 0. * ldwrite.c (build_link_order): Set data size to linker odrder size when they are the same. * scripttempl/elf.sc: Don't specify fill if NOP is undefined. ld/testsuite/ 2012-01-31 H.J. Lu <hongjiu.lu@intel.com> PR ld/13616 * ld-i386/tlsbindesc.dd: Update no-op padding. * ld-i386/tlsnopic.dd: Likewise. * ld-i386/tlspic.dd: Likewise. * ld-x86-64/tlsbin.dd: Likewise. * ld-x86-64/tlsbindesc.dd: Likewise. * ld-x86-64/tlspic.dd: Likewise.
2010-02-08include/Alan Modra1-0/+14
* opcode/ppc.h (PPC_OPCODE_TITAN): Define. bfd/ * archures.c (bfd_mach_ppc_titan): Define. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add titan entry. opcodes/ * ppc-dis.c (ppc_opts): Add titan entry. * ppc-opc.c (TITAN, MULHW): Define. (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). gas/ * config/tc-ppc.c (md_show_usage): Mention -mtitan. Don't use tabs. (ppc_mach): Handle titan. * doc/c-ppc.texi: Mention -mtitan. gas/testsuite/ * gas/ppc/titan.d, * gas/ppc/titan.s: New test. * gas/ppc/ppc.exp: Run it.
2010-01-04bfd/Alan Modra1-2/+16
* archures.c: Add bfd_mach_ppc_e500mc64. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entry for bfd_mach_ppc_e500mc64. gas/ * config/tc-ppc.c (md_show_usage): Document -me500mc64. opcodes/ * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
2009-09-02update copyright datesAlan Modra1-1/+1
2008-04-30missed from 20080414 commit for e500mc supportAlan Modra1-2/+16
2007-07-03Switch sources over to use the GPL version 3Nick Clifton1-12/+13
2007-04-26bfd/Alan Modra1-2/+2
Many files: Include sysdep.h before bfd.h. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. binutils/ * bucumm.h: Split off host dependencies to.. * sysdep.h: ..here. Many files: Include sysdep.h. Remove duplicate headers and reorder. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. ld/ Many files: Include sysdep.h first. Remove duplicate headers. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * ns32k-dis.c: Include sysdep.h first.
2005-12-06 * cpu-powerpc.c (bfd_powerpc_archs): Add ppc 750.Alan Modra1-0/+14
2005-05-04Update the address and phone number of the FSF organization in the GPL noticesNick Clifton1-1/+1
2005-05-04Update the FSF address in the copyright/GPL noticeNick Clifton1-1/+1
2005-03-03update copyright datesAlan Modra1-1/+1
2003-11-20* cpu-powerpc.c (powerpc_compatible): Any ISA in the PowerPCJim Blandy1-1/+1
family is a superset of <bfd_arch_rs6000,bfd_mach_rs6k>.
2002-11-30s/boolean/bfd_boolean/ s/true/TRUE/ s/false/FALSE/. SimplifyAlan Modra1-17/+17
comparisons of bfd_boolean vars with TRUE/FALSE. Formatting.
2002-08-30 * Makefile.am: Run "make dep-am".Alan Modra1-1/+1
* Makefile.in: Regenerate. * cpu-avr.c (compatible): Don't use hard-coded mach constants. * cpu-powerpc.c (powerpc_compatible): Likewise. * cpu-rs6000.c (rs6000_compatible): Likewise.
2002-08-192002-08-19 Elena Zannoni <ezannoni@redhat.com>Elena Zannoni1-0/+14
* archures.c (bfd_mach_ppc_e500): Added. * bfd-in2.h: Rebuilt. * cpu-powerpc.c (bfd_powerpc_archs): Added e500.
2002-06-27 * cpu-powerpc.c: Comment on ordering of arch_info.Alan Modra1-1/+7
* elf32-ppc.c (ppc_elf_object_p): New function. (elf_backend_object_p): Define. * elf64-ppc.c (ppc64_elf_object_p): New function. (elf_backend_object_p): Define.
2002-04-20 * archures.c (bfd_lookup_arch): Add comment on list order.Alan Modra1-39/+70
(bfd_default_set_arch_mach): Use bfd_lookup_arch. * cpu-powerpc.c (bfd_powerpc_archs): Re-order so that the default is always at head of list.
2002-02-05 * archures (bfd_mach_ppc64): Define.Alan Modra1-21/+34
(bfd_powerpc_arch): Rename to bfd_powerpc_archs. (bfd_powerpc_arch): Define. * bfd-in2.h: Regenerate. * cpu-powerpc.c (arch_info_struct): Rename to bfd_powerpc_archs. (bfd_powerpc_arch): Move to tail of bfd_powerpc_archs. (bfd_powerpc_archs): Add default powerpc64 arch. * gas/ppc/test1elf64.d: Tweak arch name.
2001-08-27 * config.bfd: Add powerpc64 target. Add powerpc64 vectors toAlan Modra1-3/+3
targ64_selvecs for 32 bit powerpc targets. * Makefile.am (BFD64_BACKENDS): Add elf64-ppc.lo. (BFD64_BACKENDS_CFILES): Add elf64-ppc.c. Run "make dep-am". * Makefile.in: Regenerate. * configure.in: Add elf64_powerpc vecs. * configure: Regenerate. * cpu-powerpc.c: Default to bfd_mach_ppc_620 entry for 64 bit. * elf.c (prep_headers): EM_PPC64 for 64 bit ppc elf target. * targets.c: Add bfd_elf64_powerpc_vec and bfd_elf64_powerpcle_vec. * elf64-ppc.c: New file. * reloc.c: Add powerpc64 relocs. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate.
2001-03-08Update copyright noticesNick Clifton1-1/+1
2000-11-162000-11-16 Kazu Hirata <kazu@hxi.com>Kazu Hirata1-8/+8
* cpu-a29k.c: Fix formatting. * cpu-alpha.c: Likewise. * cpu-arm.c: Likewise. * cpu-avr.c: Likewise. * cpu-d10v.c: Likewise. * cpu-h8500.c: Likewise. * cpu-hppa.c: Likewise. * cpu-i370.c: Likewise. * cpu-i386.c: Likewise. * cpu-i960.c: Likewise. * cpu-ia64-opc.c: Likewise. * cpu-ia64.c: Likewise. * cpu-m32r.c: Likewise. * cpu-m68hc11.c: Likewise. * cpu-m68hc12.c: Likewise. * cpu-m68k.c: Likewise. * cpu-m88k.c: Likewise. * cpu-mips.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-pj.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-sh.c: Likewise. * cpu-sparc.c: Likewise. * cpu-tic54x.c: Likewise. * cpu-v850.c: Likewise. * cpu-vax.c: Likewise. * cpu-w65.c: Likewise. * cpu-we32k.c: Likewise. * cpu-z8k.c: Likewise.
2000-09-052000-09-05 Steven Johnson <sbjohnson@ozemail.com.au>Geoffrey Keating1-0/+14
* cpu-powerpc.c (arch_info_struct): Added MPC860 Family entry.
2000-06-16 * archures.c (enum bfd_architecture): #define constants forNicholas Duffek1-10/+94
PowerPc and RS6000 machine numbers. * bfd-in2.h: Regenerate. * coffcode.h (coff_set_arch_mach_hook): #ifdef XCOFF64, set arch to bfd_arch_powerpc instead of bfd_arch_rs6000. Refer to PowerPc and RS6000 machine numbers using #defined constants from archures.c. * cpu-powerpc.c (arch_info_struct): Refer to PowerPc and RS6000 machine numbers using #defined constants from archures.c. Add entries for EC603e, 630, A35, RS64II, RS64III, 7400. Specify 64-bit words in 620 entry. * cpu-rs6000.c (arch_info_struct): Create with entries for RS1, RSC, and RS2. (bfd_rs6000_arch): Change default machine to 0 (bfd_mach_rs6k).
2000-04-26 Add XCOFF64 support.Clinton Popetz1-0/+14
bfd: * Makefile.am (coff64-rs6000.lo): New rule. * Makefile.in: Regenerate. * coff-rs6000.c (xcoff_mkobject, xcoff_copy_private_bfd_data, xcoff_is_local_label_name, xcoff_rtype2howto, xcoff_reloc_type_lookup, xcoff_slurp_armap, xcoff_archive_p, xcoff_read_ar_hdr, xcoff_openr_next_archived_file, xcoff_write_armap, xcoff_write_archive_contents): No longer static, and prefix with _bfd_. (NO_COFF_SYMBOLS): Define. (xcoff64_swap_sym_in, xcoff64_swap_sym_out, xcoff64_swap_aux_in, xcoff64_swap_aux_out): New functions; handle xcoff symbol tables internally. (MINUS_ONE): New macro. (xcoff_howto_tabl, xcoff_reloc_type_lookup): Add 64 bit POS relocation. (coff_SWAP_sym_in, coff_SWAP_sym_out, coff_SWAP_aux_in, coff_SWAP_aux_out): Map to the new functions. * coff64-rs6000.c: New file. * libcoff.h (bfd_coff_backend_data): Add new fields _bfd_coff_force_symnames_in_strings and _bfd_coff_debug_string_prefix_length. (bfd_coff_force_symnames_in_strings, bfd_coff_debug_string_prefix_length): New macros for above fields. * coffcode.h (coff_set_arch_mach_hook): Handle XCOFF64 magic. Set machine to 620 for XCOFF64. Use bfd_coff_swap_sym_in instead of using coff_swap_sym_in directly. (FORCE_SYMNAMES_IN_STRINGS): New macro, defined for XCOFF64. (coff_set_flags) Set magic for XCOFF64. (coff_compute_section_file_positions): Add symbol name length to string section length if bfd_coff_debug_string_prefix_length is true. (coff_write_object_contents): Don't do reloc overflow for XCOFF64. (coff_slurp_line_table): Use bfd_coff_swap_lineno_in instead of using coff_swap_lineno_in directly. (bfd_coff_backend_data): Add _bfd_coff_force_symnames_in_strings and _bfd_coff_debug_string_prefix_length fields. * coffgen.c (coff_fix_symbol_name, coff_write_symbols): Force symbol names into strings table when bfd_coff_force_symnames_in_strings is true. * coffswap.h (MAX_SCNHDR_NRELOC, MAX_SCNHDR_NLNNO, GET_RELOC_VADDR, SET_RELOC_VADDR): New macros. (coff_swap_reloc_in, coff_swap_reloc_out): Use above macros. (coff_swap_aux_in, coff_swap_aux_out): Remove RS6000COFF_C code. (coff_swap_aouthdr_in, coff_swap_aouthdr_out): Handle XCOFF64 changes within RS6000COFF_C specific code. (coff_swap_scnhdr_out): Use PUT_SCNHDR_NLNNO, PUT_SCNHDR_NRELOC, MAX_SCNHDR_NRELOC, and MAX_SCNHDR_NLNNO. * reloc.c (bfd_perform_relocation, bfd_install_relocation): Extend existing hack on target name. * xcofflink.c (XCOFF_XVECP): Extend existing hack on target name. * coff-tic54x.c (ticof): Keep up to date with new fields in bfd_coff_backend_data. * config.bfd: Add bfd_powerpc_64_arch to targ_arch and define targ_selvecs to include rs6000coff64_vec for rs6000. * configure.in: Add rs6000coff64_vec case. * cpu-powerpc.c: New bfd_arch_info_type. gas: * as.c (parse_args): Allow md_parse_option to override -a listing option. * config/obj-coff.c (add_lineno): Change type of offset parameter from "int" to "bfd_vma." * config/tc-ppc.c (md_pseudo_table): Add "llong" and "machine." (ppc_mach, ppc_subseg_align, ppc_target_format): New. (ppc_change_csect): Align correctly for XCOFF64. (ppc_machine): New function, which discards "ppc_machine" line. (ppc_tc): Cons for 8 when code is 64 bit. (md_apply_fix3): Don't check operand->insert. Handle 64 bit relocations. (md_parse_option): Handle -a64 and -a32. (ppc_xcoff64): New. * config/tc-ppc.h (TARGET_MACH): Define. (TARGET_FORMAT): Move to function. (SUB_SEGMENT_ALIGN): Use ppc_subseg_align. include: * include/coff/rs6k64.h: New file. opcodes: * configure.in: Add bfd_powerpc_64_arch. * disassemble.c (disassembler): Use print_insn_big_powerpc for 64 bit code.
1999-05-0319990502 sourceware importbinu_ss_19990502Richard Henderson1-0/+124
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