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bfd/
* bfd-in.h: Move csky function declarations to..
* elf32-csky.h: ..here, new file.
* elf32-csky.c: Include elf32-csky.h.
* bfd-in2.h: Regenerate.
ld/
* emultempl/cskyelf.em: Include elf32-csky.h.
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This one exposed a bug in tic6x gas, found with inline function
parameter type checking. struct bfd_section and struct bfd_symbol
both have a flags field, so bfd_is_com_section (symbol) compiled OK
when bfd_is_com_section was a macro but didn't special case common
symbols.
bfd/
* bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment, bfd_section_flags),
(bfd_section_userdata, bfd_is_com_section, discarded_section),
(bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros.
* bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit),
(bfd_section_list_remove, bfd_section_list_append),
(bfd_section_list_prepend, bfd_section_list_insert_after),
(bfd_section_list_insert_before, bfd_section_removed_from_list):
New inline functions.
* section.c (bfd_is_und_section, bfd_is_abs_section),
(bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove),
(bfd_section_list_append, bfd_section_list_prepend),
(bfd_section_list_insert_after, bfd_section_list_insert_before),
(bfd_section_removed_from_list): Delete macros.
(bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment, bfd_section_flags),
(bfd_section_userdata, bfd_is_com_section, bfd_is_und_section),
(bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section),
(discarded_section): New inline functions.
* bfd-in2.h: Regenerate.
gas/
* config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check.
ld/
* emultempl/xtensaelf.em (xtensa_get_section_deps): Comment.
Use bfd_section_userdata.
(xtensa_set_section_deps): Use bfd_set_section_userdata.
* ldlang.c (lang_output_section_get): Use bfd_section_userdata.
(sort_def_symbol): Likewise, and bfd_set_section_userdata.
(init_os): Use bfd_set_section_userdata.
(print_all_symbols): Use bfd_section_userdata.
* ldlang.h (get_userdata): Delete.
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* bfd-in.h (bfd_asymbol_section, bfd_asymbol_value, bfd_asymbol_name),
(bfd_asymbol_bfd, bfd_asymbol_flavour, bfd_set_asymbol_name): Delete.
* bfd.c (bfd_asymbol_section, bfd_asymbol_value, bfd_asymbol_name),
(bfd_asymbol_bfd, bfd_set_asymbol_name): New inline functions.
* targets.c (bfd_asymbol_flavour): Likewise.
* bfd-in2.h: Regenerate.
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This converts some of the macros that access struct bfd fields to
inline functions.
bfd/
* archive.c (bfd_generic_archive_p): Use bfd_set_thin_archive.
* bfd-in.h (bfd_get_filename, bfd_get_cacheable, bfd_get_format),
(bfd_get_target, bfd_get_flavour, bfd_family_coff, bfd_big_endian),
(bfd_little_endian, bfd_header_big_endian, bfd_header_little_endian),
(bfd_get_file_flags, bfd_applicable_file_flags),
(bfd_applicable_section_flags, bfd_has_map, bfd_is_thin_archive),
(bfd_valid_reloc_types, bfd_usrdata, bfd_get_start_address),
(bfd_get_symcount, bfd_get_outsymbols, bfd_count_sections),
(bfd_get_dynamic_symcount, bfd_get_symbol_leading_char): Delete.
* bfd/bfd.c (bfd_get_filename, bfd_get_cacheable, bfd_get_format),
(bfd_get_file_flags, bfd_get_start_address, bfd_get_symcount),
(bfd_get_dynamic_symcount, bfd_get_outsymbols, bfd_count_sections),
(bfd_has_map, bfd_is_thin_archive, bfd_set_thin_archive),
(bfd_usrdata, bfd_set_usrdata): New inline functions.
* targets.c (bfd_get_target, bfd_get_flavour),
(bfd_applicable_file_flags, bfd_family_coff, bfd_big_endian),
(bfd_little_endian, bfd_header_big_endian),
(bfd_header_little_endian, bfd_applicable_section_flags),
(bfd_get_symbol_leading_char): New inline functions.
* bfd-in2.h: Regenerate.
binutils/
* ar.c (write_archive): Use bfd_set_thin_archive.
gdb/
* gdb_bfd.c (gdb_bfd_ref, gdb_bfd_unref): Use bfd_set_usrdata.
* dwarf2read.c (dwarf2_read_gdb_index, dwarf2_read_debug_names),
(read_indirect_string_from_dwz): Use bfd accessor.
* dwarf2read.h (struct dwz_file <filename>): Likewise.
* machoread.c (macho_symfile_read_all_oso): Likewise.
* solib.c (solib_bfd_open): Likewise.
ld/
* ldelf.c (ldelf_after_open, ldelf_place_orphan
* ldlang.c (walk_wild_file, lang_process): Use bfd_usrdata.
(load_symbols, ldlang_add_file): Use bfd_set_usrdata.
* ldmain.c (add_archive_element): Use bfd_usrdata.
* ldlang.h (bfd_input_just_syms): New inline function.
* emultempl/aarch64elf.em (build_section_lists): Use it.
* emultempl/mmo.em (mmo_place_orphan): Likewise.
* emultempl/pe.em (gld_${EMULATION_NAME}_place_orphan): Likewise.
* emultempl/pep.em (gld_${EMULATION_NAME}_place_orphan): Likewise.
* emultempl/ppc64elf.em (build_section_lists): Likewise.
sim/
* ppc/emul_generic.c (emul_add_tree_options): Delete old bfd code.
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This large patch removes the unnecessary bfd parameter from various
bfd section macros and functions. The bfd is hardly ever used and if
needed for the bfd_set_section_* or bfd_rename_section functions can
be found via section->owner except for the com, und, abs, and ind
std_section special sections. Those sections shouldn't be modified
anyway.
The patch also removes various bfd_get_section_<field> macros,
replacing their use with bfd_section_<field>, and adds
bfd_set_section_lma. I've also fixed a minor bug in gas where
compressed section renaming was done directly rather than calling
bfd_rename_section. This would have broken bfd_get_section_by_name
and similar functions, but that hardly mattered at such a late stage
in gas processing.
bfd/
* bfd-in.h (bfd_get_section_name, bfd_get_section_vma),
(bfd_get_section_lma, bfd_get_section_alignment),
(bfd_get_section_size, bfd_get_section_flags),
(bfd_get_section_userdata): Delete.
(bfd_section_name, bfd_section_size, bfd_section_vma),
(bfd_section_lma, bfd_section_alignment): Lose bfd parameter.
(bfd_section_flags, bfd_section_userdata): New.
(bfd_is_com_section): Rename parameter.
* section.c (bfd_set_section_userdata, bfd_set_section_vma),
(bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section),
(bfd_set_section_size): Delete bfd parameter, rename section parameter.
(bfd_set_section_lma): New.
* bfd-in2.h: Regenerate.
* mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param,
update callers.
* aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c,
* coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c,
* compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h,
* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c,
* elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c,
* elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c,
* elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c,
* elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c,
* elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c,
* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
* elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c,
* elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c,
* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
* elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c,
* elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c,
* elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c,
* elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c,
* elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c,
* elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c,
* elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c,
* elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c,
* elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c,
* elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c,
* mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c,
* peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c,
* xcofflink.c: Update throughout for bfd section macro and function
changes.
binutils/
* addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c,
* objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c,
* od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c,
* resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update
throughout for bfd section macro and function changes.
gas/
* as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c,
* read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c,
* config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c,
* config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c,
* config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c,
* config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c,
* config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c,
* config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c,
* config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c,
* config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c,
* config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c,
* config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c,
* config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c,
* config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c,
* config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c,
* config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c,
* config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c,
* config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for
bfd section macro and function changes.
* write.c (compress_debug): Use bfd_rename_section.
gdb/
* aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c,
* coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c,
* dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c,
* exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h,
* hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c,
* i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c,
* maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c,
* mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c,
* objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c,
* ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c,
* rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c,
* s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c,
* solib-spu.c, * solib-svr4.c, * solib-target.c,
* spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c,
* symmisc.c, * symtab.c, * target.c, * windows-nat.c,
* xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c,
* mi/mi-interp.c: Update throughout for bfd section macro and
function changes.
* gcore (gcore_create_callback): Use bfd_set_section_lma.
* spu-tdep.c (spu_overlay_new_objfile): Likewise.
gprof/
* corefile.c, * symtab.c: Update throughout for bfd section
macro and function changes.
ld/
* ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c,
* emultempl/aarch64elf.em, * emultempl/aix.em,
* emultempl/armcoff.em, * emultempl/armelf.em,
* emultempl/cr16elf.em, * emultempl/cskyelf.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update
throughout for bfd section macro and function changes.
libctf/
* ctf-open-bfd.c: Update throughout for bfd section macro changes.
opcodes/
* arc-ext.c: Update throughout for bfd section macro changes.
sim/
* common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c,
* erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c,
* m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c,
* rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c,
* rx/trace.c: Update throughout for bfd section macro changes.
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The main point of this patch is to give bfd_get_section a better name,
bfd_asymbol_section.
bfd/
* bfd-in.h (bfd_asymbol_section): Rename from bfd_get_section.
(bfd_get_output_section): Delete.
(bfd_asymbol_base): Delete.
(bfd_asymbol_section, bfd_asymbol_value, bfd_asymbol_name),
(bfd_asymbol_bfd, bfd_asymbol_flavour): Tidy.
(bfd_set_asymbol_name): New macro.
* bfd-in2.h: Regenerate.
* aout-cris.c: Update throughout to use bfd_asymbol_section.
* aoutx.h: Likewise.
* cofflink.c: Likewise.
* dwarf2.c: Likewise.
* ecoff.c: Likewise.
* elf.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-mips.c: Likewise.
* elf32-score.c: Likewise.
* elf32-score7.c: Likewise.
* elfn32-mips.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfxx-mips.c: Likewise.
* linker.c: Likewise.
* pdp11.c: Likewise.
* elf64-mmix.c (mmix_elf_reloc): Expand bfd_get_output_section.
binutils/
* nm.c: Update bfd_get_section to bfd_asymbol_section throughout.
* objcopy.c: Likewise.
* objdump.c: Likewise.
* rdcoff.c: Likewise.
* objcopy.c (create_new_symbol): Use bfd_set_asymbol_name.
(filter_symbols): Likewise.
gas/
* symbols.c (S_IS_LOCAL): Update bfd_get_section to
bfd_asymbol_section.
gdb/
* arm-tdep.c (arm_record_special_symbol): Update bfd_get_section
to bfd_asymbol_section.
ld/
* ldcref.c (check_reloc_refs): Update bfd_get_section to
bfd_asymbol_section.
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* archures.c (bfd_get_arch): Make param const.
(bfd_get_mach, bfd_arch_bits_per_byte): Likewise.
(bfd_arch_bits_per_address, bfd_octets_per_byte): Likewise.
* bfd-in2.h: Regenerate.
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bfd/
* bfd-in.h (carsym.name): Make const.
* reloc.c (struct reloc_howto_struct.name): Likewise.
* targets.c (bfd_target.name): Likewise.!
* bfd.c (bfd_get_sign_extend_vma): Make variable const.
* som.c (som_bfd_fill_in_ar_symbols): Use an intermediary variable
when setting carsym.name.
* bfd-in2.h: Regenerate.
gdb/
* amd64-dicos-tdep.c (amd64_dicos_osabi_sniffer): Constify target.
* i386-cygwin-tdep.c (i386_cygwin_init_abi): Likewise.
* i386-dicos-tdep.c (i386_dicos_osabi_sniffer): Likewise.
ld/
* ldlang.c (stricpy, strcut, name_compare): Constify params.
(get_first_input_target): Make return and "target" const.
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This introduces a new bfd_set_filename function, which is then used in
various spots in gdb. This allows for the removal of some casts.
bfd/ChangeLog
2019-09-11 Tom Tromey <tom@tromey.com>
* opncls.c (bfd_set_filename): New function.
* bfd-in2.h: Regenerate.
gdb/ChangeLog
2019-09-11 Tom Tromey <tom@tromey.com>
* symfile-mem.c (symbol_file_add_from_memory): Use
bfd_set_filename.
* solib-darwin.c (darwin_bfd_open): Use bfd_set_filename.
* solib-aix.c (solib_aix_bfd_open): Use bfd_set_filename.
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The idea here is to not use elf-bfd.h and coff-bfd.h in generic linker
code.
bfd/
* targets.c (struct bfd_target): Add _bfd_group_name.
(BFD_JUMP_TABLE): Likewise.
* coffgen.c (bfd_coff_group_name): New function.
* elf.c (bfd_elf_group_name): New function.
* linker.c (_bfd_nolink_bfd_group_name): New function.
* section.c (bfd_generic_group_name): New function.
* elf-bfd.h (bfd_elf_group_name): Declare.
* libbfd-in.h (_bfd_nolink_bfd_group_name): Declare.
* libcoff-in.h (bfd_coff_group_name): Declare.
* aout-target.h (MY_bfd_group_name): Define.
* aout-tic30.c (MY_bfd_group_name): Define.
* bfd.c (bfd_group_name): Define.
* binary.c (binary_bfd_group_name): Define.
* coff-alpha.c (_bfd_ecoff_bfd_group_name): Define.
* coff-mips.c (_bfd_ecoff_bfd_group_name): Define.
* coff-rs6000.c (_bfd_xcoff_bfd_group_name): Define.
* coffcode.h (coff_bfd_group_name): Define.
* elfxx-target.h (bfd_elfNN_bfd_group_name): Define.
* i386msdos.c (msdos_bfd_group_name): Define.
* ihex.c (ihex_bfd_group_name): Define.
* mach-o-target.c (bfd_mach_o_bfd_group_name): Define.
* mmo.c (mmo_bfd_group_name): Define.
* pef.c (bfd_pef_bfd_group_name): Define.
* plugin.c (bfd_plugin_bfd_group_name): Define.
* ppcboot.c (ppcboot_bfd_group_name): Define.
* som.c (som_bfd_group_name): Define.
* srec.c (srec_bfd_group_name): Define.
* tekhex.c (tekhex_bfd_group_name): Define.
* verilog.c (verilog_bfd_group_name): Define.
* vms-alpha.c (vms_bfd_group_name, alpha_vms_bfd_group_name): Define.
* xsym.c (bfd_sym_bfd_group_name): Define.
* coff64-rs6000.c (rs6000_xcoff64_vec): Init new field.
(rs6000_xcoff64_aix_vec): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* libcoff.h: Regenerate.
ld/
* ldmisc.c: Don't #include elf-bfd.h or coff-bfd.h.
(vfinfo): Use bfd_group_name.
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applies to the middle of the next insn.
PR 24907
binutils* objdump.c (null_print): New function.
(disassemble_bytes): Delete previous_octets local and replace with
a test of the max_reloc_offset_into_insn field of the
bfd_arch_info structure. If a reloc is a potential match for the
next insn, then perform a dummy disassembly in order to calculate
its real length.
bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn
field.
(bfd_default_arch_struct): Initialise the new field.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c: Initialise the new field.
* cpu-alpha.c: Likewise.
* cpu-arc.c: Likewise.
* cpu-arm.c: Likewise.
* cpu-avr.c: Likewise.
* cpu-bfin.c: Likewise.
* cpu-bpf.c: Likewise.
* cpu-cr16.c: Likewise.
* cpu-cr16c.c: Likewise.
* cpu-cris.c: Likewise.
* cpu-crx.c: Likewise.
* cpu-csky.c: Likewise.
* cpu-d10v.c: Likewise.
* cpu-d30v.c: Likewise.
* cpu-dlx.c: Likewise.
* cpu-epiphany.c: Likewise.
* cpu-fr30.c: Likewise.
* cpu-frv.c: Likewise.
* cpu-ft32.c: Likewise.
* cpu-h8300.c: Likewise.
* cpu-hppa.c: Likewise.
* cpu-i386.c: Likewise.
* cpu-ia64.c: Likewise.
* cpu-iamcu.c: Likewise.
* cpu-ip2k.c: Likewise.
* cpu-iq2000.c: Likewise.
* cpu-k1om.c: Likewise.
* cpu-l1om.c: Likewise.
* cpu-lm32.c: Likewise.
* cpu-m10200.c: Likewise.
* cpu-m10300.c: Likewise.
* cpu-m32c.c: Likewise.
* cpu-m32r.c: Likewise.
* cpu-m68hc11.c: Likewise.
* cpu-m68hc12.c: Likewise.
* cpu-m68k.c: Likewise.
* cpu-m9s12x.c: Likewise.
* cpu-m9s12xg.c: Likewise.
* cpu-mcore.c: Likewise.
* cpu-mep.c: Likewise.
* cpu-metag.c: Likewise.
* cpu-microblaze.c: Likewise.
* cpu-mips.c: Likewise.
* cpu-mmix.c: Likewise.
* cpu-moxie.c: Likewise.
* cpu-msp430.c: Likewise.
* cpu-mt.c: Likewise.
* cpu-nds32.c: Likewise.
* cpu-nfp.c: Likewise.
* cpu-nios2.c: Likewise.
* cpu-ns32k.c: Likewise.
* cpu-or1k.c: Likewise.
* cpu-pdp11.c: Likewise.
* cpu-pj.c: Likewise.
* cpu-plugin.c: Likewise.
* cpu-powerpc.c: Likewise.
* cpu-pru.c: Likewise.
* cpu-riscv.c: Likewise.
* cpu-rl78.c: Likewise.
* cpu-rs6000.c: Likewise.
* cpu-rx.c: Likewise.
* cpu-s12z.c: Likewise.
* cpu-s390.c: Likewise.
* cpu-score.c: Likewise.
* cpu-sh.c: Likewise.
* cpu-sparc.c: Likewise.
* cpu-spu.c: Likewise.
* cpu-tic30.c: Likewise.
* cpu-tic4x.c: Likewise.
* cpu-tic54x.c: Likewise.
* cpu-tic6x.c: Likewise.
* cpu-tic80.c: Likewise.
* cpu-tilegx.c: Likewise.
* cpu-tilepro.c: Likewise.
* cpu-v850.c: Likewise.
* cpu-v850_rh850.c: Likewise.
* cpu-vax.c: Likewise.
* cpu-visium.c: Likewise.
* cpu-wasm32.c: Likewise.
* cpu-xc16x.c: Likewise.
* cpu-xgate.c: Likewise.
* cpu-xstormy16.c: Likewise.
* cpu-xtensa.c: Likewise.
* cpu-z80.c: Likewise.
* cpu-z8k.c: Likewise.
gas * testsuite/gas/arm/pr24907.s: New test.
* testsuite/gas/arm/pr24907.d: Expected disassembly.
|
|
This macro says:
/* Cast from const char * to char * so that caller can assign to
a char * without a warning. */
I reckon that isn't such a good idea since it can result in char*
variables where const char* is appropriate. Not very many places
need the char* cast.
bfd/
* aout-target.h (object_p): Formatting.
* bfd-in.h (bfd_get_filename): Don't cast to char*.
* corefile.c (generic_core_file_matches_executable_p): Constify
variables and remove cast.
* bfd-in2.h: Regenerate.
binutils/
* nm.c (print_object_filename_bsd, print_object_filename_sysv),
(print_object_filename_posix, print_archive_filename_bsd),
(print_archive_filename_sysv, print_archive_filename_posix),
(print_archive_member_bsd, print_archive_member_sysv),
(print_archive_member_posix): Constify parameter.
(struct output_fns <print_object_filename, print_archive_filename>),
(<print_archive_member>): Likewise.
* objcopy.c (copy_archive): Add cast for make_tempdir.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_search_needed): Constify
variable.
* emultempl/pe.em (gld_${EMULATION_NAME}_after_open): Likewise.
* emultempl/pep.em (gld_${EMULATION_NAME}_after_open): Likewise.
gdb/
* coffread.c (coff_symfile_read): Constify filename variable.
* dbxread.c (dbx_symfile_init, coffstab_build_psymtabs),
(elfstab_build_psymtabs, stabsect_build_psymtabs): Likewise.
* gdb_bfd.c (gdb_bfd_close_or_warn): Likewise.
* solib.c (reload_shared_libraries_1): Likewise.
* symfile.c (reread_symbols): Likewise.
* solib-aix.c (solib_aix_bfd_open): Add cast for xfree of filename.
* solib-darwin.c (darwin_bfd_open): Likewise.
* symfile-mem.c (symbol_file_add_from_memory): Likewise.
sim/cris/
* sim-if.c (sim_open): Constify filename variable.
|
|
BFD was leaking memory in bfd_check_format_matches. As part of
deciding the proper format of an archive, BFD looks at the format of
the first file stored. That file's bfd was left open for reasons
given in a comment removed in git commit 0e71e4955cd1 that said:
/* We ought to close `first' here, but we can't, because
we have no way to remove it from the archive cache.
It's close to impossible to figure out when we can
release bfd_ardata. FIXME. */
Well, things have changed since that comment was true and we now can
remove files from the archive cache. Closing the first file is good
and cures some of the leaks. Other leaks are caused by
bfd_check_format_matches throwing away bfd tdata before trying a new
match. That lost the element cache set up when format checking the
first element in the archive. The easiest and cleanest fix is to
simply disable the caching when checking the first element.
PR 24891
* bfd.c (struct bfd): Add no_element_cache.
* archive.c (_bfd_get_elt_at_filepos): Don't add element to
archive cache when no_element_cache.
(bfd_generic_archive_p): Set no_element_cache when opening first
element to check format. Close first element too.
(do_slurp_bsd_armap): Don't zero ardata->cache here.
* bfd-in2.h: Regenerate.
|
|
PR 24768
* bfd.c (struct bfd): Add lto_slim_object flag.
* bfd-in2.h: Regenerate.
|
|
bfd/ChangeLog:
2019-07-22 Martin Liska <mliska@suse.cz>
PR 24768
* archive.c (_bfd_compute_and_write_armap): Come up with
report_plugin_err variable.
* bfd-in2.h (struct bfd): Add lto_slim_object flag.
* elf.c (struct lto_section): New.
(_bfd_elf_make_section_from_shdr): Parse content of
.gnu_lto_.lto section.
* elflink.c: Report error for a missing LTO plugin.
* linker.c (_bfd_generic_link_add_one_symbol): Likewise.
binutils/ChangeLog:
2019-07-22 Martin Liska <mliska@suse.cz>
PR 24768
* nm.c (filter_symbols): Set report_plugin_err if
error is reported.
(display_rel_file): Report error for a missing LTO plugin.
gold/ChangeLog:
2019-07-22 Martin Liska <mliska@suse.cz>
PR 24768
* layout.h (class Layout): Add is_lto_slim_object and
set_lto_slim_object.
* object.cc (struct lto_section): Add lto_slim_object_.
(big_endian>::do_layout): Parse content of
.gnu_lto_.lto section.
(big_endian>::do_add_symbols): Report error for a missing
LTO plugin.
|
|
This patch supports using pcrel instructions in TLS code sequences. A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation. For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence. The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.
GD:
pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34
bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
edited to IE
pld 3,z@got@tprel@pcrel
add 3,3,13
edited to LE
paddi 3,13,z@tprel
nop
LD:
pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34
bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
..
paddi 9,3,z2@dtprel
pld 10,z3@got@dtprel@pcrel
add 10,10,3
edited to LE
paddi 3,13,0x1000
nop
IE:
pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34
add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1
ldx 4,9,z@tls@pcrel
lwax 5,9,z@tls@pcrel
stdx 5,9,z@tls@pcrel
edited to LE
paddi 9,13,z@tprel
nop
ld 4,0(9)
lwa 5,0(9)
std 5,0(9)
LE:
paddi 10,13,z@tprel
include/
* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
(ppc64_elf_check_relocs): Support pcrel tls relocs.
(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
ld/
* testsuite/ld-powerpc/tlsgd.d,
* testsuite/ld-powerpc/tlsgd.s,
* testsuite/ld-powerpc/tlsie.d,
* testsuite/ld-powerpc/tlsie.s,
* testsuite/ld-powerpc/tlsld.d,
* testsuite/ld-powerpc/tlsld.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
|
|
This patch moves the current AArch64 ld options of --force-bti
and --pac-plt to -z force-bti and -z pac-plt since these are
ELF specific options.
*** bfd/ChangeLog ***
2019-06-06 Sudakshina Das <sudi.das@arm.com>
* bfd-in.h: Change comment.
* bfd-in2.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_merge_gnu_properties): Update warning.
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties):
Likwise.
*** ld/ChangeLog ***
2019-06-06 Sudakshina Das <sudi.das@arm.com>
* NEWS: Update options names.
* emultempl/aarch64elf.em (OPTION_FORCE_BTI, OPTION_PAC_PLT): Remove.
(PARSE_AND_LIST_LONGOPTS): Remove force-bti and pac-plt.
(PARSE_AND_LIST_OPTIONS): Update to -z.
(PARSE_AND_LIST_ARGS_CASE_Z_AARCH64): New.
(PARSE_AND_LIST_ARGS_CASE_Z): Add PARSE_AND_LIST_ARGS_CASE_Z_AARCH64.
(PARSE_AND_LIST_ARGS_CASES): Move cases for these options.
* testsuite/ld-aarch64/bti-pac-plt-1.d: Update option.
* testsuite/ld-aarch64/bti-pac-plt-2.d: Likewise.
* testsuite/ld-aarch64/bti-plt-1.d: Likewise.
* testsuite/ld-aarch64/bti-plt-2.d: Likewise.
* testsuite/ld-aarch64/bti-plt-3.d: Likewise.
* testsuite/ld-aarch64/bti-plt-4.d: Likewise.
* testsuite/ld-aarch64/bti-plt-6.d: Likewise.
* testsuite/ld-aarch64/bti-plt-7.d: Likewise.
* testsuite/ld-aarch64/bti-warn.d: Likewise.
* testsuite/ld-aarch64/pac-plt-1.d: Likewise.
* testsuite/ld-aarch64/pac-plt-2.d: Likewise.
|
|
include/
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
(BFD_RELOC_PPC64_PLT_PCREL34),
(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
* elf64-ppc.c (PNOP): Define.
(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
relocs.
(ppc64_elf_prefix_reloc): New function.
(struct ppc_link_hash_table): Add notoc_plt.
(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set
has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle
possible need for dynamic relocs on non-pcrel powerxx relocs.
(dec_dynrel_count): Handle non-pcrel powerxx relocs.
(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_relocate_section): Handle new powerxx relocs.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
|
|
This patch adds support to BFD for elf64-bpf, in both little-endian
and big-endian variants.
bfd/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac: Add bpf_elf64_le_vec and bpf_elf64_be_vec.
* configure: Regenerated.
* Makefile.am (ALL_MACHINES): Add cpu-bpf.lo.
(ALL_MACHINES_CFILES): Add cpu-bpf.c.
(BFD64_BACKENDS): Add elf64-bpf.lo.
(BFD64_BACKENDS_CFILES): Add elf64-bpf.c.
* Makefile.in (SOURCE_HFILES): Regenerate.
* config.bfd (targ_cpu): Handle bpf-*-* targets.
* cpu-bpf.c: New file.
* elf64-bpf.c: Likewise.
* targets.c (_bfd_target_vector): Add bpf_elf64_be_vec and
bpf_elf64_le_vec.
* archures.c: Define architecture bfd_arch_bpf and machine
bfd_arch_bpf.
* reloc.c: Define BFD relocations used by the BPF target.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
|
|
The Cortex-A53 erratum currently has two ways it can resolve the erratum when
using the flag --fix-cortex-a53-843419:
1) If the address is within the range of an ADR instruction it rewrites the ADRP
into an ADR, and those doesn't need the use of a veneer.
2) If the address is not within range, it adds a branch to a veneer which will
execute the final bit of the erratum workaround and branch back to the call
site.
When we do this we always generate the veneers and we always align the size of
the text section to 4KB. This is because we only know which workaround we can
use after all linking has finished and all addresses are known. This means even
though the veneers are not used, we still generate the section and we still
change the size of the input section.
This is problematic for small memory devices as this would require the user to
take about a ~4KB hit in memory even though it's not even used.
Since there's no real way to restart the linking process from the final write
phase this patch solves the issue by allowing the user more control over which
erratum workaround gets used.
Concretely this changes the option --fix-cortex-a53-843419 to take optional
arguments --fix-cortex-a53-843419[=full|adr|adrp]
- full (default): Use both ADRP and ADR workaround. This is equivalent to not
specifying any options and is the default behavior before this
patch.
- adr: Only use the ADR workaround, this will not cause any increase in binary
size but linking will fail if the referenced address is out of range of
an ADR instruction.
- adrp: Use only the ADRP workaround, this will never rewrite your ADRP.
In the cases where the user knows how big their binaries are the `adr` option
would prevent the unneeded overhead.
bfd/ChangeLog:
PR ld/24373
* bfd-in.h (enum erratum_84319_opts): New
(bfd_elf64_aarch64_set_options, bfd_elf32_aarch64_set_options): Change
int to enum erratum_84319_opts.
* bfd-in2.h: Regenerate.
* elfnn-aarch64.c (struct elf_aarch64_link_hash_table): Change
fix_erratum_843419 to use new enum, remove fix_erratum_843419_adr.
(_bfd_aarch64_add_stub_entry_after): Conditionally create erratum stub.
(aarch64_size_one_stub): Conditionally size erratum 843419 stubs.
(_bfd_aarch64_resize_stubs): Amend comment.
(elfNN_aarch64_size_stubs): Don't generate stubs when no workaround
requested.
(bfd_elfNN_aarch64_set_options): Use new fix_erratum_843419 enum.
(_bfd_aarch64_erratum_843419_branch_to_stub): Implement selection of
erratum workaround.
(clear_erratum_843419_entry): Update erratum conditional.
ld/ChangeLog:
PR ld/24373
* emultempl/aarch64elf.em (PARSE_AND_LIST_LONGOPTS): Add optional args
to flags.
* NEWS: Add changes to flag.
(PARSE_AND_LIST_OPTIONS): Update help descriptions.
(PARSE_AND_LIST_ARGS_CASES): Add new options to parser.
* testsuite/ld-aarch64/aarch64-elf.exp: Add new run_dump_tests.
* testsuite/ld-aarch64/erratum843419-adr.d: New test.
* testsuite/ld-aarch64/erratum843419-adrp.d: New test.
* testsuite/ld-aarch64/erratum843419-far-adr.d: New test.
* testsuite/ld-aarch64/erratum843419-far-full.d: New test.
* testsuite/ld-aarch64/erratum843419-far.s: New test.
* testsuite/ld-aarch64/erratum843419-full.d: New test.
* testsuite/ld-aarch64/erratum843419-near.s: New test.
* testsuite/ld-aarch64/erratum843419-no-args.d: New test.
|
|
GOT and PLT relocs shouldn't have their symbols replaced with a
section symbol plus added. Nor should the HIGHA TLS relocations,
which failed to be caught by the range test in ppc_fix_adjustable.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA),
(BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA):
Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry.
gas/
* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
relocs, and VLE sdarel relocs.
* testsuite/gas/ppc/power4.d: Adjust.
|
|
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
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Mainline
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
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s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum.
ChangeLog entries are as follows:
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
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R_ARM_THM_BF12
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
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This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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R_ARM_THM_BF16
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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for fallback branch
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX,
BFCSEL). These are the first instructions in ARM that have more than one
relocations in them.
This is the first infrastructure patch that adds a new bfd_reloc_code_real enum
for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by the
assembler.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
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The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
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enabled PLTs
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
1) This patch adds a new ld command line option: --force-bti.
In the presence of this option, the linker enables BTI with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning
in case of missing gnu notes for BTI in inputs.
2) It also defines a new set of BTI enabled PLTs. These are used either
when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI
or when the new --force-bti option is used. This required adding new
fields in elf_aarch64_link_hash_table so that we could make the PLT
related information more generic.
3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses
this whenever it picks BTI enabled PLTs.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New.
(aarch64_bti_pac_info): New.
(bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument.
(bfd_elf32_aarch64_set_options): Likewise.
* bfd-in2.h: Regenerate
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New.
(elfNN_aarch64_small_plt0_bti_entry): New.
(elfNN_aarch64_small_plt_bti_entry): New.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): New.
(elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields.
(elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and
tlsdesc_plt_entry_size fields.
(elfNN_aarch64_link_hash_table_create): Initialise the new fields.
(setup_plt_values): New helper function.
(bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and
bti enable type.
(elfNN_aarch64_allocate_dynrelocs): Use new size members instead of
fixed macros.
(elfNN_aarch64_size_dynamic_sections): Likewise and add checks.
(elfNN_aarch64_create_small_pltn_entry): Use new generic pointers
to plt stubs instead of fixed ones and update filling them according
to the need for bti.
(elfNN_aarch64_init_small_plt0_entry): Likewise.
(elfNN_aarch64_finish_dynamic_sections): Likewise.
(get_plt_type, elfNN_aarch64_get_synthetic_symtab): New.
(elfNN_aarch64_plt_sym_val): Update size accordingly.
(elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE
is set.
(bfd_elfNN_get_synthetic_symtab): Define.
(elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti
and mising BTI NOTE SECTION.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* readelf.c (get_aarch64_dynamic_type): New.
(get_dynamic_type): Use above for EM_AARCH64.
(dynamic_section_aarch64_val): New.
(process_dynamic_section): Use above for EM_AARCH64.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* NEWS: Document --force-bti.
* emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New.
(PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI.
* testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below.
* testsuite/ld-aarch64/bti-plt-1.d: New test.
* testsuite/ld-aarch64/bti-plt-1.s: New test.
* testsuite/ld-aarch64/bti-plt-2.s: New test.
* testsuite/ld-aarch64/bti-plt-2.d: New test.
* testsuite/ld-aarch64/bti-plt-3.d: New test.
* testsuite/ld-aarch64/bti-plt-4.d: New test.
* testsuite/ld-aarch64/bti-plt-5.d: New test.
* testsuite/ld-aarch64/bti-plt-6.d: New test.
* testsuite/ld-aarch64/bti-plt-7.d: New test.
* testsuite/ld-aarch64/bti-plt-so.s: New test.
* testsuite/ld-aarch64/bti-plt.ld: New test.
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When assembling instructions which involve OPR references, emit
RELOC_S12Z_OPR instead of RELOC_EXT24.
bfd/
* bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc.
* libbfd.h: regen.
* elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero
source field. (md_apply_fix): Apply final fix
to BFD_RELOC_S12Z_OPR.
* reloc.c[BFD_RELOC_S12Z_OPR]: New reloc.
gas/
* config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
BFD_RELOC_24.
* testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead
of R_S12Z_EXT24.
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* bfd/archures.c: Add bfd_mach_rx_v2 and bfd_mach_rx_v3.
* bfd/bfd-in2.h: Regenerate.
* bfd/cpu-rx.c (arch_info_struct): Add RXv2 and RXv3 entry.
* bfd/elf32-rx.c (elf32_rx_machine): Add RXv2 and RXv3 support.
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This patch adds bfd_stdint.h to bfd.h, so that BFD can use size_t
where appropriate in function parameters and return values. I also
tidy a few other cases where headers are included twice.
bfd/
* Makefile.am (bfdinclude_HEADERS): Add bfd_stdint.h.
(BFD_H_DEPS): Add include/diagnostics.h.
(LOCAL_H_DEPS): Add bfd_stdint.h.
* bfd-in.h: Include bfd_stdint.h.
* arc-plt.h: Don't include stdint.h.
* coff-rs6000.c: Likewise.
* coff64-rs6000.c: Likewise.
* elfxx-riscv.c: Likewise.
* cache.c: Don't include bfd_stdint.h.
* elf32-arm.c: Likewise.
* elf32-avr.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-rl78.c: Likewise.
* elf32-rx.c: Likewise.
* elf32-wasm32.c: Likewise.
* elf64-nfp.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfxx-ia64.c: Likewise.
* elfxx-x86.h: Likewise.
* wasm-module.c: Likewise, and don't include sysdep.h twice.
* elf-nacl.h: Don't include bfd.h.
* mach-o.h: Likewise.
* elfxx-aarch64.c: Include bfd.h and elf-bfd.h.
* elfxx-aarch64.h: Don't include bfd.h, elf-bfd.h or stdint.h.
* mach-o-aarch64.c: Include mach-o.h later.
* mach-o-arm.c: Likewise.
* mach-o-i386.c: Likewise.
* mach-o-x86-64.c: Likewise.
* mach-o.c: Likewise.
* sysdep.h: Don't include ansidecl.h or sys/stat.h.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
opcodes/
* arm-dis.c: Include bfd.h.
* aarch64-opc.c: Include bfd_stdint.h rather than stdint.h.
* csky-dis.c: Likewise.
* nds32-asm.c: Likewise.
* riscv-dis.c: Likewise.
* s12z-dis.c: Likewise.
* wasm32-dis.c: Likewise.
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alignment correctly for the Elf32_Chdr or Elf64_Chdr type and respect the ch_addralign field when decompressing the section data.
PR binutils/23919
binutils* readelf.c (dump_sections_as_strings): Remove bogus addralign check.
(dump_sections_as_bytes): Likewise.
(load_specific_debug_sections): Likewise.
* testsuite/binutils-all/dw2-3.rS: Adjust alignment.
* testsuite/binutils-all/dw2-3.rt: Likewise.
bfd * bfd.c (bfd_update_compression_header): Explicitly set alignment.
(bfd_check_compression_header): Add uncompressed_alignment_power
argument. Check ch_addralign is a power of 2.
* bfd-in2.h: Regenerated.
* compress.c (bfd_compress_section_contents): Get and set
orig_uncompressed_alignment_pow if section is decompressed.
(bfd_is_section_compressed_with_header): Add and get
uncompressed_align_pow_p argument.
(bfd_is_section_compressed): Add uncompressed_align_power argument
to bfd_is_section_compressed_with_header call.
(bfd_init_section_decompress_status): Get and set
uncompressed_alignment_power.
* elf.c (_bfd_elf_make_section_from_shdr): Add
uncompressed_align_power argument to
bfd_is_section_compressed_with_header call.
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I should know better than to introduce the first use of size_t in
bfd.h.
PR 23534
* init.c (bfd_init): Return an unsigned int.
bfd-in2.h: Regenerate.
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This patch performs a run-time test that a shared libbfd.so has been
compiled with the same size bfd_vma as that of apps using the library.
On a 32-bit host it is easily possible to have one libbfd.so compiled
to support 64-bit targets (or configured with --enable-64-bit-bfd)
while another only supports 32-bit targets. The two libraries will
have differently sized bfd_vma types, and if the wrong one is loaded
all sorts of weird behaviour might be seen.
bfd/
PR 23534
* init.c (BFD_INIT_MAGIC): Define.
(bfd_init): Return BFD_INIT_MAGIC.
bfd-in2.h: Regenerate.
binutils/
PR 23534
* addr2line.c (main): Exit with fatal error if bfd_init
returns an unexpected value.
* ar.c (main): Likewise.
* dlltool.c (identify_dll_for_implib): Likewise.
* nm.c (main): Likewise.
* objcopy.c (main): Likewise.
* objdump.c (main): Likewise.
* size.c (main): Likewise.
* strings.c (main): Likewise.
* windmc.c (main): Likewise.
* windres.c (main): Likewise.
gas/
PR 23534
* as.c (main): Exit with fatal error if bfd_init returns an
unexpected value.
ld/
PR 23534
* ldmain.c (main): Exit with fatal error if bfd_init returns
an unexpected value.
|
|
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
|
|
This patch adds the following target relocations:
- BFD_RELOC_HI16_S High 16-bit relocation, for used with signed
asm: ha() lower.
- BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local
asm: gotoffha() symbols, for use with signed lower.
- BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial
asm: gottpoffha() executable calculation, for use with signed
lower.
- BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable
asm: tpoffha() variables, for use with signed lower.
- BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with
asm: lo() OpenRISC store instructions.
- BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for
asm: gotofflo() local symbols, used with OpenRISC store
instructions.
- BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local
asm: tpofflo() executable variables, used with OpenRISC store
instructions.
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* bfd-in2.h: Regenerated.
* elf32-or1k.c (N_ONES): New macro.
(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
BFD_RELOC_OR1K_TLS_LE_SLO16.
(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
also check results before returning.
(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
limit.
(or1k_final_link_relocate): New function.
(or1k_elf_relocate_section): Add support for new AHI and SLO
relocations. Use or1k_final_link_relocate instead of generic
_bfd_final_link_relocate.
(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
and BFD_RELOC_OR1K_GOTOFF_LO16.
* libbfd.h: Regenerated.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc: Add RTYPE_ enum.
(INVALID_STORE_RELOC): New string.
(or1k_imm16_relocs): New array array.
(parse_reloc): New static function that just does the parsing.
(parse_imm16): New static function for generic parsing.
(parse_simm16): Change to just call parse_imm16.
(parse_simm16_split): New function.
(parse_uimm16): Change to call parse_imm16.
(parse_uimm16_split): New function.
* or1korbis.cpu (simm16-split): Change to use new simm16_split.
(uimm16-split): Change to use new uimm16_split.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
* testsuite/gas/or1k/reloc-1.d: New file.
* testsuite/gas/or1k/reloc-1.s: New file.
* testsuite/gas/or1k/reloc-2.l: New file.
* testsuite/gas/or1k/reloc-2.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/offsets1.d: New file.
* testsuite/ld-or1k/offsets1.s: New file.
* testsuite/ld-or1k/or1k.exp: New file.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerate.
|
|
binutils on upstream!
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.
ld * emultempl/nds32elf.em (hyper_relax): New variable.
(nds32_elf_create_output_section_statements):
the parameters of bfd_elf32_nds32_set_target_option
(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
* (nds32_elf_create_output_section_statements): Updated.
* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.
include * elf/nds32.h: Remove the unused target features.
* dis-asm.h (disassemble_init_nds32): Declared.
* elf/nds32.h (E_NDS32_NULL): Removed.
(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
* opcode/nds32.h: Ident.
(N32_SUB6, INSN_LW): New macros.
(enum n32_opcodes): Updated.
* elf/nds32.h: Doc fixes.
* elf/nds32.h: Add R_NDS32_LSI.
* elf/nds32.h: Add new relocations for TLS.
gas * config/tc-nds32.c: Remove the unused target features.
(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
nds32_apply_fix): Likewise.
(nds32_no_ex9_begin): Removed.
* config/tc-nds32.c (add_mapping_symbol_for_align,
make_mapping_symbol, add_mapping_symbol): New functions.
* config/tc-nds32.h (enum mstate): New.
(nds32_segment_info_type): Likewise.
* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
* config.in: Regenerated.
* configure: Regenerated.
* config/tc-nds32.c (nds32_dx_regs):
Set the value according to the configuration.
(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
Likewise.
(nds32_dsp_ext): New variable. Set the value according to the
configuration.
(nds32_zol_ext): Likewise.
(asm_desc, nds32_pseudo_opcode_table): Make them static.
(nds32_set_elf_flags_by_insn): Updated.
(nds32_check_insn_available): Updated.
(nds32_str_tolower): New function.
* config/tc-nds32.c (relax_table): Updated.
(md_begin): Updated.
(md_assemble): Use XNEW macro to allocate space for `insn.info',
and then remember to free it.
(md_section_align): Cast (-1) to ValueT.
(nds32_get_align): Cast (~0U) to addressT.
(nds32_relax_branch_instructions): Updated.
(md_convert_frag): Add new local variable `final_r_type'.
(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
All callers changed.
* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
(struct nds32_hint_map): Add `option_list' field.
(struct suffix_name, suffix_table): Remove the unused `pic' field.
(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
(relax_hint_bias, relax_hint_id_current): New static variables.
(reset_bias, relax_hint_begin): New variables.
(nds_itoa): New function.
(CLEAN_REG, GET_OPCODE): New macros.
(struct relax_hint_id): New.
(nds32_relax_hint): For .relax_hint directive, we can use `begin'
and `end' to mark the relax pattern without giving exactly id number.
(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
directives are attached to pseudo instruction.
(nds32_elf_save_pseudo_pattern): Change the second parameter from
instruction's opcode to byte code.
(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
`pseudo_hint'.
(nds32_lookup_pseudo_opcode): Fix the overflow issue.
(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
Updated.
* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
NDS32_RELAX_HINT_LA_GOTOFF.
* config/tc-nds32.h (relax_ls_table): Add floating load/store
to gp relax pattern.
(hint_map, nds32_find_reloc_table): Likewise.
* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-nds32.h (enum nds32_ramp): Updated.
(enum nds32_relax_hint_type): Likewise.
* config/tc-nds32.c: Include "errno.h" and "limits.h".
(relax_ls_table): Add TLS relax patterns.
(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
each instructions of TLS patterns.
(nds32_elf_record_fixup_exp): Updated.
(nds32_apply_fix): Likewise.
(suffix_table): Add TLSDESC suffix.
binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
from 215 to 255 for NDS32.
bfd * elf32-nds32.c (nds32_elf_relax_loadstore):
Remove the unused target features.
(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
calculate_plt_offset, calculate_got_memory_address,
nds32_elf_check_dup_relocs): Removed.
All callers changed.
* elf32-nds32.h: Remove the unused macros and defines.
(elf_nds32_link_hash_table): Remove the unused variable.
(bfd_elf32_nds32_set_target_option): Update prototype.
(nds32_elf_ex9_init): Removed.
* elf32-nds32.c (nds32_convert_32_to_16): Updated.
* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
to initialize array nds32_elf_howto_table in any order
without lots of EMPTY_HOWTO.
(nds32_reloc_map): Updated.
* reloc.c: Add BFD_RELOC_NDS32_LSI.
* bfd-in2.h: Regenerated.
* bfd/libbfd.h: Regenerated.
* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
(nds32_reloc_map): Likewise.
(nds32_elf_relax_flsi): New function.
(nds32_elf_relax_section): Support floating load/store relaxation.
* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
New macro.
(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
New functions.
(nds32_info_to_howto_rel): Add BFD_ASSERT.
(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
(nds32_elf_final_sda_base): Improve it to find the better gp value.
(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
(create_got_section): Likewise.
(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
(nds32_elf_check_relocs): Fix the issue that the shared library may
has TEXTREL entry in the dynamic section.
(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
dynamic entry.
(calculate_offset): Remove the unused parameter `pic_ext_target' and
related codes.
All callers changed.
(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
will cause some errors for our test cases.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
generic object.
* reloc.c: Add TLS relocations.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* elf32-nds32.h (struct section_id_list_t): New.
(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
New prototypes.
(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
New macro.
(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
elf_nds32_link_hash_table): Updated.
* elf32-nds32.c (enum elf_nds32_tls_type): New.
(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
fls, ones32, list_insert, list_insert_sibling, dump_chain,
elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
(elf_nds32_obj_tdata): Add new fields.
(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
(nds32_elf_howto_table): Add TLS relocations.
(nds32_reloc_map): Likewise.
(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
nds32_elf_check_relocs, allocate_dynrelocs): Updated.
(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
(dtpoff_base): Rename it to `gottpof' and then update it.
opcodes * nds32-asm.c (operand_fields): Remove the unused fields.
(nds32_opcodes): Remove the unused instructions.
* nds32-dis.c (nds32_ex9_info): Removed.
(nds32_parse_opcode): Updated.
(print_insn_nds32): Likewise.
* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
build_opcode_hash_table): New functions.
(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
nds32_opcode_table): New.
(hw_ktabs): Declare it to a pointer rather than an array.
(build_hash_table): Removed.
* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
SYN_ROPT and upadte HW_GPR and HW_INT.
* nds32-dis.c (keywords): Remove const.
(match_field): New function.
(nds32_parse_opcode): Updated.
* disassemble.c (disassemble_init_for_target):
Add disassemble_init_nds32.
* nds32-dis.c (eum map_type): New.
(nds32_private_data): Likewise.
(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
(print_insn_nds32): Updated.
* nds32-asm.c (parse_aext_reg): Add new parameter.
(parse_re, parse_re2, parse_aext_reg): Only reduced registers
are allowed to use.
All callers changed.
* nds32-asm.c (keyword_usr, keyword_sr): Updated.
(operand_fields): Add new fields.
(nds32_opcodes): Add new instructions.
(keyword_aridxi_mx): New keyword.
* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
and NASM_ATTR_ZOL.
(ALU2_1, ALU2_2, ALU2_3): New macros.
* nds32-dis.c (nds32_filter_unknown_insn): Updated.
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There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
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bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs264e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS264E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs264e to
bfd_mach_mips_gs464e extension.
binutils/
* NEWS: Mention Loongson 2K1000 proccessor support.
* readelf.c (get_machine_flags): Handle gs264e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
(mips_cpu_info_table): Add gs264e descriptors.
* doc/as.texi (march table): Add gs264e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
* opcode/mips.h (CPU_XXX): New CPU_GS264E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs264e and gs464e.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
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bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs464e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS464E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs464e to
bfd_mach_mips_gs464 extension.
binutils/
* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
* readelf.c (get_machine_flags): Handle gs464e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
(mips_cpu_info_table): Add gs464e descriptors.
* doc/as.texi (march table): Add gs464e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
* opcode/mips.h (CPU_XXX): New CPU_GS464E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs464e and gs464.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
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bfd/
* archures.c (bfd_architecture): Rename
bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Likewise.
(bfd_mips_isa_ext_mach): Likewise.
(bfd_mips_isa_ext): Likewise.
(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
binutils/
* NEWS: Mention Loongson 3A1000 proccessor support.
* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
elfcpp/
* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
E_MIPS_MACH_GS464.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
CPU_LOONGSON_3A to CPU_GS464.
(mips_cpu_info_table): Add gs464 descriptors, Keep
loongson3a as an alias of gs464 for compatibility.
* doc/as.texi (march table): Rename loongson3a to gs464.
* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
flag to None.
gold/
* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
Rename loongson3a to gs464.
(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
(infer_abiflags): Use ases instead of isa_ext for infer ABI
flags.
(elf_mips_mach_name): Rename loongson3a to gs464.
include/
* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
E_MIPS_MACH_GS464.
(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
to gs464.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
loongson3a as an alias of gs464 for compatibility.
* mips-opc.c (mips_opcodes): Change Comments.
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This patch uses bitfields in reloc_howto_struct, reducing its size
from 80 to 40 bytes on 64-bit hosts and from 52 to 32 bytes on 32-bit
hosts (with a 32-bit bfd_vma). I've also added a new "negate" field
rather than making the encoded "size" field do double duty as both
a size and a flag.
There was just one use of an encoded size of 8, which according to
bfd_get_reloc_size meant 16 bytes, in vms-alpha.c ALPHA_R_LINKAGE.
See git commit c3d8e071bf adding ALPHA_R_LINKAGE and git commit
8612a388f7 decoding size 8 in bfd_get_reloc_size. Since no other part
of BFD handles 16 byte relocs, I've removed that encoding and special
cased the ALPHA_R_LINKAGE size in vms-alpha.c.
* reloc.c (reloc_howto_type): Typedef.
(bfd_symbol): Delete forward declaration.
(struct reloc_howto_struct): Add "negate" field. Make "size",
"bitsize", "rightshift", "bitpos", "complain_on_overflow",
"pc_relative", "partial_inplace", and "pcrel_offset" bitfields.
Rearrange for better packing. Revise comments.
(HOWTO): Map to rearranged reloc_howto_struct.
(bfd_get_reloc_size): Delete now unused cases.
(read_reloc, write_reloc): Likewise.
(apply_reloc, _bfd_relocate_contents): Test howto->negate
rather than howto->size < 0 for negated relocation values.
* coff-rs6000.c (xcoff_complain_overflow_bitfield_func): Avoid
signed/unsigned warning.
(xcoff_ppc_relocate_section): Delete "condition is always false"
code.
* coff64-rs6000.c (xcoff64_ppc_relocate_section): Likewise.
* cpu-ns32k.c (do_ns32k_reloc): Adjust to suit reloc_howto_struct
changes.
* vms-alpha.c (_bfd_vms_write_etir, alpha_vms_slurp_relocs): Use
size 16 for ALPHA_R_LINKAGE.
(alpha_howto_table <ALPHA_R_LINKAGE>): Set encoded size and
bitsize to zero.
* bfd-in.h (reloc_howto_type): Delete.
* bfd-in2.h: Regenerate.
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NEWHOWTO was promised way back in 1991 (git commit e5683622186).
I doubt it's ever going to be implemented. This patch removes it,
and tidies some reloc howtos. I was going to make some changes to
reloc_howto_struct, so I think it's important that all relocs howtos
are initialized with HOWTO.
* reloc.c (HOWTO): Revise comment.
(NEWHOWTO, HOWTO_PREPARE): Delete.
* coff-arm.c (coff_arm_reloc_type_lookup): Replace const struc
reloc_howto_struct with reloc_howto_type.
* ns32knetbsd.c (MY_bfd_reloc_type_lookup): Likewise.
* vms-alpha.c (alpha_vms_bfd_reloc_type_lookup): Likewise.
* elf-hppa.h (HOW): Define.
(elf_hppa_howto_table): Use it to simplify this table, correcting
name of R_PARISC_LTOFF16WF, R_PARISC_LTOFF_FPTR64, and
R_PARISC_LTOFF_FPTR16DF.
* elf32-mep.c (MEPREL): Use HOWTO.
* bfd-in2.h: Regenerate.
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R_PPC64_REL24_NOTOC is used on calls like "bl foo@notoc" to tell the
linker that linkage stubs for PLT calls or long branches can't use r2
for pic addressing. Instead, new stubs that generate pc-relative
addresses are used. One complication is that pc-relative offsets to
the PLT may need to be 64-bit in large programs, in contrast to the
toc-relative addressing used by older PLT linkage stubs where a 32-bit
offset is sufficient until the PLT itself exceeds 2G in size.
.eh_frame info to cover the _notoc stubs is yet to be implemented.
bfd/
* elf64-ppc.c (ADDI_R12_R11, ADDI_R12_R12, LIS_R12),
(ADDIS_R12_R11, ORIS_R12_R12_0, ORI_R12_R12_0),
(SLDI_R12_R12_32, LDX_R12_R11_R12, ADD_R12_R11_R12): Define.
(ppc64_elf_howto_raw): Add R_PPC64_REL24_NOTOC entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_REL24_NOTOC.
(ppc_stub_type): Add ppc_stub_long_branch_notoc,
ppc_stub_long_branch_both, ppc_stub_plt_branch_notoc,
ppc_stub_plt_branch_both, ppc_stub_plt_call_notoc, and
ppc_stub_plt_call_both.
(is_branch_reloc): Add R_PPC64_REL24_NOTOC.
(build_offset, size_offset): New functions.
(plt_stub_size): Support plt_call_notoc and plt_call_both.
(ppc_build_one_stub, ppc_size_one_stub): Support new stubs.
(toc_adjusting_stub_needed): Handle R_PPC64_REL24_NOTOC.
(ppc64_elf_size_stubs): Likewise, and new stubs.
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Likewise.
* reloc.c: Add BFD_RELOC_PPC64_REL24_NOTOC.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @notoc.
(ppc_force_relocation, ppc_fix_adjustable): Handle REL24_NOTOC.
ld/
* testsuite/ld-powerpc/ext.d,
* testsuite/ld-powerpc/ext.s,
* testsuite/ld-powerpc/ext.lnk,
* testsuite/ld-powerpc/notoc.d,
* testsuite/ld-powerpc/notoc.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
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This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
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* libbfd.c (bfd_getb24, bfd_getl24): New functions.
(bfd_get_24, bfd_put_24): New macros.
* bfd-in2.h: Regenerate.
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It is usually possible to tell absolute and ordinary symbols apart in
BFD throughout the link, by checking whether the section that owns the
symbol is absolute or not.
That however does not work for ordinary symbols defined in a linker
script outside an output section statement. Initially such symbols are
entered into to the link hash as absolute symbols, owned by the absolute
section. A flag is set in the internal linker expression defining such
symbols to tell the linker to convert them to section-relative ones in
the final phase of the link. That flag is however not accessible to BFD
linker code, including BFD target code in particular.
Add a flag to the link hash then to copy the information held in the
linker expression. Define a macro, `bfd_is_abs_symbol', for BFD code to
use where determining whether a symbol is absolute or ordinary is
required before the final link phase.
This macro will correctly identify the special `__ehdr_start' symbol as
ordinary throughout link, for example, even though early on it will be
assigned to the absolute section. Of course this does not let BFD code
identify what the symbol's ultimate section will be before the final
link phase has converted this symbol (in `update_definedness').
include/
* bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.
bfd/
* linker.c (bfd_is_abs_symbol): New macro.
* bfd-in2.h: Regenerate.
ld/
* ldexp.c (exp_fold_tree_1) <etree_assign, etree_provide>
<etree_provided>: Copy expression's `rel_from_abs' flag to the
link hash.
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