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2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu5-2/+32
This patch is fixes the '.fpu' behaviour. Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them), but does not reset previous FPU options selected by other means (ie. when using '.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset). Example: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ ADD (already existing bits, does not reset) vfms.f32 s0, s1, s2 @ OK .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR After the patch this becomes: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ RESET TO VFPV2 vfms.f32 s0, s1, s2 @ ERROR .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR gas/ChangeLog: 2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits. (fpu_any): Remove OBJ_ELF guards. * gas/testsuite/gas/arm/fpu-rst.s: New. * gas/testsuite/gas/arm/fpu-rst.d: New. * gas/testsuite/gas/arm/fpu-rst.l: New.
2019-11-12x86: fold EsSeg into IsStringJan Beulich8-11306/+11318
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
2019-11-12x86: eliminate ImmExt abuseJan Beulich18-445/+540
Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12x86: introduce operand type "instance"Jan Beulich9-14228/+14307
Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
2019-11-12Automatic date update in version.inGDB Administrator1-1/+1
2019-11-11Document and extend readline-bindable functionsTom Tromey4-1/+27
This adds readline-bindable function names to a few gdb functions that already had key bindings. This lets users change the bindings. This also removes the gdb-command function. Due to how this function is implemented, it doesn't make sense to allow binding it. Finally, this updates the documentation to reflect these changes. gdb/ChangeLog 2019-11-11 Tom Tromey <tom@tromey.com> * tui/tui.c (tui_initialize_readline): Add new bindable readline functions. gdb/doc/ChangeLog 2019-11-11 Tom Tromey <tom@tromey.com> * gdb.texinfo (TUI Keys): Document readline function names. Change-Id: I2233779b7aefe372f19bd03c8f325733c3385e72
2019-11-11Document operate-and-get-nextTom Tromey2-0/+11
This adds some documentation for the operate-and-get-next readline function that gdb supplies. The text is largely taken from the Bash manual. gdb/doc/ChangeLog 2019-11-11 Tom Tromey <tom@tromey.com> * gdb.texinfo (Editing): Document operate-and-get-next. Change-Id: I9adb16d9ce84bfbda5fe8a2828f668ea878c080c
2019-11-11Use getpwuid_r instead of getpwuidChristian Biesinger2-1/+8
gdb/ChangeLog: 2019-11-11 Christian Biesinger <cbiesinger@google.com> * nat/linux-osdata.c (user_from_uid): Use getpwuid_r. Change-Id: I587359267f8963ef1da6ba0223a1525807a721de
2019-11-11Fix typo in vFile:pwrite documentationTom Tromey2-1/+5
A user on irc noticed that the remote protocol documentation mentioned "vFile:write" -- but this is a typo, there is only "vFile:pwrite". This patch fixes the bug. Tested by rebuilding, committing as obvious. gdb/doc/ChangeLog 2019-11-11 Tom Tromey <tromey@adacore.com> * gdb.texinfo (Host I/O Packets): Fix typo in "vFile:pwrite". Change-Id: I2f668a691eed7883ba6bc092471739f44c82301b
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich5-2/+17
This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
2019-11-11Arm64: fix build with old glibcJan Beulich2-10/+12
Some old glibc versions have string.h surface "index", which some compilers then warn about if shadowed by a local variable. Re-use an existing variable instead.
2019-11-11PR24996, Gold fix for ternary operator within linker scriptsMiguel Saldivar2-2/+9
PR 24996 * expression.cc (Trinary_expression::arg2_value): Use correct integer expression when calling "eval_maybe_dot" method. (Trinary_expression::arg3_value): Likewise.
2019-11-11Automatic date update in version.inGDB Administrator1-1/+1
2019-11-10gdb/python: Introduce gdb.lookup_static_symbolsAndrew Burgess9-0/+142
If gdb.lookup_static_symbol is going to return a single symbol then it makes sense (I think) for it to return a context sensitive choice of symbol, that is the global static symbol that would be visible to the program at that point. However, if the user of the python API wants to instead get a consistent set of global static symbols, no matter where they stop, then they have to instead consider all global static symbols with a given name - there could be many. That is what this new API function offers, it returns a list (possibly empty) of all global static symbols matching a given name (and optionally a given symbol domain). gdb/ChangeLog: * python/py-symbol.c (gdbpy_lookup_static_symbols): New function. * python/python-internal.h (gdbpy_lookup_static_symbols): Declare new function. * python/python.c (python_GdbMethods): Add gdb.lookup_static_symbols method. * NEWS: Mention gdb.lookup_static_symbols. gdb/testsuite/ChangeLog: * gdb.python/py-symbol.exp: Add test for gdb.lookup_static_symbols. gdb/doc/ChangeLog: * python.texi (Symbols In Python): Add documentation for gdb.lookup_static_symbols. Change-Id: I1153b0ae5bcbc43b3dcf139043c7a48bf791e1a3
2019-11-10gdb/python: smarter symbol lookup for gdb.lookup_static_symbolAndrew Burgess8-14/+109
When using gdb.lookup_static_symbol I think that GDB should find static symbols (global symbol with static linkage) from the current object file ahead of static symbols from other object files. This means that if we have two source files f1.c and f2.c, and both files contains 'static int foo;', then when we are stopped in f1.c a call to 'gdb.lookup_static_symbol ("foo")' will find f1.c::foo, and if we are stopped in f2.c we would find 'f2.c::foo'. Given that gdb.lookup_static_symbol always returns a single symbol, but there can be multiple static symbols with the same name GDB is always making a choice about which symbols to return. I think that it makes sense for the choice GDB makes in this case to match what a user would get on the command line if they asked to 'print foo'. gdb/testsuite/ChangeLog: * gdb.python/py-symbol.c: Declare and call function from new py-symbol-2.c file. * gdb.python/py-symbol.exp: Compile both source files, and add new tests for gdb.lookup_static_symbol. * gdb.python/py-symbol-2.c: New file. gdb/doc/ChangeLog: * python.texi (Symbols In Python): Extend documentation for gdb.lookup_static_symbol. gdb/ChangeLog: * python/py-symbol.c (gdbpy_lookup_static_symbol): Lookup in static block of current object file first. Also fix typo in header comment. Change-Id: Ie55dbeb8806f35577b46015deecde27a0ca2ab64
2019-11-10gdb: Add a class to track last display symtab and line informationAndrew Burgess3-73/+148
In stack.c we currently have a set of static global variables to track the last displayed symtab and line. This commit moves all of these into a class and adds an instance of the class to track the same information. The API into stack.c is unchanged after this cleanup. There should be no user visible changes after this commit. gdb/ChangeLog: * stack.c (set_last_displayed_sal): Delete. (last_displayed_sal_valid): Delete. (last_displayed_pspace): Delete. (last_displayed_addr): Delete. (last_displayed_symtab): Delete. (last_displayed_line): Delete. (class last_displayed_symtab_info_type): New. (last_displayed_symtab_info): New static global variable. (print_frame_info): Call methods on last_displayed_symtab_info. (clear_last_displayed_sal): Update header comment, and make use of last_displayed_symtab_info. (last_displayed_sal_is_valid): Likewise. (get_last_displayed_pspace): Likewise. (get_last_displayed_addr): Likewise. (get_last_displayed_symtab): Likewise. (get_last_displayed_line): Likewise. (get_last_displayed_sal): Likewise. * stack.h (clear_last_displayed_sal): Update header comment. (last_displayed_sal_is_valid): Likewise. (get_last_displayed_pspace): Likewise. (get_last_displayed_addr): Likewise. (get_last_displayed_symtab): Likewise. (get_last_displayed_line): Likewise. (get_last_displayed_sal): Likewise. Change-Id: Ia3dbfe267feec03108c5c8ed8bd94fc0a030c3ed
2019-11-10gdb: Convert frame_show_address to return a boolAndrew Burgess3-4/+10
Just a clean up, should be no user visible changes after this commit. gdb/ChangeLog: * stack.c (frame_show_address): Convert return type to bool. * stack.h (frame_show_address): Likewise, and update header comment. Change-Id: Iaaa9ebd4ff6534db19c5329f1c604932c747bd7f
2019-11-10gdb_vecs.h: Avoid self move assignAndrew Burgess4-1/+75
While working on another patch I ran into an issue with unordered_remove (in gdb_vecs.h), where removing the last item of the vector can cause a self move assign. When compiling the C++ standard library in debug mode (with -D_GLIBCXX_DEBUG=1) this causes an error to trigger. I've fixed the issue in this patch and provided a unit test. The provided unit test includes an assignment operator which checks for self move assign, this removes the need to compile with -D_GLIBCXX_DEBUG=1 in order to spot the bug. If you're keen to see the error reported from the C++ standard library then remove operator= from the unit test and recompile GDB with -D_GLIBCXX_DEBUG=1. gdb/ChangeLog: * Makefile.in (SUBDIR_UNITTESTS_SRCS): Add new file to the list. * unittests/vec-utils-selftests.c: New file. * gdbsupport/gdb_vecs.h (unordered_remove): Avoid self move assign. Change-Id: I80247b20cd5212038117db7412865f5e6a9257cd
2019-11-10Remove can_highlight from TUI windowsTom Tromey4-7/+12
Each TUI window has a "can_highlight" member. However, this has the same meaning as "can_box" -- a window can be highlighted if and only if it can be boxed. So, this patch removes can_highlight in favor of simply using can_box. gdb/ChangeLog 2019-11-10 Tom Tromey <tom@tromey.com> * tui/tui-wingeneral.c (tui_unhighlight_win): Use can_box. (tui_highlight_win): Likewise. (tui_win_info::check_and_display_highlight_if_needed): Likewise. * tui/tui-data.h (struct tui_win_info) <can_highlight>: Remove. * tui/tui-command.h (struct tui_cmd_window) <tui_cmd_window>: Don't set can_highlight. Change-Id: I35916859070efcdfcc6e692c71cc6070956dcfce
2019-11-10Remove unused constructor declaration from cli_style_optionTom Tromey2-3/+5
I noticed that cli_style_option declares a constructor that is never defined. This removes it. gdb/ChangeLog 2019-11-10 Tom Tromey <tom@tromey.com> * cli/cli-style.h (class cli_style_option) <cli_style_option>: Remove unused declaration. Change-Id: Ic59ec7eab4d7183d9392b58709354b2d4449b7be
2019-11-10Automatic date update in version.inGDB Administrator1-1/+1
2019-11-09Automatic date update in version.inGDB Administrator1-1/+1
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu9-48/+79
We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
2019-11-08Constify command_line_inputTom Tromey7-9/+20
This changes command_line_input to return a "const char *", which is appropriate because the memory is owned by command_line_input. Then it fixes up the users. I looked at making command_line_input transfer ownership to its caller instead, but this is complicated due to the way read_next_line is called, so I decided against it. Tested by rebuilding. gdb/ChangeLog 2019-11-08 Tom Tromey <tromey@adacore.com> * top.c (read_command_file): Update. (command_line_input): Make return type const. * python/py-gdb-readline.c: Update. * linespec.c (decode_line_2): Update. * defs.h (command_line_input): Make return type const. * cli/cli-script.c (read_next_line): Make return type const. * ada-lang.c (get_selections): Update. Change-Id: I27e6c9477fd1005ab5b16e0d337e4c015b6e6248
2019-11-08Revert "GENERATE_SHLIB_SCRIPT vs. EMBEDDED."Alan Modra15-9/+35
This reverts commit f2aaebdb97977ee7a5c83c02af871e758e7d594b. My reasons for making that change were just plain wrong.
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich9-14566/+14587
This is to further shrink the operand type representation.
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich9-19217/+19240
This is to further shrink the operand type representation.
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich9-14015/+14035
This is to further shrink the operand type representation.
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich10-13819/+13841
This is to further shrink the operand type representation.
2019-11-08x86: introduce operand type "class"Jan Beulich8-146/+238
Many operand types, in particular the various kinds of registers, can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field.
2019-11-08PR25172, Wrong description of --stop-address=ADDR switchAlan Modra2-1/+6
PR 25172 * objdump.c (usage): Correct --stop-address description.
2019-11-08Automatic date update in version.inGDB Administrator1-1/+1
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson6-49/+81
Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. In this last patch, the new Data Gathering Hint mnemonic is introduced. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * testsuite/gas/aarch64/dgh.s: New test. * testsuite/gas/aarch64/dgh.d: New test. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions. (aarch64_opcode_table): Add data gathering hint mnemonic. * opcodes/aarch64-dis-2.c: Account for new instruction. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson10-5/+195
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson19-463/+1225
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson5-0/+98
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat' directive for the AArch64 backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on aarch64-none-elf and aarch64-none-linux-gnu with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format. * testsuite/gas/aarch64/bfloat16-directive-le.d: New test. * testsuite/gas/aarch64/bfloat16-directive-be.d: New test. * testsuite/gas/aarch64/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson5-0/+96
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat16' directive for the Arm backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function (included in the previous patch) in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-arm.c (md_atof): Add encoding for bfloat16 * testsuite/gas/arm/bfloat16-directive-le.d: New test. * testsuite/gas/arm/bfloat16-directive-be.d: New test. * testsuite/gas/arm/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson3-29/+63
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions). This patch contains some general refactoring of the atof_ieee function, exposing a function that allows a higher level of control over the format of IEEE-like floating point numbers. This has been done in order to be able to add a directive for assembling floating point literals in the bfloat16 format in the following patches. Committed on behalf of Mihail Ionescu. Tested on arm-none-eabi, arm-none-linux-gnueabihf, aarch64-none-elf and aarch64-none-linux-gnuwith no issues. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function. (atof_ieee): Move some code into the atof_ieee_detail function. (atof_ieee_detail): Add function that provides a higher level of control over generating IEEE-like numbers. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson22-29/+863
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[Patch][binutils][arm] Create a new generic coprocessor array [3/10]Matthew Malcomson2-51/+98
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. Some generic instructions match a large range of encoding space (e.g. stc, mcr, mrc). Currently these instructions are in the coprocessor_opcodes array, which means they are checked before many other instructions when disassembling arm and thumb32 codes. This patch moves the generic instructions into a separate array to be checked later on. This is done in order to avoid instruction conflict between the generic instructions and newer ones -- this has already been seen with MVE, and is also a problem with BFloat16. One way to avoid the conflict could be to swap the search order between coprocessor_opcodes and neon_opcodes. We avoid this since it's a larger change that may introduce extra bugs (that aren't caught by the testsuite). We have decided against searching the generic array after searching the arm specific and thumb32 specific arrays with a similar reasoning about keeping the change small. Regression tested with arm-none-linux-gnueabihf. Committed on behalf of Mihail Ionescu. opcodes/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_coprocessor, print_insn_generic_coprocessor): Create wrapper functions around the implementation of the print_insn_coprocessor control codes. (print_insn_coprocessor_1): Original print_insn_coprocessor function that now takes which array to look at as an argument. (print_insn_arm): Use both print_insn_coprocessor and print_insn_generic_coprocessor. (print_insn_thumb32): As above. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson18-73/+766
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson7-2/+25
Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
2019-11-07Allow the --output option of the "ar" prorgam to extract files to locations ↵Nick Clifton3-20/+25
outside of the current directory. * ar.c (open_output_file): Check for filename validity before prefixing with output directory. Display the constructed output filename if in verbose mode. (extract_file): Let open_output_file display the filename.
2019-11-07Fix bug merging notes with objcopy when no merging results in zeroes being ↵Nick Clifton2-15/+20
written back into the note section. * objcopy.c (copy_object): Skip note sections that do not have an output section. Always copy note sections, even if no changes are made.
2019-11-07[gdb/contrib] Add words.sh scriptTom de Vries1-0/+129
Add a script that takes a list of files as arguments and output a list of words from the C comments with their frequencies. For: ... $ ./gdb/contrib/words.sh $(find gdb -type f -name "*.c" -o -name "*.h") ... it generates a list of ~15000 words prefixed with frequency. This could be used to generate a dictionary that is kept as part of the sources, against which new code can be checked, generating a warning or error. The hope is that misspellings would trigger this frequently, and rare words rarely, otherwise the burden of updating the dictionary would be too much. And for: ... $ ./gdb/contrib/words.sh -f 1 $(find gdb -type f -name "*.c" -o -name "*.h") ... it generates a list of ~5000 words with frequency 1. This can be used to scan for misspellings manually. Change-Id: I7b119c9a4519cdbf62a3243d1df2927c80813e8b
2019-11-07Remove CR16C supportAlan Modra24-1532/+33
I think it is past time to remove CR16C support. CR16C was added in 2004, and only for ld. gas and binutils support is lacking, and there have been no commits to bfd/elf32-cr16c.c other than warning fixes or global maintainers making changes to all targets. I see no maintainer listed for CR16C, and no commits from anyone at NSC supporting the target. Furthermore, at the time the CR16 support was added in 2007, config.sub was changed upstream to no longer recognise cr16c as a valid cpu. That means the CR16C ld support is only available as a secondary target by configuring with, for example, --enable-targets=all or --enable-targets=cr16c-unknown-elf. No testing of the CR16C target is possible. include/ * elf/cr16c.h: Delete. bfd/ * cpu-cr16c.c: Delete. * elf32-cr16c.c: Delete. * Makefile.am, * archures.c, * config.bfd, * configure.ac, * reloc.c, * targets.c: Remove cr16c support. * Makefile.in, * bfd-in2.h, * configure, * libbfd.h, * po/SRC-POTFILES.in: Regenerate. ld/ * emulparams/elf32cr16c.sh: Delete. * scripttempl/elf32cr16c.sc: Delete. * Makefile.am, * configure.tgt: Remove cr16c support. * NEWS: Mention removal of cr16c. * Makefile.in, * po/BLD-POTFILES.in: Regenerate.
2019-11-07Order targets in ld/configure.tgtAlan Modra2-99/+100
The target list was supposed to be more or less alphabetically sorted, but this wasn't anywhere near the case. The comment about keeping architecture variants together seems odd to me, and is no doubt the reason why ix86 and x86_64 were grouped together, so I removed that comment. The patch doesn't change order of entries for a given cpu. * configure.tgt: Order targets by cpu.
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich17-4135/+4205
Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich14-217/+100
As the comments (here: almost, in the opcode table: fully) correctly state - all register operands except MONITOR's address one are fixed at 32 bit size. Don't print 64-bit registers there. Also adjust x86-64-suffix.d's name such that it wouldn't be identical to x86-64-rep-suffix.d's, but instead resemble that of its sibling x86-64-suffix-intel.d.
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich3-4/+11
These were mistakenly added by d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling"). This addresses part of PR/gas 25167.
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