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ELFv2 functions with localentry:0 are those with a single entry point,
ie. global entry == local entry, and that have no requirement on r2 or
r12, and guarantee r2 is unchanged on return. Such an external
function can be called via the PLT without saving r2 or restoring it
on return, avoiding a common load-hit-store for small functions. The
optimization is attractive. The TOC pointer load-hit-store is a major
reason why calls to small functions that need no register saves, or
with shrink-wrap, no register saves on a fast path, are slow on
powerpc64le.
To be safe, this optimization needs ld.so support to check that the
run-time matches link-time function implementation. If a function
in a shared library with st_other localentry non-zero is called
without saving and restoring r2, r2 will be trashed on return, leading
to segfaults. For that reason the optimization does not happen for
weak functions since a weak definition is a fairly solid hint that the
function will likely be overridden. I'm also not enabling the
optimization by default unless glibc-2.26 is detected, which should
have the ld.so checks implemented.
bfd/
* elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0.
(ppc64_elf_merge_symbol_attribute): Merge localentry bits from
dynamic objects.
(is_elfv2_localentry0): New function.
(ppc64_elf_tls_setup): Default params->plt_localentry0.
(plt_stub_size): Adjust size for tls_get_addr_opt stub.
(build_tls_get_addr_stub): Use a simpler stub when r2 is not saved.
(ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for
optimized localentry:0 stubs.
(ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve.
(ppc64_elf_relocate_section): Leave nop unchanged for optimized
localentry:0 stubs.
(ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in
DT_PPC64_OPT.
* elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0.
include/
* elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
ld/
* emultempl/ppc64elf.em (params): Init plt_localentry0 field.
(enum ppc64_opt): New, replacing OPTION_* defines. Add
OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY.
(PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry.
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry.
* testsuite/ld-powerpc/tlsopt5.d: Update.
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Later CPU generations added optional operands to the ipte/idte
instructions. I've added these with:
https://sourceware.org/ml/binutils/2017-05/msg00316.html ... but
supported the optional operands only with the specific hardware
levels. However, it is more useful to have the optional operands
already in the first versions. Of course they need to be zero there.
Regression-tested with on s390 and s390x. Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-06-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt: Support the optional parameters with the first
versions of ipte/idte.
gas/ChangeLog:
2017-06-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/esa-g5.d: Add ipte tests.
* testsuite/gas/s390/esa-g5.s: Likewise.
* testsuite/gas/s390/zarch-z196.d: Remove ipte tests.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-z990.d: Add idte tests.
* testsuite/gas/s390/zarch-z990.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Remove ipte/idte tests.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
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Rename "mem" related commands, so that their naming is consistent with
the <command-name>_command pattern of naming functions that implement
commands.
gdb/ChangeLog:
* memattr.c (mem_info_command): Rename to ...
(info_mem_command): ... this.
(mem_enable_command): Rename to ...
(enable_mem_command): ... this.
(mem_disable_command): Rename to ...
(disable_mem_command): ... this.
(mem_delete_command): Rename to ...
(delete_mem_command): ... this.
(_initialize_mem): Adjust function names.
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* emultempl/ppc64elf.em (plt-static-chain help): Fix quoting.
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Newer versions of libipt support instruction flow decoder events instead of
indicating those events with flags in struct pt_insn. Add support for them in
GDB.
gdb/
* btrace.c (handle_pt_insn_events): New.
(ftrace_add_pt): Call handle_pt_insn_events. Rename ERRCODE into
STATUS. Split into this and ...
(handle_pt_insn_event_flags): ... this.
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Version 2 of libipt adds an event system to instruction flow decoders and
deprecates indicating events via flags in struct pt_insn. Add configuration
checks to determine which version we have.
gdb/
* configure.ac: Check for pt_insn_event, struct pt_insn.enabled,
and struct pt_insn.resynced.
* configure: Regenerated.
* config.in: Regenerated.
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libiberty/ChangeLog:
2017-05-31 DJ Delorie <dj@redhat.com>
* configure.ac (strnlen): Add to AC_CHECK_DECLS.
* configure: Likewise.
* config.in: Add HACE_DECL_STRNLEN.
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libiberty/ChangeLog:
2017-05-31 Eli Zaretskii <eliz@gnu.org>
* waitpid.c (wait) [__MINGW32__]: Define as a macro
that calls _cwait, so that this function works on MinGW.
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include/ChangeLog:
2017-05-31 Eli Zaretskii <eliz@gnu.org>
* environ.h: Add #ifndef guard.
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instruction.
PR ld/21523
* elf32-arm.c (elf32_arm_final_link_relocate): Install an absolute
value when processing the R_ARM_THM_ALU_PREL_11_0 reloc.
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Currently print_insn_arc relies on BFD mach and ELF private headers to
distinguish between various ARC architectures. Sometimes those values are not
correct or available, mainly in the case of debugging targets without and ELF
file available. Changing a BFD mach is not a problem for the debugger, because
this is a generic BFD field, and GDB, for example, already sets it according to
information provided in XML target description or specified via GDB 'set arch'
command. However, things are more complicated for ELF private headers, since
it requires existing of an actual ELF file. To workaround this problem this
patch allows CPU model to be specified via disassemble info options. If CPU is
specified in options, then it will take a higher precedence than whatever might
be specified in ELF file.
This is mostly needed for ARC EM and ARC HS, because they have the same
"architecture" (mach) ARCv2 and differ in their private ELF headers. Other ARC
architectures can be distinguished between each other purely via "mach" field.
Proposed disassemble option format is "cpu=<CPU>", where CPU can be any valid
ARC CPU name as supported by GAS. Note that this creates a seeming redundancy
with objdump -m/--architecture option, however -mEM and -mHS still result in
"ARCv2" architecture internally, while -Mcpu={HS,EM} would have an actual
effect on disassembler.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* arc-dis.c (enforced_isa_mask): Declare.
(cpu_types): Likewise.
(parse_cpu_option): New function.
(parse_disassembler_options): Use it.
(print_insn_arc): Use enforced_isa_mask.
(print_arc_disassembler_options): Document new options.
binutils/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* doc/binutils.texi: Document new cpu=... disassembler options for ARC.
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This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types)
into a separate file arc-cpu.def. This will allow reuse of CPU type definition
in multiple places where it might be needed, for example in disassembler. This
will help ensure that gas and disassembker use same option values for CPUs.
arc-cpu.def file relies on preprocessor macroses which are defined somewhere
else. This for example multiple C files to include arc-cpu.def, but define
different macroses, therefore creating different structures.
include/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* elf/arc-cpu.def: New file.
gas/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* config/tc-arc.c (cpu_types): Include arc-cpu.def
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
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The general rule for bfd_arch_info_type->compatible (A, B) is that if A and B
are compatible, then this function should return architecture that is more
"feature-rich", that is, can run both A and B. ARCv2, EM and HS all has same
mach number, so bfd_default_compatible assumes they are the same, and returns
an A. That causes issues with GDB, because GDB assumes that if machines are
compatible, then "compatible ()" always returns same machine regardless of
argument order. As a result GDB gets confused because, for example,
compatible(ARCv2, EM) returns ARCv2, but compatible(EM, ARCv2) returns EM,
hence GDB is not sure if they are compatible and prints a warning.
bfd/ChangeLog:
yyyy-mm-dd Anton Kolesov Anton.Kolesov@synopsys.com
cpu-arc.c (arc_compatible): New function.
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ARC600 is already defined as the head of the bfd_arch_arc.
bfd/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* cpu-arc.c (arch_info_struct): Remove duplicate ARC600 entry.
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We can't use stat() to get archive element size. Add bfd_get_file_size
to get size for both normal files and archive elements.
bfd/
PR binutils/21519
* bfdio.c (bfd_get_file_size): New function.
* bfd-in2.h: Regenerated.
binutils/
PR binutils/21519
* objdump.c (dump_relocs_in_section): Replace get_file_size
with bfd_get_file_size to get archive element size.
* testsuite/binutils-all/objdump.exp (test_objdump_f): New
proc.
(test_objdump_h): Likewise.
(test_objdump_t): Likewise.
(test_objdump_r): Likewise.
(test_objdump_s): Likewise.
Add objdump tests on archive.
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This used to hold a pair of pointers to the previous and next function segment
that belong to this function call. Replace with a pair of indices into the
vector of function segments.
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This used to hold a pair of pointers to the previous and next function segment
in execution flow order. It is no longer necessary as the previous and next
function segments now are simply the previous and next elements in the vector
of function segments.
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This used to hold a function segment pointer. Change it to hold an index into
the vector of function segments instead.
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These are no longer needed and might hold invalid addresses once we change the
vector of function segment pointers into a vector of function segment objects
where a reallocation of the vector changes the address of its elements.
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Remove FUNCTION pointer in struct btrace_insn_iterator and use an index into
the list of function segments instead.
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Remove FUNCTION pointer in struct btrace_call_iterator and use an index into
the list of function segments instead.
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This will serve as the access path to the vector of function segments once
the FUNCTION pointer in struct btrace_insn_iterator is removed.
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Directly insert new btrace_function pointers into the vector and have the
vector own these pointers. This allows us to later retrieve these objects by
their number directly after creation whereas at the moment we have to wait
until the vector is fully populated.
This requires to pull btrace_thread_info through different functions but
cleans up the code for freeing the trace.
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gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Fix indentation.
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Change the GDB 8.0 section of the NEWS file to try to follow this order:
* Functional changes
* Added and removed configurations and targets
* New commands
* New options
* MI changes
In particular, there were two "New commands" sections.
gdb/ChangeLog:
* NEWS (Changes in GDB 8.0): Remove extra empty line. Move
"Removed targets and native configurations" up. Merge duplicate
"New commands" sub-sections. Add "New options" sub-sections.
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This test requires calling a function in the inferior, and therefore it
doesn't make sense to run it if the target doesn't support calling
functions from GDB.
gdb/testsuite/ChangeLog:
* gdb.base/watch-cond-infcall.exp: Don't run if target doesn't
support function calls from GDB.
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opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new instruction types RRF_0URF and RRF_0UREFE.
* s390-opc.txt: Fix instruction typs of csdtr and csxtr.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z9-ec.d: Adjust csdtr and csxtr.
* testsuite/gas/s390/zarch-z9-ec.s: Likewise.
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gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/esa-g5.d: Add missing operand to tb
instruction.
* testsuite/gas/s390/esa-g5.s: Likewise.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt: Add missing operand to tb instruction.
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This patch adds missing variants of ipte and idte instructions added with later CPU
generations.
ipte got an optional operand with z196 and another one with zEC12.
idte got an optional operand with zEC12
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new idte/ipte variants.
* s390-opc.txt: Likewise.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z196.d: Add new idte/ipte variants.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
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So far we only had an instruction flag which made an arbitrary number
of operands optional. This limits error checking capabilities for
instructions marked that way. With this patch the optparm flag only
allows a single optional parameter and another one is added (optparm2)
allowing 2 optional arguments. Hopefully we won't need more than that
in the future. So far there will be only a single use of optparm2.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Support new optparm2
instruction flag.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Add new instruction flags optparm2.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-dis.c (s390_print_insn_with_opcode): Support new optparm2
instruction flag.
* s390-mkopc.c (main): Recognize the new instruction flag when
parsing instruction list.
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The per operand optional flag hasn't been used for quite some time.
Cleanup some remains.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Remove S390_OPERAND_OPTIONAL.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Remove code dealing with
S390_OPERAND_OPTIONAL.
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Use these to replace instances of MAX_REGISTER_SIZE.
* defs.h (copy_integer_to_size): New declaration.
* findvar.c (copy_integer_to_size): New function.
(do_cint_test): New selftest function.
(copy_integer_to_size_test): Likewise.
(_initialize_findvar): Likewise.
* mips-fbsd-tdep.c (mips_fbsd_supply_reg): Use raw_supply_integer.
(mips_fbsd_collect_reg): Use raw_collect_integer.
* mips-linux-tdep.c (supply_32bit_reg): Use raw_supply_integer.
(mips64_fill_gregset): Use raw_collect_integer
(mips64_fill_fpregset): Use raw_supply_integer.
* regcache.c (regcache::raw_supply_integer): New function.
(regcache::raw_collect_integer): Likewise.
* regcache.h: (regcache::raw_supply_integer): New declaration.
(regcache::raw_collect_integer): Likewise.
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This patch adds one unit test for gdbarch methods register_to_value and
value_to_register. The test pass different combinations of {regnu, type}
to gdbarch_register_to_value and gdbarch_value_to_register. In order
to do the test, add a new function create_new_frame to create a fake
frame. It can be improved after we converted frame_info to class.
In order to isolate regcache (from target_ops operations on writing
registers, like target_store_registers), the sub-class of regcache in the
test override raw_write. Also, in order to get the right regcache from
get_thread_arch_aspace_regcache, the sub-class of regcache inserts itself
to current_regcache.
Suppose I incorrectly modified the size of buffer as below,
@@ -1228,7 +1228,7 @@ ia64_register_to_value (struct frame_info *frame, int regnum,
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte in[MAX_REGISTER_SIZE];
+ gdb_byte in[1];
/* Convert to TYPE. */
if (!get_frame_register_bytes (frame, regnum, 0,
build GDB with "-fsanitize=address" and run unittest.exp, asan can detect
such error
==2302==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fff98193870 at pc 0xbd55ea bp 0x7fff981935a0 sp 0x7fff98193598
WRITE of size 16 at 0x7fff98193870 thread T0
#0 0xbd55e9 in frame_register_unwind(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1119
#1 0xbd58c8 in frame_register(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1147
#2 0xbd6e25 in get_frame_register_bytes(frame_info*, int, unsigned long, int, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1427
#3 0x70080a in ia64_register_to_value /home/yao/SourceCode/gnu/gdb/git/gdb/ia64-tdep.c:1236
#4 0xbf570e in gdbarch_register_to_value(gdbarch*, frame_info*, int, type*, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch.c:2619
#5 0xc05975 in register_to_value_test /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch-selftests.c:131
Or, even if GDB is not built with asan, GDB just crashes.
*** stack smashing detected ***: ./gdb terminated
Aborted (core dumped)
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* Makefile.in (SFILES): Add gdbarch-selftests.c.
(COMMON_OBS): Add gdbarch-selftests.o.
* frame.c [GDB_SELF_TESTS] (create_new_frame): New function.
* frame.h [GDB_SELF_TESTS] (create_new_frame): Declare.
* gdbarch-selftests.c: New file.
* regcache.h (regcache) <~regcache>: Mark it virtual if
GDB_SELF_TEST.
<raw_write>: Likewise.
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This patches moves global variable current_regcache to a class regcache
static variable (protected) so that the unit test I add in the following
patch can access it (by means of extending class regcache in unit test).
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* regcache.c (current_regcache): Change it to
regcache::current_regcache.
(regcache_observer_target_changed): Update.
(regcache_thread_ptid_changed): Make it a regcache static
method.
(regcache_thread_ptid_changed): Update.
(class regcache_access): New.
(current_regcache_test): Update.
(_initialize_regcache): Update.
* regcache.h: Include forward_list.
(regcache): Declare regcache_thread_ptid_changed and declare
registers_changed_ptid as friend.
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We should use register_size to get register contents instead of
TYPE_LENGTH.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* i387-tdep.c (i387_register_to_value): Use register_size
instead of TYPE_LENGTH.
* m68k-tdep.c (m68k_register_to_value): Likewise.
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gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* i387-tdep.c (i387_convert_register_p): Return false if type
code isn't TYPE_CODE_FLT.
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This patch restricts alpha_convert_register_p from
"TYPE_LENGTH (type) != 8" to "TYPE_LENGTH (type) == 4", because,
- we have check "TYPE_LENGTH (valtype) == 4" in alpha_register_to_value
and alpha_value_to_register,
- alpha lds and sts instruction access 4 bytes,
- comments "It might need to convert the [float] register into the
corresponding [integer] type (see Alpha)" and integer is 4-byte on
alpha,
I think it is the right restrict condition to "TYPE_LENGTH (valtype) == 4".
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-tdep.c (alpha_convert_register_p): Return true if type
length is 4.
(alpha_register_to_value): Remove type length check.
(alpha_value_to_register): Likewise.
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gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* ia64-tdep.c (ia64_convert_register_p): Check type's code is
TYPE_CODE_FLT.
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