Age | Commit message (Collapse) | Author | Files | Lines |
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start-sanitize-tic80
* config/tc-tic80.c (md_pseudo_table): Add entry for bss, which takes
an additional alignment argument.
(find_opcode): Allow O_symbol relocs for any 32 bit field, not just
base relative ones.
(build_insn): Handle O_symbol relocs for any 32 bit field, not just
base relative ones.
end-sanitize-tic80
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regops.d, relocs1.d,
(relocs1.c): Add file for reference.
(relocs1b.d): Split reloc table contents test to different test file.
(relocs2.c): Add test that uses various types (char, short, int, ...) of
static and global variables with data shuffling to generate lots of ld/st
instructions for the different types.
(relocs2.d): New file, expected code for relocs2 test.
(relocs2.lst): New file, TI assembler listing for reference.
(relocs2.s): New file, assembly source for relocs2 test.
(relocs2b.d): New file, expected reloc table contents for relocs2 test.
(tic80.exp): Run the relocs1b, relocs2, and relocs2b tests.
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* as.c: Define stubs for itbl_parse and itbl_init if HAVE_ITBL_CPU
is not defined.
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* configure, configure.in: Move itbl-cpu.h to mips specific configure.
* itbl-ops.h: Include itbl-cpu.h only if HAVE_ITBL_CPU is defined.
* config/tc-mips.h: Define HAVE_ITBL_CPU.
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* gdb.*/*.exp: Call gdb_expect instead of expect.
* lib/gdb.exp(gdb_expect): New function.
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Remove parameters from itbl_get_reg_val and
change itbl_get_insn_name to itbl_get_field.
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* gas/mips/itbl.s: Add comments. Prefix register names with $.
* gas/all/itbl: Generic table for testing for itbl support.
* gas/all/itbl.s: Generic assembly for testing for itbl support.
* gas/mips/itbl-test.c: Moved to gas/all.
* gas/all/itbl-test.c: Moved from gas/mips.
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* config/tc-mips.c: Remove test for itbl_have_entries.
* config/tc-mips.h: Define tc_init_after_args to mips_init_after_args.
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itbl-ops.c. Add itbl-parse.c and itbl-lex.c.
(LEX, LEXFLAGS): Define.
* itbl-ops.c (append_insns_as_macros): Remove bogus ASSERT.
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Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
so that we can increase the size of the mips opcodes table
dynamically.
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Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
so that we can increase the size of the mips opcodes table
dynamically.
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* itbl-lex.l: Fix indentation mistakes from indent program.
* itbl-ops.h: Add include for ansidecl.h.
Add PARAMS around function arguments.
Add declaration for itbl_have_entries.
* itbl-ops.c: Add PARAMS around function arguments.
* Makefile.in: Add itbl build rules.
Add dependancies for itbl files to mips target.
* as.c: Add itbl support.
Add new option "--insttbl" for dynamically extending instruction set.
* as.h: Declare insttbl_file_name;
the name of file defining extensions to the basic instruction set
* configure.in, configure: Add itbl-parse.o, itbl-lex.o, and
itbl-ops.o to extra_objects for mips configuration.
Add include file link from itbl-cpu.h to
config/itbl-${target_cpu_type}.h.
* config/tc-mips.c: Allow copz instructions.
Add notes for future additions to the itbl support.
Add debug macros.
(macro): Call itbl_assemble to assemble itbl instructions.
See if an unknown register is specified in an itbl entry.
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store BITNUM values in the table in one's complement form
to match behavior when assembler is given a raw numeric
value for a BITNUM operand.
* tic80-dis.c (print_operand_bitnum): Ditto.
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description.
start-sanitize-tic80
* config/tc-tic80.h (NEED_FX_R_TYPE): Define.
* config/tc-tic80.c (find_opcode): Add code to support O_symbol
operands.
(build_insn): Grab a frag early so we can use the address in
fixups. Take one's complement of BITNUM values before insertion
in opcode. Add code to support O_symbol operands.
(md_apply_fix): Replace unimplemented warning with implementation.
(md_pcrel_from): Ditto.
(tc_coff_fix2rtype): Ditto.
end-sanitize-tic80
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endmask.lst, regops.lst}: Remove ^M's from end of lines.
* gas/tic80/bitnum.s: Add comment to each line showing value
that symbolic BITNUM assembles to. Add coverage for raw
numeric values for the BITNUM operand.
* gas/tic80/bitnum.d: Update due to bitnum.s changes.
* gas/tic80/regops.d: Update due to opcode library additions
of floating point test BITNUM values that are ambiguous with
the integral ones.
* gas/tic80/relocs1.s: New test case that tests simple relocs.
* gas/tic80/relocs1.d: Expected output for above.
* gas/tic80/relocs1.lst: TI assembler listing for above.
* gas/tic80/tic80.exp: Add relocs1 test.
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with template parameters containing `::'.
* valops.c (search_struct_field, search_struct_method):
Pass correct valaddr parameter to baseclass_offset.
Prevent gdb crashes by making sure that the virtual base pointer
from an user object still points to accessible memory.
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* configure.in (noconfigdirs): Enable ld for d30v.
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* Makefile.in (ed30velf.c): New target.
* configure.tgt (d30v-*-*): New target.
* emulparams/d30velf.sh: New file.
* scripttempl/elfd30v.sc: New file.
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* d30v.h (FLAG_X): Remove unused flag.
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* d30v-opc.c: Removed references to FLAG_X.
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* config/tc-d30v.c (parallel_ok): New function.
* config/tc-d30v.h: Define TARGET_BYTES_BIG_ENDIAN.
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somewhat.
(mn10200_elf_relax_section): Correctly compute a symbol's value
when the symbol is local, but not in the same section as we are
relaxing. Implement abs24 -> abs16, imm24 -> imm16 and d24 -> d16
relaxing.
Another 1.3% size reduction for hello world. Only relaxing left todo is
imm16 -> imm8 and d16 -> d8 where applicable.
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* config/tc-d10v.c (md_pcrel_from_section): Return 0 if
relocation is in different section. Fixes PR11574.
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* gas/d30v/{align.d, align.s, d30.exp, guard.d, guard.s,
inst.d, inst.s, opt.d, opt.s}: Test files for D30V.
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Store lower 16 bits of addend in R_M32R_HI16_[SU]LO insns.
Add small data area support (R_M32R_SDA16).
* reloc.c: Document BFD_RELOC_M32R_SDA16.
* bfd-in2.h,libbfd.h: Regenerated.
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(SHN_M32R_SCOMMON): Define.
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These changes are related to Ian's gas/libgloss changes of Dec 13/Dec 18.
* tc-mips.c (mips_ip): If configured for an embedded ELF system,
don't set the section alignment to 2**4.
* mips/ddb.ld: Align the location counter before setting _gp, and
before setting edata. Remove ALIGN from _gp computation.
* mips/idt.ld, mips/pmon.ld: Before setting _gp, use ALIGN(8) instead
of ALIGN(16). Remove ALIGN from _gp computation.
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(do_scrub_begin): Don't set lex['*'].
(do_scrub_chars): When handling LEX_IS_TWOCHAR_COMMENT_1ST, don't
check for LEX_IS_TWOCHAR_COMMENT_2ND. Instead, just check for
a literal '*'.
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* configure: Rebuild.
* config/te-svr4.h: New file.
* config/tc-m68k.c (m68k_comment_chars): Only include `#' if
TE_SVR4 or TE_DELTA.
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(mn10200_elf_relax_delete_bytes): Likewise.
(mn10200_elf_symbol_address_p): Likewise.
(mn10200_elf_get_relocated_section_contents): Likewise.
(bfd_elf32_bfd_relax_section): Define.
(bfd_elf32_bfd_get_relocated_section_contents): Likewise.
First cut at relaxing linker for the mn10200:
jsr:24 -> jsr:16
jmp:24 -> jmp:16
jmp:16 -> bra:8
bCC .+4;bra:8 -> bCC':8
Reduces code size by about 2.5% for hello world.
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short conditional branch around a long unconditional branch.
Showing the reloc will allow the linker to shorten the long unconditional
branch or remove the long unconditional branch entirely when relaxing.
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the sim directory.
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and being made more generic.
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directory more widely available.
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