aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2015-12-18Cast to enum bfd_endian in arm_get_next_pcs_read_memory_unsigned_integerAntoine Tremblay2-1/+7
This patch fixes the cxx build broken by commit : d9311bfaf572cf14af577a66e79c51c491553552. Pushed as obvious. gdb/ChangeLog: * arm-tdep.c (arm_get_next_pcs_read_memory_unsigned_integer): Cast to enum bfd_endian)
2015-12-18Add documentation to gdb_compileSimon Marchi2-0/+38
This patch adds some documentation to gdb_compile. It describes the various options that can influence compilation. Most of them are handled by DejaGnu, but are not really documented anywhere, so I think it's good to have a quick reference. Not all possible options are described, that would add way to much noise. I chose those that I think are relevant in the context of writing a test case. gdb/testsuite/ChangeLog: * lib/gdb.exp (gdb_compile): Add function doc.
2015-12-18Enable conditional breakpoints for targets that support software single step ↵Antoine Tremblay2-6/+6
in GDBServer This patch enables support for conditional breakpoints if the target supports software single step. This was disabled before as the implementations of software single step were too simple as discussed in https://sourceware.org/ml/gdb-patches/2015-04/msg01110.html. Since these issues are now fixed support can be added back. New tests passing : PASS: gdb.base/cond-eval-mode.exp: set breakpoint condition-evaluation target and related... No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } gdb/gdbserver/ChangeLog: * server.c (handle_query): Call target_supports_software_single_step.
2015-12-18Enable software single stepping for while-stepping actions in GDBServerAntoine Tremblay2-17/+37
This patch enables software single stepping if the targets support it, to do while-stepping actions. No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } gdb/gdbserver/ChangeLog: * linux-low.c (single_step): New function. (linux_resume_one_lwp_throw): Call single_step. (start_step_over): Likewise.
2015-12-18Support software single step on ARM in GDBServerAntoine Tremblay22-1361/+1924
This patch teaches GDBServer how to software single step on ARM linux by sharing code with GDB. The arm_get_next_pcs function in GDB is now shared with GDBServer. So that GDBServer can use the function to return the possible addresses of the next PC. A proper shared context was also needed so that we could share the code, this context is described in the arm_get_next_pcs structure. Testing : No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Append arm-get-next-pcs.o, arm-linux.o. (ALLDEPFILES): Append arm-get-next-pcs.c, arm-linux.c (arm-linux.o): New rule. (arm-get-next-pcs.o): New rule. * arch/arm-get-next-pcs.c: New file. * arch/arm-get-next-pcs.h: New file. * arch/arm-linux.h: New file. * arch/arm-linux.c: New file. * arm.c: Include common-regcache.c. (thumb_advance_itstate): Moved from arm-tdep.c. (arm_instruction_changes_pc): Likewise. (thumb_instruction_changes_pc): Likewise. (thumb2_instruction_changes_pc): Likewise. (shifted_reg_val): Likewise. * arm.h (submask): Move macro from arm-tdep.h (bit): Likewise. (bits): Likewise. (sbits): Likewise. (BranchDest): Likewise. (thumb_advance_itstate): Moved declaration from arm-tdep.h (arm_instruction_changes_pc): Likewise. (thumb_instruction_changes_pc): Likewise. (thumb2_instruction_changes_pc): Likewise. (shifted_reg_val): Likewise. * arm-linux-tdep.c: Include arch/arm.h, arch/arm-get-next-pcs.h arch/arm-linux.h. (arm_linux_get_next_pcs_ops): New struct. (ARM_SIGCONTEXT_R0, ARM_UCONTEXT_SIGCONTEXT, ARM_OLD_RT_SIGFRAME_SIGINFO, ARM_OLD_RT_SIGFRAME_UCONTEXT, ARM_NEW_RT_SIGFRAME_UCONTEXT, ARM_NEW_SIGFRAME_MAGIC): Move stack layout defines to arch/arm-linux.h. (arm_linux_sigreturn_next_pc_offset): Move to arch/arm-linux.c. (arm_linux_software_single_step): Adjust for arm_get_next_pcs implementation. * arm-tdep.c: Include arch/arm-get-next-pcs.h. (arm_get_next_pcs_ops): New struct. (submask): Move macro to arm.h. (bit): Likewise. (bits): Likewise. (sbits): Likewise. (BranchDest): Likewise. (thumb_instruction_changes_pc): Move to arm.c (thumb2_instruction_changes_pc): Likewise. (arm_instruction_changes_pc): Likewise. (shifted_reg_val): Likewise. (thumb_advance_itstate): Likewise. (thumb_get_next_pc_raw): Move to arm-get-next-pcs.c. (arm_get_next_pc_raw): Likewise. (arm_get_next_pc): Likewise. (thumb_deal_with_atomic_sequence_raw): Likewise. (arm_deal_with_atomic_sequence_raw): Likewise. (arm_deal_with_atomic_sequence): Likewise. (arm_get_next_pcs_read_memory_unsigned_integer): New function. (arm_get_next_pcs_addr_bits_remove): Likewise. (arm_get_next_pcs_syscall_next_pc): Likewise. (arm_get_next_pcs_is_thumb): Likewise. (arm_software_single_step): Adjust for arm_get_next_pcs implementation. * arm-tdep.h: (arm_get_next_pc): Remove declaration. (arm_get_next_pcs_read_memory_unsigned_integer): New declaration. (arm_get_next_pcs_addr_bits_remove): Likewise. (arm_get_next_pcs_syscall_next_pc): Likewise. (arm_get_next_pcs_is_thumb): Likewise. (arm_deal_with_atomic_sequence: Remove declaration. * common/gdb_vecs.h: Add CORE_ADDR vector definition. * configure.tgt (aarch64*-*-linux): Add arm-get-next-pcs.o, arm-linux.o. (arm*-wince-pe): Add arm-get-next-pcs.o. (arm*-*-linux*): Add arm-get-next-pcs.o, arm-linux.o, arm-get-next-pcs.o (arm*-*-netbsd*,arm*-*-knetbsd*-gnu): Add arm-get-next-pcs.o. (arm*-*-openbsd*): Likewise. (arm*-*-symbianelf*): Likewise. (arm*-*-*): Likewise. * symtab.h: Move CORE_ADDR vector definition to gdb_vecs.h. gdb/gdbserver/ChangeLog: * Makefile.in (SFILES): Append arch/arm-linux.c, arch/arm-get-next-pcs.c. (arm-linux.o): New rule. (arm-get-next-pcs.o): New rule. * configure.srv (arm*-*-linux*): Add arm-get-next-pcs.o, arm-linux.o. * linux-aarch32-low.c (arm_abi_breakpoint): Remove macro. Moved to linux-aarch32-low.c. (arm_eabi_breakpoint, arm_breakpoint): Likewise. (arm_breakpoint_len, thumb_breakpoint): Likewise. (thumb_breakpoint_len, thumb2_breakpoint): Likewise. (thumb2_breakpoint_len): Likewise. (arm_is_thumb_mode): Make non-static. * linux-aarch32-low.h (arm_abi_breakpoint): New macro. Moved from linux-aarch32-low.c. (arm_eabi_breakpoint, arm_breakpoint): Likewise. (arm_breakpoint_len, thumb_breakpoint): Likewise. (thumb_breakpoint_len, thumb2_breakpoint): Likewise. (thumb2_breakpoint_len): Likewise. (arm_is_thumb_mode): New declaration. * linux-arm-low.c: Include arch/arm-linux.h aarch/arm-get-next-pcs.h, sys/syscall.h. (get_next_pcs_ops): New struct. (get_next_pcs_addr_bits_remove): New function. (get_next_pcs_is_thumb): New function. (get_next_pcs_read_memory_unsigned_integer): Likewise. (arm_sigreturn_next_pc): Likewise. (get_next_pcs_syscall_next_pc): Likewise. (arm_gdbserver_get_next_pcs): Likewise. (struct linux_target_ops) <arm_gdbserver_get_next_pcs>: Initialize. * linux-low.h: Move CORE_ADDR vector definition to gdb_vecs.h. * server.h: Include gdb_vecs.h.
2015-12-18Share regcache function regcache_raw_read_unsignedAntoine Tremblay10-51/+119
This patch is in preparation for software single step support on ARM in GDBServer. It adds a new shared function regcache_raw_read_unsigned and regcache_raw_get_unsigned so that GDB and GDBServer can use the same call to fetch a raw register into an integer. No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } gdb/ChangeLog: * Makefile.in (SFILES): Append common/common-regcache.c. (COMMON_OBS): Append common/common-regcache.o. (common-regcache.o): New rule. * common/common-regcache.h (register_status) New enum. (regcache_raw_read_unsigned): New declaration. * common/common-regcache.c: New file. * regcache.h (enum register_status): Move to common-regcache.h. (regcache_raw_read_unsigned): Likewise. (regcache_raw_get_unsigned): Likewise. gdb/gdbserver/ChangeLog: * Makefile.in (SFILES): Append common/common-regcache.c. (OBS): Append common-regcache.o. (common-regcache.o): New rule. * regcache.c (init_register_cache): Initialize cache to REG_UNAVAILABLE. (regcache_raw_read_unsigned): New function. * regcache.h (REG_UNAVAILABLE, REG_VALID): Replaced by shared register_status enum.
2015-12-18Refactor arm_software_single_step to use regcacheAntoine Tremblay6-79/+212
This patch is in preparation for software single step support on ARM in GDBServer. It refactors arm_*_software_single_step and sub-functions to use regcache instead of frame to access registers so that the code can be shared more easily between GDB and GDBServer. Note also that since the intention is at some point to get rid of frame completely in that function, memory reads have also been replaced by read_memory_unsigned_integer rather than get_frame_memory_unsigned. No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } gdb/ChangeLog: * arm-linux-tdep.c (arm_linux_sigreturn_next_pc_offset): New function. (arm_linux_sigreturn_next_pc): Likewise. (arm_linux_syscall_next_pc): Use regcache instead of frame. (arm_linux_software_single_step): Likewise. * arm-tdep.c (arm_is_thumb): New function. (shifted_reg_va): Use regcache instead of frame. (thumb_get_next_pc_raw): Likewise. (arm_get_next_pc_raw): Likewise. (arm_get_next_pc): Likewise. (thumb_deal_with_atomic_sequence_raw): Likewise. (arm_deal_with_atomic_sequence_raw): Likewise. (arm_deal_with_atomic_sequence): Likewise. (arm_software_single_step): Likewise. * arm-tdep.h (struct gdbarch_tdep): Use regcache for syscall_next_pc. (arm_get_next_pc): Use regcache. (arm_deal_with_atomic_sequence): Likewise. (arm_is_thumb): New declaration. * regcache.c (regcache_raw_get_unsigned): New function. * regcache.h (regcache_raw_get_unsigned): New function declaration.
2015-12-18Share some ARM target dependent code from GDB with GDBServerAntoine Tremblay7-86/+109
This patch is in preparation for software single stepping support on ARM it shares some functions and definitions that will be needed. No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } Not tested: wince/bsd build. gdb/ChangeLog: * arch/arm.c (bitcount): Move from arm-tdep.c. (condition_true): Likewise. * arch/arm.h (Instruction Definitions): Move form arm-tdep.h. (condition_true): Move defenition from arm-tdep.h. (bitcount): Likewise. * arm-tdep.c (condition_true): Move to arch/arm.c. (bitcount): Likewise. * arm-tdep.h (Instruction Definitions): Move to arch/arm.h. * arm-wince-tdep.c: Include arch/arm.h. * armnbsd-tdep.c: Likewise.
2015-12-18Replace breakpoint_reinsert_addr by get_next_pcs operation in GDBServerAntoine Tremblay11-13/+53
This patch in preparation for software single step support on ARM. It refactors breakpoint_reinsert_addr into get_next_pcs so that multiple location can be returned. When software single stepping there can be multiple possible next addresses because we're stepping over a conditional branch instruction, for example. The operation get_next_pcs handles that by returning a vector of all the possible next addresses. Software breakpoints are installed at each location returned. No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } gdb/gdbserver/ChangeLog: * linux-aarch64-low.c (the_low_targets): Rename breakpoint_reinsert_addr to get_next_pcs. * linux-arm-low.c (the_low_targets): Likewise. * linux-bfin-low.c (the_low_targets): Likewise. * linux-cris-low.c (the_low_targets): Likewise. * linux-crisv32-low.c (the_low_targets): Likewise. * linux-low.c (can_software_single_step): Likewise. (install_software_single_step_breakpoints): New function. (start_step_over): Use install_software_single_step_breakpoints. * linux-low.h: New CORE_ADDR vector. (struct linux_target_ops) Rename breakpoint_reinsert_addr to get_next_pcs. * linux-mips-low.c (the_low_targets): Likewise. * linux-nios2-low.c (the_low_targets): Likewise. * linux-sparc-low.c (the_low_targets): Likewise.
2015-12-18Fix formatting in coff-x86_64.cH.J. Lu2-48/+54
* coff-x86_64.c (coff_amd64_reloc): Fix formatting.
2015-12-18Fix formatting of coff-i386.cNick Clifton2-32/+36
* coff-i386.c (coff_i386_reloc): Fix formatting.
2015-12-17Implement --long-plt flag (ARM only).Peter Collingbourne3-21/+127
gold/ PR gold/18780 * arm.cc (Target_arm::do_make_data_plt): Choose PLT generator based on value of --long-plt flag. (Output_data_plt_arm_standard::do_get_plt_entry_size): Moved to Output_data_plt_arm_short. (Output_data_plt_arm_standard::do_fill_plt_entry): Likewise. (Output_data_plt_arm_standard::plt_entry): Likewise. (Output_data_plt_arm_standard::do_fill_first_plt_entry): Fix variable reference. (Output_data_plt_arm_short): New class. (Output_data_plt_arm_short::do_fill_plt_entry): Error out on too large PLT offsets instead of asserting. (Output_data_plt_arm_long): New class. * options.h (General_options): Define --long-plt flag.
2015-12-18Automatic date update in version.inGDB Administrator1-1/+1
2015-12-17MAINTAINERS: Add myself as MIPS maintainerMaciej W. Rozycki2-0/+5
binutils/ * MAINTAINERS: Add myself as MIPS maintainer.
2015-12-17[Patch ARM] Fix build attributes for armv8-a in case of assembler files that ↵Ramana Radhakrishnan1-0/+9
contain no directives. Add missing ChangeLog entry.
2015-12-17Fix PR threads/19354: "info threads" error with multiple inferiorsPedro Alves5-34/+81
Note: this applies on top of: [PATCH] Remove support for LinuxThreads and vendor 2.4 kernels w/ backported NPTL https://sourceware.org/ml/gdb-patches/2015-12/msg00214.html We try to avoid using libthread_db.so to list threads in the inferior when debugging live processes, but the code that decides whether to use it decides incorrectly if you have more than one inferior, and the current inferior doesn't have execution yet. The result is visible as: (gdb) add-inferior Added inferior 2 (gdb) inferior 2 [Switching to inferior 2 [<null>] (<noexec>)] (gdb) info inferiors Num Description Executable 1 process 15397 /home/pedro/gdb/tests/threads * 2 <null> (gdb) info threads Cannot find new threads: generic error (gdb) Fix this by checking whether each inferior has execution rather than just the current inferior. By moving the core updating to linux-nat.c's update_thread_list implementation, this also ends up fixing the lwp-last-seen-running-on-core updating in the case we're debugging a program that uses raw clone rather than pthreads, as linux-thread-db.c isn't pushed in the target stack in that scenario. Tested on x86_64 Fedora 20. gdb/ChangeLog: 2015-12-17 Pedro Alves <palves@redhat.com> PR threads/19354 * linux-nat.c (linux_nat_update_thread_list): Update process cores each lwp was last seen running on here. * linux-thread-db.c (update_thread_core): Delete. (thread_db_update_thread_list_td_ta_thr_iter): Rename to ... (thread_db_update_thread_list): ... this. Skip inferiors with execution. Also call the target beneath. (thread_db_update_thread_list): Delete. gdb/testsuite/ChangeLog: 2015-12-17 Pedro Alves <palves@redhat.com> PR threads/19354 * gdb.multi/info-threads.exp: New file.
2015-12-17Remove support for LinuxThreads and vendor 2.4 kernels w/ backported NPTLPedro Alves12-541/+171
Since we now rely on PTRACE_EVENT_CLONE being available (added in Linux 2.5.46), we're relying on NPTL. This commit removes the support for older LinuxThreads, as well as the workarounds for vendor 2.4 kernels with NPTL backported. - Rely on tkill being available. - Assume gdb doesn't get cancel signals. - Remove code that checks the LinuxThreads restart and cancel signals in the inferior. - Assume that __WALL is available. - Assume that non-leader threads report WIFEXITED. - Thus, no longer need to send signal 0 to check whether threads are still alive. - Update comments throughout. Tested on x86_64 Fedora 20, native and gdbserver. gdb/ChangeLog: * configure.ac: Remove tkill checks. * configure, config.in: Regenerate. * linux-nat.c: Remove HAVE_TKILL_SYSCALL check. Update top level comments. (linux_nat_post_attach_wait): Remove 'cloned' parameter. Use __WALL. (attach_proc_task_lwp_callback): Don't set the cloned flag. (linux_nat_attach): Adjust. (kill_lwp): Remove HAVE_TKILL_SYSCALL check. No longer fall back to 'kill'. (linux_handle_extended_wait): Use __WALL. Don't set the cloned flag. (wait_lwp): Use __WALL. Update comments. (running_callback, stop_and_resume_callback): Delete. (linux_nat_filter_event): Don't stop and resume all lwps. Don't check if the event LWP has previously exited. (check_zombie_leaders): Update comments. (linux_nat_wait_1): Use __WALL. (kill_wait_callback): Don't handle clone processes separately. Use __WALL instead. (linux_thread_alive): Delete. (linux_nat_thread_alive): Return true as long as the LWP is in the LWP list. (linux_nat_update_thread_list): Assume the kernel supports PTRACE_EVENT_CLONE. (get_signo): Delete. (lin_thread_get_thread_signals): Remove LinuxThreads references. No longer check __pthread_sig_restart / __pthread_sig_cancel in the inferior. * linux-nat.h (struct lwp_info) <cloned>: Delete field. * linux-thread-db.c: Update comments. (_initialize_thread_db): Remove LinuxThreads references. * nat/linux-waitpid.c (my_waitpid): No longer emulate __WALL. Pass down flags unmodified. * linux-waitpid.h (my_waitpid): Update documentation. gdb/gdbserver/ChangeLog: * linux-low.c (linux_kill_one_lwp): Remove references to LinuxThreads. (kill_lwp): Remove HAVE_TKILL_SYSCALL check. No longer fall back to 'kill'. (linux_init_signals): Delete. (initialize_low): Adjust. * thread-db.c (thread_db_init): Remove LinuxThreads reference.
2015-12-17Fix one heap buffer overflow in aarch64_push_dummy_callYao Qi2-3/+12
Hi, AddressSanitizer reports an error like this, (gdb) PASS: gdb.base/call-ar-st.exp: continue to tbreak9 print print_long_arg_list(a, b, c, d, e, f, *struct1, *struct2, *struct3, *struct4, *flags, *flags_combo, *three_char, *five_char, *int_char_combo, *d1, *d2, *d3, *f1, *f2, *f3) ================================================================= ==6236==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200008eb50 at pc 0x89e432 bp 0x7fffa3df9080 sp 0x7fffa3df9078 READ of size 5 at 0x60200008eb50 thread T0 #0 0x89e431 in memory_xfer_partial gdb/target.c:1264 #1 0x89e6c7 in target_xfer_partial gdb/target.c:1320 #2 0x89f267 in target_write_partial gdb/target.c:1595^M #3 0x8a014b in target_write_with_progress gdb/target.c:1889^M #4 0x8a0262 in target_write gdb/target.c:1914^M #5 0x89ee59 in target_write_memory gdb/target.c:1492^M #6 0x9a1c74 in write_memory gdb/corefile.c:393^M #7 0x467ea5 in aarch64_push_dummy_call gdb/aarch64-tdep.c:1388 The problem is that an instance of stack_item_t is created to adjust stack for alignment, the item.len is correct, but item.data is buf, which is wrong, because item.len can be greater than the length of buf. This patch sets item.data to NULL, and only update sp (no inferior memory writes on stack for this item). gdb: 2015-12-17 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (struct stack_item_t): Update comments. (pass_on_stack): Set item.data to NULL. (aarch64_push_dummy_call): Call write_memory if si->data isn't NULL.
2015-12-17[Patch ARM] Fix build attributes for armv8-a in case of assembler files that ↵Ramana Radhakrishnan6-3/+31
contain no directives. There is currently a problem in the way in which we produce build attributes for simple assembler files that have armv8-a instructions. In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2 and set the architecture profile to be 'A' rather than not setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use to be Thumb-1. This is a pre-requisite for any v8-m patches that have been posted. arm-none-eabi gas testsuite run. no regressions. 2015-12-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust TAG_ARCH_profile for armv8-a. * gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test. * gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test. * gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test. * gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
2015-12-17Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:Christophe Lyon5-0/+47
2015-12-16 Mickael Guene <mickael.guene@st.com> bfd/ * bfd-in2.h: Regenerate. * reloc.c: Add new relocations. * libbfd.h (bfd_reloc_code_real_names): Add new relocations display names. * elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new relocations. (elf32_arm_reloc_map): Add bfd/arm mapping for new relocations. (elf32_arm_final_link_relocate): Implement new relocations resolution. gas/ * doc/c-arm.texi: Add documentation about new directives * config/tc-arm.c (group_reloc_table): Add mapping between gas syntax and new relocations. (do_t_add_sub): Keep new relocations for add operand. (do_t_mov_cmp): Keep new relocations for mov operand. (insns): Use 'shifter operand with possible group relocation' operand parse code for movs operand. (md_apply_fix): Implement mov and add encoding when new relocations on them. (tc_gen_reloc): Add new relocations. (arm_fix_adjustable): Since offset has a limited range ([0:255]) we disable adjust_reloc_syms() for new relocations. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local.d: New * gas/arm/adds-thumb1-reloc-local.s: New * gas/arm/movs-thumb1-reloc-local.d: New * gas/arm/movs-thumb1-reloc-local.s: New include/ * elf/arm.h: Add new arm relocations. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests_common): Add new relocations tests. * ld-arm/thumb1-adds.d: New * ld-arm/thumb1-adds.s: New * ld-arm/thumb1-movs.d: New * ld-arm/thumb1-movs.s: New
2015-12-16PR gold/17473: Fix gold build with system C++ headers that use <ctype.h>.Roland McGrath2-2/+13
gold/ PR gold/17473 * binary.cc: Move #include "safe-ctype.h" to be last #include.
2015-12-17Automatic date update in version.inGDB Administrator1-1/+1
2015-12-16Fix -Wno-unknown-warning support detectionPedro Alves6-8/+56
Ref: https://sourceware.org/ml/gdb/2015-12/msg00024.html We have code in configure.ac that tries to detect whether the compiler supports each warning and suppress it if not, but that doesn't work with "-Wno-" options, because gcc doesn't error out for -Wno-unknown-warning unless other diagnostics are being produced. See https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html. Handle this by checking whether -Wfoo works when we actually want -Wno-foo. gdb/ChangeLog: 2015-12-16 Pedro Alves <palves@redhat.com> * configure.ac (compiler warning flags): When testing a -Wno-foo option, check whether -Wfoo works instead. * configure: Regenerate. gdb/gdbserver/ChangeLog: 2015-12-16 Pedro Alves <palves@redhat.com> * configure.ac (compiler warning flags): When testing a -Wno-foo option, check whether -Wfoo works instead. * configure: Regenerate.
2015-12-16[C++] Fix -Winvalid-offsetof warnings with g++ 4.4Pedro Alves2-10/+40
Ref: https://sourceware.org/ml/gdb/2015-12/msg00014.html Fixes the build in C++ mode with g++ 4.4: gdb/btrace.h: In function ‘size_t VEC_btrace_insn_s_embedded_size(int)’: gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly) gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_alloc(int)’: gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly) gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_copy(VEC_btrace_insn_s*)’: gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly) gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_merge(VEC_btrace_insn_s*, VEC_btrace_insn_s*)’: gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly) gdb/btrace.h: In function ‘int VEC_btrace_insn_s_reserve(VEC_btrace_insn_s**, int, const char*, unsigned int)’: gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly) gdb/ChangeLog: 2015-12-16 Pedro Alves <palves@redhat.com> * common/vec.h (vec_offset): New macro. (DEF_VEC_ALLOC_FUNC_I, DEF_VEC_ALLOC_FUNC_O): Use it instead of offsetof.
2015-12-16[ARM] Add support for thumb1 pcrop relocations.Mickael Guene16-6/+458
To support thumb1 execute-only code we need to support four new relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC). These relocations allow the static linker to finalize construction of symbol address. Typical sequence of code to get address of the symbol foo is then the following : movs r3, #:upper8_15:#foo lsls r3, #8 adds r3, #:upper0_7:#foo lsls r3, #8 adds r3, #:lower8_15:#foo lsls r3, #8 adds r3, #:lower0_7:#foo This will give following sequence of text and relocations after assembly : 4: 2300 movs r3, #0 4: R_ARM_THM_ALU_ABS_G3_NC foo 6: 021b lsls r3, r3, #8 8: 3300 adds r3, #0 8: R_ARM_THM_ALU_ABS_G2_NC foo a: 021b lsls r3, r3, #8 c: 3300 adds r3, #0 c: R_ARM_THM_ALU_ABS_G1_NC foo e: 021b lsls r3, r3, #8 10: 3300 adds r3, #0 10: R_ARM_THM_ALU_ABS_G0_NC foo
2015-12-16Automatic date update in version.inGDB Administrator1-1/+1
2015-12-15[ARM] Enable CRC by default for ARMv8.1 and later.Matthew Wahab2-3/+11
ARMv8.1 includes CRC as a required extension but the +crc feature isn't enabled by -march=armv8.1-a as it should be. This patch fixes that. opcode/include 2015-12-15 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor feature macro. (ARM_ARCH_V8_2A): Likewise. Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e
2015-12-15Remove refernces to a non-existent silicon errata.Nick Clifton3-14/+9
* doc/c-msp430.texi (MSP430 Options): Remove references to a non-existent silicon errata. * config/tc-msp430.c: Likewise.
2015-12-15Tweak gdb.trace/ftrace.exp for aarch64Yao Qi2-0/+7
Some tests are skipped on aarch64 unexpectedly because arg0exp isn't set. This patch is to set arg0exp to "$x0" for aarch64. gdb/testsuite: 2015-12-15 Yao Qi <yao.qi@linaro.org> * gdb.trace/ftrace.exp: Set arg0exp to "$x0" if target is aarch64*-*-*.
2015-12-15bfd: don't produce corrupt COFF symbol table due to long ELF file name symbolsJan Beulich5-14/+61
The re-writing logic in _bfd_coff_final_link() overwrote the ".file" part of the symbol table entry, due to not coping with the auxiliary entry generated in all cases. Note that while I would have wanted to add a test case, (a) I didn't spot any one testing the base functionality here, and (b) I wasn't able to figure out proper conditionals to use in e.g. ld-elf/elf.exp to check for the necessary PE/PE+ support (which varies by target).
2015-12-15Fix invalid left shift of negative valueDominik Vogt11-33/+55
Fix occurrences of left-shifting negative constants in C code. sim/arm/ChangeLog: * thumbemu.c (handle_T2_insn): Fix left shift of negative value. * armemu.c (handle_v6_insn): Likewise. sim/avr/ChangeLog: * interp.c (sign_ext): Fix left shift of negative value. sim/mips/ChangeLog: * micromips.igen (process_isa_mode): Fix left shift of negative value. sim/msp430/ChangeLog: * msp430-sim.c (get_op, put_op): Fix left shift of negative value. sim/v850/ChangeLog: * simops.c (v850_bins): Fix left shift of negative value.
2015-12-15Update the copyright notices in the affected files.Nick Clifton5-12/+12
PR 19339 * elf-vxworks.h: Update copyright notice. * elf-vxworks.c: Update copyright notice. * elf-nacl.h: Update copyright notice. * elf-nacl.c: Update copyright notice.
2015-12-15Add support for the MRS instruction to the AArch64 simulator.Nick Clifton2-9/+53
* aarch64/simulator.c (system_get): New function. Provides read access to the dczid system register. (do_mrs): New function - implements the MRS instruction. (dexSystem): Call do_mrs for the MRS instruction. Halt on unimplemented system instructions.
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato92-1368/+3800
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-12-15Automatic date update in version.inGDB Administrator1-1/+1
2015-12-14Check for readline support in gdb.base/history-duplicates.exp.Sandra Loosemore2-1/+12
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/history-duplicates.exp: Skip if no readline support.
2015-12-14Skip gdb.base/gdbinit-history.exp on remote hosts.Sandra Loosemore2-0/+12
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/gdbinit-history.exp: Skip for remote-host testing.
2015-12-14Skip gdb.base/gdbhistsize-history.exp on remote hosts.Sandra Loosemore2-0/+12
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/gdbhistsize-history.exp: Skip for remote-host testing.
2015-12-14Skip tests that send ctrl-c to GDB if nointerrupts target property is set.Sandra Loosemore17-57/+137
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/completion.exp: Skip tests that interrupt GDB with ctrl-C if nointerrupts target property is set. * gdb.base/double-prompt-target-event-error.exp: Likewise. * gdb.base/paginate-after-ctrl-c-running.exp: Likewise. * gdb.base/paginate-bg-execution.exp: Likewise. * gdb.base/paginate-execution-startup.exp: Likewise. * gdb.base/random-signal.exp: Likewise. * gdb.base/range-stepping.exp: Likewise. * gdb.cp/annota2.exp: Likewise. * gdb.cp/annota3.exp: Likewise. * gdb.gdb/selftest.exp: Likewise. * gdb.threads/continue-pending-status.exp: Likewise. * gdb.threads/leader-exit.exp: Likewise. * gdb.threads/manythreads.exp: Likewise. * gdb.threads/pthreads.exp: Likewise. * gdb.threads/schedlock.exp: Likewise. * gdb.threads/sigthread.exp: Likewise.
2015-12-14Target remote mode fork and exec event documentationDon Breazeal4-77/+213
This patch implements documentation updates for target remote mode fork and exec events. A summary of the rationale for the changes made here: * Connecting to a remote target -- explain that the two protocols exist. * Connecting in target remote mode -- explain invoking gdbserver for target remote mode, and move remote-specific text from original "Connecting to a remote target" section. * Connecting in target extended-remote mode -- promote this section from "Using the gdbserver Program | Running gdbserver | Multi-Process Mode for gdbserver". Put it next to the target remote mode section. * Host and target files -- collect paragraphs dealing with how to locate symbol files from original sections "Connecting to a remote target" and "Using the gdbserver program | Connecting to gdbserver". * Steps for connecting to a remote target -- used to be "Using the gdbserver program | Connecting to gdbserver" * Remote connection commands -- used to be the bulk of "Connecting to a remote target". Added "target extended-remote" commands and information. gdb/ChangeLog: * NEWS: Announce fork and exec event support for target remote. gdb/doc/ChangeLog: * gdb.texinfo (Forks): Correct Linux kernel version where fork and exec events are supported, add notes about support of these events in target remote mode. (Connecting): Reorganize and clarify distinctions between target remote, extended-remote, and multiprocess. Reorganize related text from separate sections into new sections. (Server): Note effects of target extended-remote mode. Delete section on Multi-Process Mode for gdbserver. Move some text to "Connecting" node.
2015-12-14Target remote mode fork and exec event supportDon Breazeal6-114/+161
This patch implements support for fork and exec events with target remote mode Linux targets. For such targets with Linux kernels 2.5.46 and later, this enables follow-fork-mode, detach-on-fork and fork and exec catchpoints. The changes required to implement this included: * Don't exit from gdbserver if there are still active inferiors. * Allow changing the active process in remote mode. * Enable fork and exec events in remote mode. * Print "Ending remote debugging" only when disconnecting. * Combine remote_kill and extended_remote_kill into a single function that can handle the multiple inferior case for target remote. Also, the same thing for remote_mourn and extended_remote_mourn. * Enable process-style ptids in target remote. * Remove restriction on multiprocess mode in target remote. gdb/gdbserver/ChangeLog: * server.c (process_serial_event): Don't exit from gdbserver in remote mode if there are still active inferiors. gdb/ChangeLog: * inferior.c (number_of_live_inferiors): New function. (have_live_inferiors): Use number_of_live_inferiors in place of duplicate code. * inferior.h (number_of_live_inferiors): Declare new function. * remote.c (set_general_process): Remove restriction on target remote mode. (remote_query_supported): Likewise. (remote_detach_1): Exit in target remote mode only when there is just one live inferior left. (remote_disconnect): Unpush the target directly instead of calling remote_mourn. (remote_kill): Rewrite function to handle both target remote and extended-remote. Call remote_kill_k. (remote_kill_k): New function. (extended_remote_kill): Delete function. (remote_mourn, extended_remote_mourn): Combine functions into one, remote_mourn, and enable extended functionality for target remote. (remote_pid_to_str): Enable "process" style ptid string for target remote. (remote_supports_multi_process): Remove restriction on target remote mode.
2015-12-14Target remote mode fork and exec test updatesDon Breazeal18-65/+49
This patch updates tests for fork and exec events in target remote mode. In the majority of cases this was a simple matter of removing some code that disabled the test for target remote. In a few cases the test needed to be disabled; in those cases the gdb_protocol was checked instead of using the [is_remote target] etc. In a couple of cases we needed to use clean_restart, since target remote doesn't support the run command, and in one case we had to modify an expect expression to allow for a "multiprocess-style" ptid. Tested with the patch that implemented target remote mode fork and exec event support. gdb/testsuite/ChangeLog: * gdb.base/execl-update-breakpoints.exp (main): Enable for target remote. * gdb.base/foll-exec-mode.exp (main): Disable for target remote. * gdb.base/foll-exec.exp (main): Enable for target remote. * gdb.base/foll-fork.exp (main): Likewise. * gdb.base/foll-vfork.exp (main): Likewise. * gdb.base/multi-forks.exp (main): Likewise, and use clean_restart. (proc continue_to_exit_bp_loc): Use clean_restart. * gdb.base/pie-execl.exp (main): Disable for target remote. * gdb.base/watch-vfork.exp (main): Enable for target remote. * gdb.mi/mi-nsthrexec.exp (main): Likewise. * gdb.threads/execl.exp (main): Likewise. * gdb.threads/fork-child-threads.exp (main): Likewise. * gdb.threads/fork-plus-threads.exp (main): Disable for target remote. * gdb.threads/fork-thread-pending.exp (main): Enable for target remote. * gdb.threads/linux-dp.exp (check_philosopher_stack): Allow pid.tid style ptids, instead of just tid. * gdb.threads/thread-execl.exp (main): Enable for target remote. * gdb.threads/watchpoint-fork.exp (main): Likewise. * gdb.trace/report.exp (use_collected_data): Allow pid.tid style ptids, instead of just tid.
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate ↵Matthew Wahab8-1021/+1088
instructions. ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Scalar Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Hd>, <Hs>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift by immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD scalar shift by immediate group. Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab10-1262/+1344
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The new instructions legal make some uses of the 4h vector type that had been invalid. This patch adjusts a test that checks for these uses. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, #<imm> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace tests for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_VSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD shift by immediate group. Change-Id: I3480f63883d54db46562573185da6982f2365ee8
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab8-1101/+1223
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Scalar Pairwise, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar Pairwise instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_PAIR_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp, fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group. Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab7-8/+33
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type, 2H. This patch adds support for this vector type to binutils. The patch adds a new operand qualifier to the enum aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation used by aarch64-dis.c:get_vreg_qualifier_from_value, called when decoding an instruction. Since the new vector type is only used in FP16 scalar pairwise instructions which do not require the function, this patch adjusts the function to ignore the new qualifier. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to take into account new vector type 2H. (vectype_to_qualifier): Likewise. include/opcode/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (enum aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_2H. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.coM> * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment and adjust calculation to ignore qualifier for type 2H. * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
2015-12-14[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.Matthew Wahab2-6/+35
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type. This patch reworks code in the assembler to allow the addition of the new type. The new vector type requires the addtion of a new operand qualifier to the enum aarch64_opnd_qualifier which is defined include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_. The correctness of the GAS utility function tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and ordering of this group. In particular, it makes assumptions about the positions of the members of the group that are not true if a qualifier for type 2H is added before the qualifier for 4H. This patch reworks the function to weaken its assumptions, making it calculate positions in the group from the type (B, H, S, D, Q) and register width. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand qualifier from per-type base and offet. Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab8-1535/+1577
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds an FP16 instruction to the group Adv.SIMD Modified Immediate, making it available when +simd+fp16 is enabled. The instruction added is: FMOV. The form of this instructions is <OP> <Hd>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SIMD_IMM_H): New. (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD modified immediate group. Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab10-1664/+1776
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Across Lanes, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV. The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. The new instructions valid make uses of the 8H and 4H that were previously illegal. The patch adjusts a test for illegal uses of vector types to take this into account. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace test for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_XLANES_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv, fminnmv, fminv to the Adv.SIMD across lanes group. Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab8-1215/+1312
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <Hd>, <Hs>, <V>.h[<idx>] gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the scalar indexed element group. Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
generated by cgit v1.1 at 2024-11-20 01:22:57 +0000