aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2018-03-08x86: fold several AVX512VL templatesJan Beulich6-2058/+404
The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold these as far as possible, and also fold register-only forms. Further folding is possible, but needs other prereq work done first. A note regarding EVEXDYN: This is intended to be used only when no other properties of the template would make is_evex_encoding() return true. In all "normal" cases I think it is preferable to omit this indicator, to keep the table half way readable.
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich5-957/+151
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust VexNDD handling to cope with these, allowing their register and memory forms to be folded.
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich3-86/+21
2018-03-08x86: fold a few AVX512F templatesJan Beulich3-240/+31
The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold them as far as possible. Further folding is possible, but needs other prereq work done first.
2018-03-08x86: fold LWP templatesJan Beulich3-86/+20
Also drop the no longer necessary explicit Disp<N> from them.
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich3-1656/+330
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich6-45/+39
They aren't really useful (anymore?): The conflicting operand size check isn't applicable to any insn validly using respective memory operand sizes (and if they're used wrongly, another error would result), and the logic in process_suffix() can be easily changed to work without them. While re-structuring conditionals in process_suffix() also drop the CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode table.
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich5-7/+64
Some BMI/BMI2 insns allow their middle operands to be a memory one. In such a case, matching register types between operands 0 and 1 as well as 1 and 2 won't help - operands 0 and 2 also need to be checked.
2018-03-08x86: fold redundant expressions in process_suffix()Jan Beulich2-20/+18
There's no point repeatedly evaluating i.types[op].bitfield.reg.
2018-03-08x86: simplify result processing of cpu_flags_match()Jan Beulich2-24/+21
Make more obvious what the success and failure paths are, and in particular that what used to be at the "skip" label can't be reached by what used to be straight line code.
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich19-2/+177
Just like for the AVX/AES and AVX/PCLMUL combinations, AVX/GFN, AVX512F/GFNI, AVX512F/VAES, and AVX512F/PCLMUL need special handling to deal with the pair of required checks specified in the templates.
2018-03-08x86: change AVX512VL handling in cpu_flags_match()Jan Beulich2-11/+9
In order to add an AVX512F counterpart to the present AVX checking, it is better to move the AVX512VL check out of the conditional it's currently in.
2018-03-08x86: drop CPU_FLAGS_32BIT_MATCHJan Beulich2-5/+10
It has become a plain alias of CPU_FLAGS_ARCH_MATCH now.
2018-03-08x86: simplify AVX checks in cpu_flags_match()Jan Beulich2-22/+14
No caller cares about the specifics of CPU_FLAGS_{AES,AVX,PCLMUL}_MATCH, so drop those and fold the nested if()-s.
2018-03-08x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCHJan Beulich2-6/+5
2018-03-08x86: drop bogus NoAVXJan Beulich3-14/+20
These are meaningful only for insns with CpuSSE* (and a few other Cpu*) attribute.
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich3-4/+9
Neither touches any XMM register, so the check is pointless. It is imo even questionable whether in SSE2AVX mode the two should be converted to their AVX counterparts.
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich16-126/+88
When aiming at not mixing SSE and AVX insns, these should be warned about the same way other non-AVX ones are treated.
2018-03-08x86: drop FloatDJan Beulich7-19745/+19755
It can be expressed by D, when making the consumer look at operand size to tell apart both uses.
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich5-8/+728
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning).
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich4-30/+39
Drop "second": For one there's no other source register (the other source operand is in memory), and in Intel syntax such numbering would also be wrong. Take the opportunity and also - properly place declarations ahead of statements - use %u format for unsigned int arguments - fix indentation
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich7-12/+17
These templates exist solely to satisfy gcc's needs, and gcc only produces these with register operands.
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich5-30/+50
This requires a change to ModR/M handling: Recording of displacement types must not discard operand size information. Change the respective code to alter only .disp<N>.
2018-03-08Really remove unnecessary power9 group terminating nopAlan Modra2-4/+8
Oops, not tested well enough. -mpower9 sets all the PPC_OPCODE_POWERn for n <= 9. * config/tc-ppc.c (ppc_handle_align): Correct last patch. Really don't emit a group terminating nop for power9. Simplify cpu tests.
2018-03-08Remove unnecessary power9 group terminating nopAlan Modra2-10/+13
Power9 doesn't have a group terminating nop, so we may as well emit a normal nop for power9. Not that it matters a great deal, I believe ori 2,2,0 will be treated exactly as ori 0,0,0 by the hardware. * config/tc-ppc.c (ppc_handle_align): Don't emit a group terminating nop for power9.
2018-03-07Fix PR binutils/22923.Paul Pluzhnikov2-1/+7
A static buffer in get_ver_flags may overflow when e.g. German translation is longer than English original. Avoid that by expanding the buffer.
2018-03-08Automatic date update in version.inGDB Administrator1-1/+1
2018-03-07Return gdb::optional<std::string> from target_fileio_readlinkTom Tromey7-51/+45
This changes to_fileio_readlink and target_fileio_readlink to return a gdb::optional<std::sring>, and then fixes up the callers and implementations. This allows the removal of some cleanups. Regression tested by the buildbot. gdb/ChangeLog 2018-03-07 Tom Tromey <tom@tromey.com> * linux-tdep.c (linux_info_proc): Update. * target.h (struct target_ops) <to_fileio_readlink>: Return optional<string>. (target_fileio_readlink): Return optional<string>. * remote.c (remote_hostio_readlink): Return optional<string>. * inf-child.c (inf_child_fileio_readlink): Return optional<string>. * target.c (target_fileio_readlink): Return optional<string>.
2018-03-07xtensa: ld: support -z relroMax Filippov2-0/+5
ld/ 2018-03-07 Max Filippov <jcmvbkbc@gmail.com> * emulparams/elf32xtensa.sh (COMMONPAGESIZE): Define.
2018-03-07New option -z,keep-text-section prefix.Sriraman Tallam8-18/+272
This option does not merge certain text sections with prefixes .text.hot, .text.unlikely, .text.startup and .text.exit. * layout.cc (Layout::default_section_order): Check for text section prefixes. (Layout::text_section_name_mapping): New static member. (Layout::text_section_name_mapping_count): New static member. (Layout::match_section_name): New static function. (Layout::output_section_name): Check for text section prefixes. * layout.h (Output_section_order::ORDER_TEXT_HOT): New enum value. (Output_section_order::ORDER_TEXT_STARTUP): New enum value. (Output_section_order::ORDER_TEXT_EXIT): New enum value. (Output_section_order::ORDER_TEXT_UNLIKELY): New enum value. (Layout::text_section_name_mapping): New static member. (Layout::text_section_name_mapping_count): New static member. (Layout::match_section_name): New static function. * options.h (keep_text_section_prefix): New -z option. * testsuite/Makefile.am (keep_text_section_prefix): New test. * testsuite/Makefile.in: Regenerate. * testsuite/keep_text_section_prefix.cc: New test source. * testsuite/keep_text_section_prefix.sh: New test script.
2018-03-07gdb: Add riscv to list of architectures with a save_reggroupAndrew Burgess2-1/+7
The regcache cooked_read test needs to know which architectures have a save_reggroup, riscv does and needs adding to the list. gdb/ChangeLog: * regcache.c (cooked_read_test): Add riscv to the list of architectures that have a save_reggroup.
2018-03-07[PR20402][LD][AARCH64]Don't emit RELATIVE relocation for absolute symbols ↵Renlin Li6-2/+38
which are resolved at static linking time. For absolute symbols which are forced local or not dynamic, the ABS relocation should be resolved at static linking time. Originally, an RELATIVE/ABS relocation will be generated even for absolution symbols for the dynamic linker to resolve. bfd/ 2018-03-07 Renlin Li <renlin.li@arm.com> PR ld/20402 * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Check absolute symbol, and don't emit relocation in specific case. ld/ 2018-03-07 Renlin Li <renlin.li@arm.com> PR ld/20402 * testsuite/ld-aarch64/aarch64-elf.exp: Run new test. * testsuite/ld-aarch64/pr20402.s: New. * testsuite/ld-aarch64/pr20402.d: New.
2018-03-07Fix watching structs in C++Andreas Arnez5-2/+76
Some of the watchpoint logic depends on the fact that the head of the value chain represents the user-specified value to watch. Thus no additional values should be added to the value chain after that. However, if a watchpoint is defined for a C++ structure/class object, then run-time type information (RTTI) may be present. Thus, while constructing the value chain for the watchpoint, the dynamic type is fetched by gnuv3_rrti_type, which invokes value_addr, which then adds a new value to the head of the value chain. This new value represents the pointer to the structure instead of the structure itself. With such a "polluted" value chain the watchpoint logic does not recognize when the user intended to watch a struct, and can_use_hardware_watchpoint returns zero. Instead of a hardware watchpoint, a software watchpoint will then be set for no apparent reason. This is fixed by adding an early exit to gnuv3_rtti_type when the input value is not a dynamic class object. gdb/testsuite/ChangeLog: * gdb.cp/watch-cp.cc: New test. * gdb.cp/watch-cp.exp: New file. gdb/ChangeLog: * gnu-v3-abi.c (gnuv3_rtti_type): Add early exit if the given value is not a dynamic class object.
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu65-3363/+2392
Rewrite NOP generation for fill and code alignment by: 1. Add a 11-byte NOP with another 0x66 prefix. 2. Remove the multi-byte NOP entries which consist of 2 instructions. 3. Select proper NOPs based on ISA and processor tuning. 4. Generate multiple NOPs with the longer NOPs first followed by the shorter NOP. 5. Use jump for larger NOP padding: a. > 8 bytes (2 NOPs) in 16-bit mode. b. > 14 bytes (2 NOPs) for older processors. c. > 77 bytes (7 NOPs) for newer processors. 6. Update MAX_MEM_FOR_RS_ALIGN_CODE to 4095. PR gas/22874 * config/tc-i386.c (f32_5): Removed. (f32_8): Likewise. (f32_9): Likewise. (f32_10): Likewise. (f32_11): Likewise. (f32_12): Likewise. (f32_13): Likewise. (f32_14): Likewise. (f16_5): Likewise. (f16_6): Likewise. (f16_7): Likewise. (f16_8): Likewise. (jump_31): Likewise. (alt64_11): Likewise. (alt64_patt): Likewise. (jump_disp8): New. (jump32_disp32): Likewise. (jump16_disp32): Likewise. (alt_11): Likewise. (f32_patt): Updated. (f16_patt): Likewise. (alt_patt): Add alt_11. (i386_align_code): Merged with ... (i386_generate_nops): This. Rewritten. (fits_in_imm7): Moved before i386_generate_nops. (fits_in_imm31): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to 4095. (i386_align_code): Removed. (HANDLE_ALIGN): Rewritten with i386_generate_nops. * doc/as.texinfo: Update limits of control byte for x86 .nops directive. * testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7. * gas/testsuite/gas/i386/noavx-3.l: Updated. * gas/testsuite/gas/i386/nop-1.d: Likewise. * gas/testsuite/gas/i386/nop-1.s: Likewise. * gas/testsuite/gas/i386/nop-2.d: Likewise. * gas/testsuite/gas/i386/nop-2.s: Likewise. * gas/testsuite/gas/i386/nop-3.d: Likewise. * gas/testsuite/gas/i386/nop-4.d: Likewise. * gas/testsuite/gas/i386/nop-5.d: Likewise. * gas/testsuite/gas/i386/nop-5.s: Likewise. * gas/testsuite/gas/i386/nop-6.d: Likewise. * gas/testsuite/gas/i386/nop-bad-1.l: Likewise. * gas/testsuite/gas/i386/nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-i386.d: Likewise. * gas/testsuite/gas/i386/nops-1-i686.d: Likewise. * gas/testsuite/gas/i386/nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/nops-1.d: Likewise. * gas/testsuite/gas/i386/nops-2-core2.d: Likewise. * gas/testsuite/gas/i386/nops-2-i386.d: Likewise. * gas/testsuite/gas/i386/nops-2.d: Likewise. * gas/testsuite/gas/i386/nops-3-i386.d: Likewise. * gas/testsuite/gas/i386/nops-3-i686.d: Likewise. * gas/testsuite/gas/i386/nops-3.d: Likewise. * gas/testsuite/gas/i386/nops-4-i386.d: Likewise. * gas/testsuite/gas/i386/nops-4-i686.d: Likewise. * gas/testsuite/gas/i386/nops-4.d: Likewise. * gas/testsuite/gas/i386/nops-4a-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5-i686.d: Likewise. * gas/testsuite/gas/i386/nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-6.d: Likewise. * gas/testsuite/gas/i386/nops16-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/testsuite/gas/i386/nops-7.d: New file. * gas/testsuite/gas/i386/nops-7.s: Likewise. * gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
2018-03-07XCOFF disassemblerAlan Modra11-96/+107
xcoff (32-bit) objdump accepted but ignored -M options unless -mpowerpc was also given. This patch fixes that, leaving the default as -Mpwr for xcoff. I've also enabled more tests for xcoff targets. binutils/ * configure.ac: Add objdump_private_desc_xcoff for rs6000. * configure: Regenerate. gas/ * testsuite/gas/ppc/aix.exp: Run for rs6000 too. * testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets. * testsuite/gas/ppc/machine.d: Don't run for PE targets. opcodes/ * disassemble.c (disassembler): Use bfd_arch_powerpc entry for bfd_arch_rs6000. * disassemble.h (print_insn_rs6000): Delete. * ppc-dis.c (powerpc_init_dialect): Handle rs6000. (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. (print_insn_rs6000): Delete.
2018-03-07mips64 rtype_to_howto error statusAlan Modra2-1/+8
* elf64-mips.c (mips_elf64_rtype_to_howto): Return NULL on error. (mips_elf64_slurp_one_reloc_table): Pass on error.
2018-03-07Automatic date update in version.inGDB Administrator1-1/+1
2018-03-06Formatting fixes in rust-exp.yTom Tromey2-10/+13
I noticed a few formatting buglets in rust-exp.y: A couple of lines were too long, and a couple of parser rules did not follow the same formatting as the rest of the code. I'm checking this in as obvious. Tested by rebuilding. 2018-03-06 Tom Tromey <tom@tromey.com> * rust-exp.y: Formatting fixes.
2018-03-06RISC-V: Disallow output format changes.Jim Wilson5-2/+38
PR 22920 * emultempl/riscvelf.em (riscv_create_output_section_statements): New. (LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): New. * testsuite/ld-elf/pr21884.d (#notarget): Add riscv*-*-*. * testsuite/ld-unique/pr21529.d (#notarget): Likewise. * testsuite/ld-srec/srec.exp (run_srec_test): For riscv*-*-* target, call setup_xfail.
2018-03-06gdb/riscv: Remove partial target description supportAndrew Burgess2-37/+6
Some parts of the target description support were committed with the initial riscv patch. As target descriptions are not currently supported on riscv this commit removes the two pieces for code that relate to target description support. It is expected that target description support will be added in the future, at which point this, or similar code will be added back. gdb/ChangeLog: * riscv-tdep.c (riscv_register_name): Remove target description support. (riscv_gdbarch_init): Remove target description check.
2018-03-06gdb/riscv: Remove 'Contributed by....' commentsAndrew Burgess3-10/+6
The GDB coding standard states these lines should never have been added. gdb/ChangeLog: * riscv-tdep.c: Remove 'Contributed by ...' lines from header comment. * riscv-tdep.h: Likewise.
2018-03-06gdb/riscv: Remove use of pseudo registersAndrew Burgess2-25/+6
The code making use of pseudo registers was initially intended to support running 32-bit ABI files on 64-bit riscv targets. However, the implementation was incomplete, and broken. For now I've removed all reference to pseudo registers from the riscv target, we've not lost any functionality, and this cleans up failures in the selftests. Once the riscv target has matured a little we'll probably end up bringing back some of the use of pseudo registers in order to better support running 32-bit executables on a 64-bit target. gdb/ChangeLog: * riscv-tdep.c (riscv_pseudo_register_read): Delete. (riscv_pseudo_register_write): Delete. (riscv_gdbarch_init): Remove all use of pseudo registers.
2018-03-06btrace: Remove ui_out cleanupsSimon Marchi4-82/+35
This patch replaces the cleanups that close the list and tuple of the btrace instruction history output with ui_out_emit_tuple and ui_out_emit_list. This allows removing make_cleanup_ui_out_tuple_begin_end and make_cleanup_ui_out_list_begin_end. This patch (along with the previous ones in the series) was regtested on the buildbot. gdb/ChangeLog: * record-btrace.c (btrace_print_lines): Replace cleanup parameter with RAII equivalents. (btrace_insn_history): Replace cleanup with RAII equivalents. * ui-out.h (make_cleanup_ui_out_list_begin_end, make_cleanup_ui_out_tuple_begin_end): Remove. * ui-out.c (struct ui_out_end_cleanup_data, do_cleanup_end, make_cleanup_ui_out_end, make_cleanup_ui_out_tuple_begin_end, make_cleanup_ui_out_list_begin_end): Remove.
2018-03-06btrace: Remove VEC cleanupsSimon Marchi3-35/+72
This patch replaces two VEC(tp_t) with std::vector<thread_info *>, which allows to remove two cleanups. To make it easier to map the old code to the new code, I added the ordered_remove and unordered_remove functions, which operate on std::vector and do the same as VEC's ordered_remove/unordered_remove. gdb/ChangeLog: * record-btrace.c (record_btrace_maybe_mark_async_event): Change parameter types to std::vector. Use bool. (record_btrace_wait): Replace VEC(tp_t) with std::vector<thread_info *>. * common/gdb_vecs.h (unordered_remove, ordered_remove): New.
2018-03-06btrace: Remove btrace disable cleanupSimon Marchi2-14/+39
This patch removes a cleanup that disables btrace on threads in case of failure, so we don't leave it enabled for some the threads and disabled for the rest. gdb/ChangeLog: * record-btrace.c (record_btrace_disable_callback): Remove. (struct scoped_btrace_disable): New. (record_btrace_open): Use scoped_btrace_disable.
2018-03-06gdb/riscv: Fix type when reading register from regcacheAndrew Burgess2-1/+6
Should use a ULONGEST when reading from the regcache. gdb/ChangeLog: * riscv-tdep.c (riscv_return_value): Change type to ULONGEST for reading values from registers.
2018-03-06gdb/riscv: Additional print format string fixesAndrew Burgess2-2/+7
Another riscv format string fix. gdb/ChangeLog: * riscv-tdep.c (riscv_push_dummy_call): Use core_addr_to_string_nz where appropriate.
2018-03-06gdb/riscv: Fixes to printf format stringsAndrew Burgess2-31/+53
Some of the format strings used in the new riscv target were incorrect, resulting in build failures on some hosts. This commit does the following: 1. Uses core_addr_to_string for formatting CORE_ADDR types. 2. Fixes legacy use of stderr for logging in one place that got missed, instead gdb_stdlog is used. 3. Re-indent a few printf related lines that were wrong. This should resolve some (but not all) of the build failures the new riscv target introduced. gdb/ChangeLog: * riscv-tdep.c (riscv_print_arg_location): Add header comment, change parameter type. Use GDB's print functions, and use core_addr_to_string where appropriate. (riscv_push_dummy_call): Use core_addr_to_string where appropriate, update call to riscv_print_arg_location, and reindent a few lines. (riscv_return_value): Update call to riscv_print_arg_location.
2018-03-06gdb: Initial baremetal riscv supportAndrew Burgess11-0/+3198
This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
2018-03-06gdb/amd64: Ignore zero sized fields when calling functionsAndrew Burgess2-2/+8
In some cases passing an argument to a function on amd64, or attempting to fetch the return value, can trigger an assertion failure within GDB. An example of a type that would trigger such an error is: struct foo_t { long double a; struct { struct { /* Empty. */ } es1; } s1; }; GCC does permit empty structures, so we should probably support this. The test that exposes this bug is in the next commit along with the RiscV support. gdb/ChangeLog: * amd64-tdep.c (amd64_classify_aggregate): Ignore zero sized fields within aggregates.
generated by cgit v1.1 at 2024-11-20 14:31:18 +0000