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2021-11-19[gdb/testsuite] Fix 64-bit dwarf test-cases with -m32Tom de Vries2-9/+58
When running test-case gdb.dwarf2/loc-sec-offset.exp with target board -m32, I run into: ... builtin_spawn -ignore SIGHUP gcc -fno-stack-protector -m32 \ -fdiagnostics-color=never -c -o loc-sec-offset-dw641.o \ loc-sec-offset-dw64.S^M as: loc-sec-offset-dw641.o: unsupported relocation type: 0x1^M loc-sec-offset-dw64.S: Assembler messages:^M loc-sec-offset-dw64.S:29: Error: cannot represent relocation type \ BFD_RELOC_64^M ... Looking at line 29, we have: ... .8byte .Labbrev1_begin /* Abbrevs */ ... It would be nice if the assembler could handle this somehow. But I guess it's not unreasonable that an assembler for a 32-bit architecture will object to handling 64-bit labels. Instead, work around this in the dwarf assembler by emitting: ... .4byte .Labbrev1_begin /* Abbrevs (lsw) */ .4byte 0 /* Abbrevs (msw) */ ... Tested on x86_64-linux with target board unix/-m32. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28383
2021-11-19[gdb/testsuite] Fix gdb.threads/thread-specific-bp.expTom de Vries1-3/+18
On OBS I ran into a failure in test-case gdb.threads/thread-specific-bp.exp: ... (gdb) PASS: gdb.threads/thread-specific-bp.exp: non-stop: continue to end info breakpoint^M Num Type Disp Enb Address What^M 1 breakpoint keep y 0x0000555555555167 in main at $src:36^M breakpoint already hit 1 time^M 2 breakpoint keep y 0x0000555555555151 in start at $src:23^M breakpoint already hit 1 time^M 3 breakpoint keep y 0x0000555555555167 in main at $src:36 thread 2^M stop only in thread 2^M 4 breakpoint keep y 0x000055555555515c in end at $src:29^M breakpoint already hit 1 time^M (gdb) [Thread 0x7ffff7db1640 (LWP 19984) exited]^M Thread-specific breakpoint 3 deleted - thread 2 no longer in the thread list.^M FAIL: gdb.threads/thread-specific-bp.exp: non-stop: \ thread-specific breakpoint was deleted (timeout) ... Fix this by waiting for the "[Thread 0x7ffff7db1640 (LWP 19984) exited]" message before issuing the "info breakpoint command". Tested on x86_64-linux.
2021-11-19gdb/testsuite: Extend tests for print of cv qualifiersChristina Schimpe2-0/+16
This commit supplements whatis and ptype command tests for print of const-volatile qualifiers. gdb/testsuite/ChangeLog: 2021-11-16 Christina Schimpe <christina.schimpe@intel.com> * gdb.cp/ptype-cv-cp.cc: New const and volatile typedef variables. * gdb.cp/ptype-cv-cp.exp: Add new tests.
2021-11-19gdb: Print cv qualifiers if class attributes are substitutedChristina Schimpe3-0/+51
Make ptype print const/volatile qualifiers when template or typedef attributes are substituted. For a programm like ~~~ template<typename DataT> class Cfoo { typedef float myfloat; public: DataT me0; const DataT me1=1; const myfloat me2=2.0; }; int main() { Cfoo<int> cfoo; return 0; } ~~~ gdb outputs the following type for cfoo's attributes: ~~~ (gdb) b 14 Breakpoint 1 at 0x1170: file tmp.cc, line 14. (gdb) run Starting program: /tmp Breakpoint 1, main () at tmp.cc:14 14 return 0; (gdb) ptype cfoo type = class Cfoo<int> [with DataT = int] { public: DataT me0; DataT me1; myfloat me2; private: typedef float myfloat; } ~~~ The cv qualifiers (const in this case) are ignored for me1 and me2. After: ~~~ (gdb) ptype cfoo type = class Cfoo<int> [with DataT = int] { public: DataT me0; const DataT me1; const myfloat me2; private: typedef float myfloat; } ~~~ gdb/ChangeLog: 2021-11-16 Christina Schimpe <christina.schimpe@intel.com> * gdb/c-typeprint.c: Print cv qualifiers in case of parameter substitution. gdb/testsuite/ChangeLog: 2021-11-16 Christina Schimpe <christina.schimpe@intel.com> * gdb.cp/templates.cc: New template class Cfoo with const, template, typdef and integer attributes. * gdb.cp/templates.exp: Add new test using ptype and ptype/r commmands for template class CFoo.
2021-11-19RISC-V: Support new .option arch directive.Nelson Chu14-43/+272
https://github.com/riscv/riscv-asm-manual/pull/67 Format: .option arch, +<extension><version>, ... .option arch, -<extension> .option arch, =<ISA string> The new direcitve is used to enable/disable extensions for the specific code region. For example, .attribute arch, "rv64ic" # arch = rv64i2p0_c2p0 .option push .option arch, +d2p0, -c # arch = rv64i2p0_f2p0_d2p0, f is added implied .option arch, =rv32gc # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0 .option pop # arch = rv64i2p0_c2p0 Note that, 1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c". 2. ".option arch -i" is illegal, since we cannot remove base i extension. 3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version from 2.0 to 3.0. 4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version from 2.0 to the default one according to the chosen isa spec. bfd/ * elfxx-riscv.c (riscv_add_subset): If the subset is already added, and the new versions are not RISCV_UNKNOWN_VERSION, then update the versions to the subset list. (riscv_copy_subset): New function. Copy the subset from list. (riscv_copy_subset_list): New function. Return the new copyed list. (riscv_update_subset): Updated to make .option arch directives workable. * elfxx-riscv.h: Updated. gas/ * config/tc-riscv.c (riscv_subsets): Defined as a pointer. (riscv_rps_as): Init the subset_list to NULL, we will set it later once riscv_opts_stack is created or updated. (struct riscv_option_stack, riscv_opts_stack): Moved forward. (riscv_set_arch): Updated. (s_riscv_option): Support new .option arch directive, to add, remove or update subsets for the specific code region. (riscv_write_out_attrs): Updated. * doc/c-riscv.texi: Added document for new .option arch directive. * testsuite/gas/riscv/option-arch-01a.d: New testcase. * testsuite/gas/riscv/option-arch-01b.d: Likewise. * testsuite/gas/riscv/option-arch-01.s: Likewise.. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/option-arch-02.s: Likewise. * testsuite/gas/riscv/option-arch-fail.d: Likewise. * testsuite/gas/riscv/option-arch-fail.l: Likewise. * testsuite/gas/riscv/option-arch-fail.s: Likewise.
2021-11-19Re: Add multibyte character warning option to the assembler.Alan Modra1-10/+10
On hppa*-hp-hpux* run_dump_test edits the test file, adjusting .comm directives to suit those target's unusual syntax. Thus gas is passed a temporary file name. * testsuite/gas/all/multibyte1.l: Ignore file name.
2021-11-19sim: install various doc filesMike Frysinger8-14/+330
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu15-1/+536
This is the original discussion, https://github.com/riscv/riscv-elf-psabi-doc/pull/190 And here is the glibc part, https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html For binutils part, we need to support a new direcitve: .variant_cc. The function symbol marked by .variant_cc means it need to be resolved directly without resolver for dynamic linker. We also add a new dynamic entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the special attribute in the dynamic symbol table of the object. I heard that llvm already have supported this in their mainline, so I think it's time to commit this. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc flag. It is used to check if relocations for variant CC symbols may be present. (allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC flag, then raise the variant_cc flag of riscv_elf_link_hash_table. (riscv_elf_size_dynamic_sections): Added dynamic entry for variant_cc. (riscv_elf_merge_symbol_attribute): New function, used to merge non-visibility st_other attributes, including STO_RISCV_VARIANT_CC. binutils/ * readelf.c (get_riscv_dynamic_type): New function. (get_dynamic_type): Called get_riscv_dynamic_type for riscv targets. (get_riscv_symbol_other): New function. (get_symbol_other): Called get_riscv_symbol_other for riscv targets. gas/ * config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a variant CC convention. (riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes, but without copying st_other. If a function symbol has special st_other value set via directives, then attaching an IFUNC resolver to that symbol should not override the st_other setting. (riscv_pseudo_table): Support variant_cc diretive. * config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined. * testsuite/gas/riscv/variant_cc-set.d: New testcase. * testsuite/gas/riscv/variant_cc-set.s: Likewise. * testsuite/gas/riscv/variant_cc.d: Likewise. * testsuite/gas/riscv/variant_cc.s: Likewise. include/ * elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1). (STO_RISCV_VARIANT_CC): Defined to 0x80. ld/ * testsuite/ld-riscv-elf/variant_cc-1.s: New testcase. * testsuite/ld-riscv-elf/variant_cc-2.s: Likewise. * testsuite/ld-riscv-elf/variant_cc-now.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-r.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-11-18sim: use program_transform_name for libsimMike Frysinger1-1/+1
Instead of always using target_alias as a prefix on the name, use program_transform_name instead so that the library is scoped in the same way as the run program.
2021-11-18sim: avoid installing headers when there is no simMike Frysinger4-48/+72
If we aren't building any sims, don't install the sim headers as they won't be useful to anyone.
2021-11-19Automatic date update in version.inGDB Administrator1-1/+1
2021-11-18dprintf-execution-x-script.exp: Adjust test for native-extended-gdbserverKevin Buettner1-1/+22
Without this commit, doing... make check RUNTESTFLAGS="--target_board=native-extended-gdbserver" \ TESTS="gdb.base/dprintf-execution-x-script.exp" ...will show one failure. Here's a snippet from gdb.log showing the circumstances - I've trimmed the paths for readability: builtin_spawn gdb -nw -nx -data-directory data-directory -iex set height 0 -iex set width 0 -iex set auto-connect-native-target off -iex set sysroot -ex set height unlimited -x testsuite/gdb.base/dprintf-execution-x-script.gdb --args testsuite/outputs/gdb.base/dprintf-execution-x-script/dprintf-execution-x-script ... Reading symbols from testsuite/outputs/gdb.base/dprintf-execution-x-script/dprintf-execution-x-script... Dprintf 1 at 0x40116e: file testsuite/gdb.base/dprintf-execution-x-script.c, line 38. Breakpoint 2 at 0x40113a: file testsuite/gdb.base/dprintf-execution-x-script.c, line 26. testsuite/gdb.base/dprintf-execution-x-script.gdb:21: Error in sourced command file: Don't know how to run. Try "help target". (gdb) FAIL: gdb.base/dprintf-execution-x-script.exp: load and run script with -x ... GNU gdb (GDB) 12.0.50.20211118-git Copyright (C) 2021 Free Software Foundation, Inc. ... (gdb) set height 0 (gdb) set width 0 (gdb) builtin_spawn gdbserver/gdbserver --once --multi localhost:2346 Listening on port 2346 target extended-remote localhost:2346 Remote debugging using localhost:2346 ... [Tests after this point will pass.] Note that the command which spawns gdb prevents the gdb script from using the native target via "-iex set auto-connect-native-target off". Moreover, the script in question contains a "run" command, so GDB doesn't know how to run (since it's prevented from using the native target and no alternate "target" command has been issued. But, once GDB finishes starting up, the test will spawn a gdbserver and then connect to it. The other (two) tests after this point both pass. I've fixed this by using gdb_test_multiple instead of gdb_test. When a "Don't know how to run message" is received, the test is unsupported. I've also added a comment explaining the reason for needing to check for "Don't know how to run" despite bailing out at the top of the test via: if ![target_can_use_run_cmd] { return 0 }
2021-11-18gdb: fix array-view-selftests.c build with g++ 4.8Simon Marchi1-1/+1
When building with g++ 4.8, I get: CXX unittests/array-view-selftests.o /home/smarchi/src/binutils-gdb/gdb/unittests/array-view-selftests.c:123:42: error: expected 'class' before 'Container' template<template<typename ...> typename Container> ^ I am no C++ template expert, but it looks like if I change "typename" for "class", as the compiler kind of suggests, the code compiles. Change-Id: I9c3edd29fb2b190069f0ce0dbf3bc3604d175f48
2021-11-18gdb: fix ia64-tdep.c build with g++ 4.8Simon Marchi1-5/+4
When building with g++ 4.8, I get: CXX ia64-tdep.o /home/smarchi/src/binutils-gdb/gdb/ia64-tdep.c:3862:1: error: could not convert '{ia64_allocate_new_rse_frame, ia64_store_argument_in_slot, ia64_set_function_addr}' from '<brace -enclosed initializer list>' to 'const ia64_infcall_ops' }; ^ This happens since commit 345bd07cce3 ("gdb: fix gdbarch_tdep ODR violation"), which added default values for ia64_infcall_ops fields. It looks like g++ 4.8 doesn't like initializing the ia64_infcall_ops object using the brace-enclosed initializer list when the ia64_infcall_ops fields are assigned default values. Later compilers don't have a problem with that, so I suppose that the code is correct, but still, change it to make gcc 4.8 happy. Don't initialize the fields of ia64_infcall_ops directly, instead default-initialize ia64_gdbarch_tdep::infcall_ops. Change-Id: I35e3a61abd7b7bbcafe6cb207078c738c5266d76
2021-11-18gdb: move AIX_TEXT_SEGMENT_BASE to rs6000-aix-tdep.c, remove rs6000-tdep.hSimon Marchi4-27/+3
The contents of rs6000-tdep.h (AIX_TEXT_SEGMENT_BASE) is AIX-specific, so I thought that this file should be named rs6000-aix-tdep.h. But there's already a rs6000-aix-tdep.h, so then I though AIX_TEXT_SEGMENT_BASE should simply be moved there, and rs6000-tdep.h deleted. But then I realized that AIX_TEXT_SEGMENT_BASE is only used in rs6000-aix-tdep.c, so move it to the beginning of that file. Change-Id: Ia212c6fae202f31aedb46575821cd642beeda7a3
2021-11-18gdb: rename rs6000-nat.c to rs6000-aix-nat.cSimon Marchi3-2/+2
This file seems to be AIX-specific, according to its contents and configure.nat. Rename it to rs6000-aix-nat.c, to make that clear (and to follow the convention). Change-Id: Ib418dddc6b79b2e28f64431121742b5e87f5f4f5
2021-11-18[gdb/doc] Fix negative repeat count examining memory exampleTom de Vries1-1/+1
The documentation for the examining memory command x contains an example: ... You can also specify a negative repeat count to examine memory backward from the given address. For example, 'x/-3uh 0x54320' prints three halfwords (h) at 0x54314, 0x54328, and 0x5431c. ... The 0x54328 looks like a typo, which was intended to be 0x54318. But the series uses a 4-byte distance, while the halfword size used in the command means a 2-byte distance, so the series should be: ... 0x5431a, 0x5431c, and 0x5431e. ... Fix this by updating the addresses in the example accordingly. Reported here ( https://sourceware.org/pipermail/gdb/2021-November/049784.html ).
2021-11-18Add multibyte character warning option to the assembler.Nick Clifton14-10/+205
* as.c (parse_args): Add support for --multibyte-handling. * as.h (multibyte_handling): Declare. * app.c (scan_for_multibyte_characters): New function. (do_scrub_chars): Call the new function if multibyte warning is enabled. * input-scrub,c (input_scrub_next_buffer): Call the multibyte scanning function if multibyte warnings are enabled. * symbols.c (struct symbol_flags): Add multibyte_warned bit. (symbol_init): Call the multibyte scanning function if multibyte symbol warnings are enabled. (S_SET_SEGMENT): Likewise. * NEWS: Mention the new feature. * doc/as.texi: Document the new feature. * testsuite/gas/all/multibyte.s: New test source file. * testsuite/gas/all/multibyte1.d: New test driver file. * testsuite/gas/all/multibyte1.l: New test expected output. * testsuite/gas/all/multibyte2.d: New test driver file. * testsuite/gas/all/multibyte2.l: New test expected output. * testsuite/gas/all/gas.exp: Run the new tests.
2021-11-18gdb: include gdbarch.h in all files extending gdbarch_tdepSimon Marchi24-0/+31
Commit 345bd07cce33 ("gdb: fix gdbarch_tdep ODR violation") made a bunch of files define a *_gdbarch_tdep class that inherits from a gdbarch_tdep base. But some of these files don't include gdbarch.h, where gdbarch_tdep is defined. This may cause build errors if gdbarch.h isn't already included by chance by some other header file. Avoid this by making them include gdbarch.h. Change-Id: If433d302007e274daa4f656cfc94f769cf1aa68a
2021-11-18gdbsupport: make gdb_assert_not_reached accept a format stringSimon Marchi19-39/+39
Change gdb_assert_not_reached to accept a format string plus corresponding arguments. This allows giving more precise messages. Because the format string passed by the caller is prepended with a "%s:" to add the function name, the callers can no longer pass a translated string (`_(...)`). Make the gdb_assert_not_reached include the _(), just like the gdb_assert_fail macro just above. Change-Id: Id0cfda5a57979df6cdaacaba0d55dd91ae9efee7
2021-11-18gdb fix for catch-syscall.expCarl Love1-2/+4
Remove check_continue "execve" from Proc test_catch_syscall_execve. The check_continue proceedure checs that the command, execve, starts and checks for the return from the command. The execve command starts a new program and thus the return from the command causing the test to fail. The call to proc check_continue "execve" is removed and replaced with just the call to check_call_to_syscall "execve" to verify the command executed. The next test in proc test_catch_syscall_execve verifies that the new program started and hit the break point in main. Update the check for the PowerPC architecture. Power Little Endian systems include "le" in the name. The istarget "power64-*-linux*" check fails to match LE sytems. The expected string is updated to capture both Big Endian and Little Endian systems. Power 10 LE istarget prints as: powerpc64le-unknown-linux-gnu. This patch fixes three failures and the error: ERROR: can't read "arch1": no such variable Patch tested on Power 10 ppc64le GNU/Linux platform.
2021-11-18gdb: PowerPC fix gdb.base/break-interp.expCarl Love3-9/+33
This patch fixes eight test failures on PowerPC for the test gdb.base/break-interp.exp. The patch adds a funtion and registers it to setup the displaced stepping for ppc-linux platform. The patch moves the struct ppc_inferior_data to the ppc-tdep.h include file to make it visible to the ppc-linux-tdep.c and rs6000-tdep.c files. Additionally the function get_ppc_per_inferior is made external in ppc-tdep.h to make it visible in both files. Tested on Power 10 ppc64le-linux with no regressions.
2021-11-18gdb fix PowerPC test gdb.arch/ppc-longdouble.expCarl Love1-1/+1
The test complains of duplicate tests. DUPLICATE: gdb.arch/ppc-longdouble.exp: continue to breakpoint: return The do_test calls gdb_continue_to_breakpoint "return". The duplicates are the result of calling do_test three times with different arguments. This patch fixes the duplicate tests by adding $name to the gdb_continue_to_breakpoint argument. Patch tested on Power 10 ppc64le GNU/Linux, no duplicate tests reported, no new regression errors.
2021-11-18elf/x86: Issue an error on discarded output .plt sectionH.J. Lu5-0/+37
Issue an error, instead of crash, on discarded output .plt section. bfd/ PR ld/28597 * elf32-i386.c (elf_i386_finish_dynamic_sections): Issue an error on discarded output .plt section. * elf64-x86-64.c (elf_x86_64_finish_dynamic_sections): Likewise. ld/ PR ld/28597 * testsuite/ld-elf/pr28597.d: New file. * testsuite/ld-elf/pr28597.s: Likewise. * testsuite/ld-elf/pr28597.t: Likewise.
2021-11-18[gdb/testsuite] Add missing wait in gdb.base/signals-state-child.expTom de Vries1-3/+11
On OBS I ran into: ... (gdb) shell diff -s outputs/gdb.base/signals-state-child/standalone.txt \ outputs/gdb.base/signals-state-child/gdb.txt^M diff: outputs/gdb.base/signals-state-child/standalone.txt: \ No such file or directory^M (gdb) FAIL: gdb.base/signals-state-child.exp: signals states are identical ... I managed to reproduce this by adding "sleep (5)" at the start of main in signals-state-child.c. Fix this by waiting on the result of the spawned command. Tested on x86_64-linux.
2021-11-18Re: Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra2-10/+10
Put bpf back in the 32-bit targets, even though bpf requires a 64-bit bfd. bpf sim support apparently works without being 64-bit. * Makefile.am (TARGET64_LIBOPCODES_CFILES): Move bpf files.. (TARGET32_LIBOPCODES_CFILES): ..to here. * Makefile.in: Regenerate.
2021-11-18Pass DEBUGINFOD_CFLAGS when compiling dwarf.cAlan Modra2-2/+22
Pick up the elfutils/debuginfod.h install location -I flags from a variable set by debuginfod.m4 (via pkg.m4 and pkg-config). * Makefile.am (DEBUGINFOD_CFLAGS): Define. (dwarf.@OBJECT@): New rule.
2021-11-18RISC-V: Add testcases for z[fdq]inxjiawei6-0/+222
Use gpr when the zfinx enable, the testcases contain float instructions that reuse by z[fdq]inx. gas/ChangeLog: * testsuite/gas/riscv/zdinx.d: New test. * testsuite/gas/riscv/zdinx.s: New test. * testsuite/gas/riscv/zfinx.d: New test. * testsuite/gas/riscv/zfinx.s: New test. * testsuite/gas/riscv/zqinx.d: New test. * testsuite/gas/riscv/zqinx.s: New test. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei5-149/+167
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if z*inx enabled and use gpr instead of fpr when z*inx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for z*inx extension. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Added register choice for z*inx. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for z*inx. * riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-11-18RISC-V: Add mininal support for z[fdq]inxjiawei1-0/+12
Minimal support for zfinx, zdinx, zqinx. Like f/d/q, the zqinx imply zdinx and zdinx imply zfinx, where zfinx are not compatible with f/d/q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Added implicit rules for z*inx extensions. (riscv_supported_std_z_ext): Added entries for z*inx. (riscv_parse_check_conflicts): Added conflict check for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-11-18Automatic date update in version.inGDB Administrator1-1/+1
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus17-191/+736
This patch is adding new SVE2 instructions added to support SME extension. The following SVE2 instructions are added by the SME architecture: * PSEL, * REVD, SCLAMP and UCLAMP. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_pred_reg_with_index): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-9-illegal.d: New test. * testsuite/gas/aarch64/sme-9-illegal.l: New test. * testsuite/gas/aarch64/sme-9-illegal.s: New test. * testsuite/gas/aarch64/sme-9.d: New test. * testsuite/gas/aarch64/sme-9.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_PnT_Wm_imm. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): New inserter. * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): New extractor. * aarch64-opc.c (aarch64_print_operand): Printout of OPND_SME_PnT_Wm_imm. * aarch64-opc.h (enum aarch64_field_kind): New bitfields FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. (OP_SVE_QMQ): New qualifier. (struct aarch64_opcode): New instructions PSEL, REVD, SCLAMP and UCLAMP. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus6-1/+72
This patch is adding miscellaneous SME related system registers. gas/ChangeLog: * testsuite/gas/aarch64/sme-sysreg.d: New test. * testsuite/gas/aarch64/sme-sysreg.s: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.d: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.l: New test. * testsuite/gas/aarch64/sme-sysreg-illegal.s: New test. opcodes/ChangeLog: * aarch64-opc.c: New system registers id_aa64smfr0_el1, smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1, smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus17-1522/+1766
This patch is adding new SME mode selection and state access instructions: * Add SMSTART and SMSTOP instructions. * Add SVCR system register. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_sm_za): New parser. (parse_operands): New parser. * testsuite/gas/aarch64/sme-8-illegal.d: New test. * testsuite/gas/aarch64/sme-8-illegal.l: New test. * testsuite/gas/aarch64/sme-8-illegal.s: New test. * testsuite/gas/aarch64/sme-8.d: New test. * testsuite/gas/aarch64/sme-8.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_SM_ZA. (enum aarch64_insn_class): New instruction classes sme_start and sme_stop. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. (aarch64_ins_sme_sm_za): New inserter. * aarch64-dis.c (aarch64_ext_imm): New extractor. (aarch64_ext_pstatefield): New extractor. (aarch64_ext_sme_sm_za): New extractor. * aarch64-opc.c (operand_general_constraint_met_p): New pstatefield value for SME instructions. (aarch64_print_operand): Printout for OPND_SME_SM_ZA. (SR_SME): New register SVCR. * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. (PSTATE_ENCODE_CRM): Encode CRm field. (PSTATE_DECODE_CRM): Decode CRm field. (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate field. * aarch64-tbl.h (struct aarch64_opcode): New SMSTART and SMSTOP instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus26-245/+1417
This patch is adding new loads and stores defined by SME instructions. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_address): New parser. (parse_sme_za_hv_tiles_operand_with_braces): New parser. (parse_sme_za_array): New parser. (output_operand_error_record): Print error details if present. (parse_operands): Support new operands. * testsuite/gas/aarch64/sme-5-illegal.d: New test. * testsuite/gas/aarch64/sme-5-illegal.l: New test. * testsuite/gas/aarch64/sme-5-illegal.s: New test. * testsuite/gas/aarch64/sme-5.d: New test. * testsuite/gas/aarch64/sme-5.s: New test. * testsuite/gas/aarch64/sme-6-illegal.d: New test. * testsuite/gas/aarch64/sme-6-illegal.l: New test. * testsuite/gas/aarch64/sme-6-illegal.s: New test. * testsuite/gas/aarch64/sme-6.d: New test. * testsuite/gas/aarch64/sme-6.s: New test. * testsuite/gas/aarch64/sme-7-illegal.d: New test. * testsuite/gas/aarch64/sme-7-illegal.l: New test. * testsuite/gas/aarch64/sme-7-illegal.s: New test. * testsuite/gas/aarch64/sme-7.d: New test. * testsuite/gas/aarch64/sme-7.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands. (enum aarch64_insn_class): Added sme_ldr and sme_str. (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. (aarch64_ins_sme_za_list): New inserter. (aarch64_ins_sme_za_array): New inserter. (aarch64_ins_sme_addr_ri_u4xvl): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. (aarch64_ext_sme_za_list): New extractor. (aarch64_ext_sme_za_array): New extractor. (aarch64_ext_sme_addr_ri_u4xvl): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. * aarch64-opc.c (operand_general_constraint_met_p): (aarch64_match_operands_constraint): Handle sme_ldr, sme_str and sme_misc. (aarch64_print_operand): New operands supported. * aarch64-tbl.h (OP_SVE_QUU): New qualifier. (OP_SVE_QZU): New qualifier. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus13-140/+539
This patch is adding ZERO (a list of 64-bit element ZA tiles) instruction. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_list_of_64bit_tiles): New parser. (parse_operands): Handle OPND_SME_list_of_64bit_tiles. * testsuite/gas/aarch64/sme-4-illegal.d: New test. * testsuite/gas/aarch64/sme-4-illegal.l: New test. * testsuite/gas/aarch64/sme-4-illegal.s: New test. * testsuite/gas/aarch64/sme-4.d: New test. * testsuite/gas/aarch64/sme-4.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_SME_list_of_64bit_tiles. opcodes/ChangeLog: * aarch64-opc.c (print_sme_za_list): New printing function. (aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles. * aarch64-opc.h (enum aarch64_field_kind): New bitfield FLD_SME_zero_mask. * aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus26-176/+952
This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus17-134/+1423
Patch is adding new SME matrix instructions. Please note additional instructions will be added in following patches. gas/ChangeLog: * config/tc-aarch64.c (parse_sme_zada_operand): New parser. * config/tc-aarch64.c (parse_reg_with_qual): New reg parser. * config/tc-aarch64.c (R_ZA): New egister type. (parse_operands): New parser. * testsuite/gas/aarch64/sme-illegal.d: New test. * testsuite/gas/aarch64/sme-illegal.l: New test. * testsuite/gas/aarch64/sme-illegal.s: New test. * testsuite/gas/aarch64/sme.d: New test. * testsuite/gas/aarch64/sme.s: New test. * testsuite/gas/aarch64/sme-f64.d: New test. * testsuite/gas/aarch64/sme-f64.s: New test. * testsuite/gas/aarch64/sme-i64.d: New test. * testsuite/gas/aarch64/sme-i64.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New operands AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and AARCH64_OPND_SME_Pm. (enum aarch64_insn_class): New instruction class sme_misc. opcodes/ChangeLog: * aarch64-opc.c (aarch64_print_operand): Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands. (verify_constraints): Handle OPND_SME_Pm. * aarch64-opc.h (enum aarch64_field_kind): New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm. * aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set. (OP_SME_ZADA_PN_PM_ZN_D): New qualifier. (OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier. (OP_SME_ZADA_S_PM_PM_S_S): New qualifier. (OP_SME_ZADA_D_PM_PM_D_D): New qualifier. (OP_SME_ZADA_S_PM_PM_H_H): New qualifier. (OP_SME_ZADA_S_PM_PM_B_B): New qualifier. (OP_SME_ZADA_D_PM_PM_H_H): New qualifier. (SME_INSN): New instruction macro. (SME_F64_INSN): New instruction macro. (SME_I64_INSN): New instruction macro. (SME_INSNC): New instruction macro. (struct aarch64_opcode): New SME instructions. aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus5-0/+33
This series of patches (tagged [SME]) add support for the Scalable Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and +sme-i64 to -march command line options. gas/ChangeLog: * NEWS: Updated docs. * config/tc-aarch64.c: New SME command line options. * doc/c-aarch64.texi: Update docs. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_SME): New flag. (AARCH64_FEATURE_SME_F64): New flag. (AARCH64_FEATURE_SME_I64): New flag. opcodes/ChangeLog: * aarch64-tbl.h (SME): New feature object.
2021-11-17Set the default DLL chracteristics to 0 for Cygwin based targets.Jeremy Drake3-3/+23
* emultempl/pep.em (DEFAULT_DLL_CHARACTERISTICS): Set to 0 for Cygwin targets. * emultempl/pep.em (DEFAULT_DLL_CHARACTERISTICS): Likewise.
2021-11-17Fix the linker script parser so that it will recognise the PT_GNU_RELRO ↵Nick Clifton4-3/+24
segment type, and the linker itself so that it will gracefully handle being unable to assign any sections to such a segment. PR 28452 bfd * elf.c (assign_file_positions_for_non_load_sections): Replace assertion with a warning message. ld * ldgram.y: Add support for PT_GNU_RELRO and PT_GNU_PROPERTY. * ldgram.c: Regenerate.
2021-11-17[gdb/build, s390x] Fix build after gdbarch_tdep changesAndreas Arnez1-1/+1
Commit 345bd07cce33 ("gdb: fix gdbarch_tdep ODR violation") changes a declaration in s390-tdep.h from struct gdbarch_tdep { ... }; to struct s390_gdbarch_tdep : gdbarch_tdep { ... }; and now requires that gdbarch_tdep has been declared before. Which is usually the case, except when compiling s390-linux-nat.c, where s390-tdep.h is included before gdbarch.h. Thus the s390x build errors out with the compiler complaining about a missing class name after the colon. Fix this in s390-linux-nat.c, by including gdbarch.h before s390-tdep.h.
2021-11-17Expose the BTI BTYPE more explicitly in the registersLuis Machado2-0/+4
Augment the register description XML to expose the BTI BTYPE field contained in the CPSR register. It will be displayed like so: cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
2021-11-17elfedit: Add --output-abiversion option to update ABIVERSIONH.J. Lu5-3/+83
* NEWS: Mention --output-abiversion. * elfedit.c (input_elf_abiversion): New. (output_elf_abiversion): Likewise. (update_elf_header): Update EI_ABIVERSION. (command_line_switch): Add OPTION_INPUT_ABIVERSION and OPTION_OUTPUT_ABIVERSION. (options): Add --input-abiversion and --output-abiversion. (usage): Likewise. (main): Handle --input-abiversion and --output-abiversion. * doc/binutils.texi: Document --input-abiversion and --output-abiversion. * testsuite/binutils-all/elfedit.exp: Run elfedit-6. * testsuite/binutils-all/elfedit-6.d: New file.
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu24-15/+6615
2021-11-17 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector spec, https://github.com/riscv/riscv-v-spec bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules of v, zve and zvl extensions. (riscv_supported_std_ext): Updated verison of v to 1.0. (riscv_supported_std_z_ext): Added zve and zvl extensions. (riscv_parse_check_conflicts): The zvl extensions need to enable either v or zve extension. (riscv_multi_subset_supports): Check the subset list to know if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported. gas/ * config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V. (enum reg_class): Added RCLASS_VECR and RCLASS_VECM. (validate_riscv_insn): Check whether the rvv operands are valid. (md_begin): Initialize register hash for rvv registers. (macro_build): Added rvv operands when expanding rvv pseudoes. (vector_macro): Expand rvv macros into one or more instructions. (macro): Likewise. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_ip): Parse and encode rvv operands. Besides, The rvv loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march to rv32ifv_zkr. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/march-imply-v.d: New testcase. * testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/vector-insns.d: Likewise. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv. * opcode/riscv.h: Defined rvv immediate encodings and fields. (enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF. (INSN_V_EEW64): Defined. (M_VMSGE, M_VMSGEU): Added for the rvv pseudoes. opcodes/ * riscv-dis.c (print_insn_args): Dump the rvv operands. * riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers. (riscv_vecm_names_numeric): Likewise. (riscv_vsew): Likewise. (riscv_vlmul): Likewise. (riscv_vta): Likewise. (riscv_vma): Likewise. (match_vs1_eq_vs2): Added for rvv Vu operand. (match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand. (riscv_opcodes): Added rvv v1.0 instructions.
2021-11-17gdb/nat/linux-osdata.c: fix build on gcc-12 (string overfow)Sergei Trofimovich1-9/+4
On gcc-12 build fails as: ../../gdbserver/../gdb/nat/linux-osdata.c: In function 'void linux_xfer_osdata_processes(buffer*)': ../../gdbserver/../gdb/nat/linux-osdata.c:330:39: error: '__builtin___sprintf_chk' may write a terminating nul past the end of the destination [-Werror=format-overflow=] 330 | sprintf (core_str, "%d", i); | ^ It's an off-by-one case in an infeasible scenario for negative huge core count. The change switches to std::string for memory handling. Tested by running 'info os processes' and checking CPU cores column.
2021-11-16gdb: Add aliases for read_core_file_mappings callbacksAaron Merey7-37/+46
Add aliases read_core_file_mappings_loop_ftype and read_core_file_mappings_pre_loop_ftype. Intended for use with read_core_file_mappings. Also add build_id parameter to read_core_file_mappings_loop_ftype.
2021-11-16sim: testsuite: add support for $pwd replacementsMike Frysinger19-20/+18
Extend the common test framework to support $pwd replacements in settings. This allows replacing the custom cris @exedir@ with it.
2021-11-16sim: cris: replace @srcdir@ test extension with $srcdir/$subdirMike Frysinger6-11/+9
The common framework supports $srcdir & $subdir replacements already, so replace the custom @srcdir@ logic with those. Since the replace happens in slurp_options that cris already uses, we don't have any logic to port over there. We have to duplicate that into the cris slurp_rv helper though.
2021-11-16sim: cris: drop custom "dynamic" test fieldMike Frysinger7-17/+0
This tag is used to force tests to be built dynamically (i.e. without -static linking). This is because cris-sim.exp in dejagnu turns on static linking in ldflags. The default configs and runtest flags shouldn't load these boards. If these settings are still needed, we should figure out a different way of suppressing the stock settings wholesale. We want these to all pass out of the box with little to no configuration so that they can run in a multitarget build. With dropping "dynamic", it'll be easier to merge the custom cris test logic with the common sim test logic.
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