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2015-12-15Fix invalid left shift of negative valueDominik Vogt11-33/+55
Fix occurrences of left-shifting negative constants in C code. sim/arm/ChangeLog: * thumbemu.c (handle_T2_insn): Fix left shift of negative value. * armemu.c (handle_v6_insn): Likewise. sim/avr/ChangeLog: * interp.c (sign_ext): Fix left shift of negative value. sim/mips/ChangeLog: * micromips.igen (process_isa_mode): Fix left shift of negative value. sim/msp430/ChangeLog: * msp430-sim.c (get_op, put_op): Fix left shift of negative value. sim/v850/ChangeLog: * simops.c (v850_bins): Fix left shift of negative value.
2015-12-15Update the copyright notices in the affected files.Nick Clifton5-12/+12
PR 19339 * elf-vxworks.h: Update copyright notice. * elf-vxworks.c: Update copyright notice. * elf-nacl.h: Update copyright notice. * elf-nacl.c: Update copyright notice.
2015-12-15Add support for the MRS instruction to the AArch64 simulator.Nick Clifton2-9/+53
* aarch64/simulator.c (system_get): New function. Provides read access to the dczid system register. (do_mrs): New function - implements the MRS instruction. (dexSystem): Call do_mrs for the MRS instruction. Halt on unimplemented system instructions.
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato92-1368/+3800
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-12-15Automatic date update in version.inGDB Administrator1-1/+1
2015-12-14Check for readline support in gdb.base/history-duplicates.exp.Sandra Loosemore2-1/+12
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/history-duplicates.exp: Skip if no readline support.
2015-12-14Skip gdb.base/gdbinit-history.exp on remote hosts.Sandra Loosemore2-0/+12
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/gdbinit-history.exp: Skip for remote-host testing.
2015-12-14Skip gdb.base/gdbhistsize-history.exp on remote hosts.Sandra Loosemore2-0/+12
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/gdbhistsize-history.exp: Skip for remote-host testing.
2015-12-14Skip tests that send ctrl-c to GDB if nointerrupts target property is set.Sandra Loosemore17-57/+137
2015-12-14 Sandra Loosemore <sandra@codesourcery.com> gdb/testsuite/ * gdb.base/completion.exp: Skip tests that interrupt GDB with ctrl-C if nointerrupts target property is set. * gdb.base/double-prompt-target-event-error.exp: Likewise. * gdb.base/paginate-after-ctrl-c-running.exp: Likewise. * gdb.base/paginate-bg-execution.exp: Likewise. * gdb.base/paginate-execution-startup.exp: Likewise. * gdb.base/random-signal.exp: Likewise. * gdb.base/range-stepping.exp: Likewise. * gdb.cp/annota2.exp: Likewise. * gdb.cp/annota3.exp: Likewise. * gdb.gdb/selftest.exp: Likewise. * gdb.threads/continue-pending-status.exp: Likewise. * gdb.threads/leader-exit.exp: Likewise. * gdb.threads/manythreads.exp: Likewise. * gdb.threads/pthreads.exp: Likewise. * gdb.threads/schedlock.exp: Likewise. * gdb.threads/sigthread.exp: Likewise.
2015-12-14Target remote mode fork and exec event documentationDon Breazeal4-77/+213
This patch implements documentation updates for target remote mode fork and exec events. A summary of the rationale for the changes made here: * Connecting to a remote target -- explain that the two protocols exist. * Connecting in target remote mode -- explain invoking gdbserver for target remote mode, and move remote-specific text from original "Connecting to a remote target" section. * Connecting in target extended-remote mode -- promote this section from "Using the gdbserver Program | Running gdbserver | Multi-Process Mode for gdbserver". Put it next to the target remote mode section. * Host and target files -- collect paragraphs dealing with how to locate symbol files from original sections "Connecting to a remote target" and "Using the gdbserver program | Connecting to gdbserver". * Steps for connecting to a remote target -- used to be "Using the gdbserver program | Connecting to gdbserver" * Remote connection commands -- used to be the bulk of "Connecting to a remote target". Added "target extended-remote" commands and information. gdb/ChangeLog: * NEWS: Announce fork and exec event support for target remote. gdb/doc/ChangeLog: * gdb.texinfo (Forks): Correct Linux kernel version where fork and exec events are supported, add notes about support of these events in target remote mode. (Connecting): Reorganize and clarify distinctions between target remote, extended-remote, and multiprocess. Reorganize related text from separate sections into new sections. (Server): Note effects of target extended-remote mode. Delete section on Multi-Process Mode for gdbserver. Move some text to "Connecting" node.
2015-12-14Target remote mode fork and exec event supportDon Breazeal6-114/+161
This patch implements support for fork and exec events with target remote mode Linux targets. For such targets with Linux kernels 2.5.46 and later, this enables follow-fork-mode, detach-on-fork and fork and exec catchpoints. The changes required to implement this included: * Don't exit from gdbserver if there are still active inferiors. * Allow changing the active process in remote mode. * Enable fork and exec events in remote mode. * Print "Ending remote debugging" only when disconnecting. * Combine remote_kill and extended_remote_kill into a single function that can handle the multiple inferior case for target remote. Also, the same thing for remote_mourn and extended_remote_mourn. * Enable process-style ptids in target remote. * Remove restriction on multiprocess mode in target remote. gdb/gdbserver/ChangeLog: * server.c (process_serial_event): Don't exit from gdbserver in remote mode if there are still active inferiors. gdb/ChangeLog: * inferior.c (number_of_live_inferiors): New function. (have_live_inferiors): Use number_of_live_inferiors in place of duplicate code. * inferior.h (number_of_live_inferiors): Declare new function. * remote.c (set_general_process): Remove restriction on target remote mode. (remote_query_supported): Likewise. (remote_detach_1): Exit in target remote mode only when there is just one live inferior left. (remote_disconnect): Unpush the target directly instead of calling remote_mourn. (remote_kill): Rewrite function to handle both target remote and extended-remote. Call remote_kill_k. (remote_kill_k): New function. (extended_remote_kill): Delete function. (remote_mourn, extended_remote_mourn): Combine functions into one, remote_mourn, and enable extended functionality for target remote. (remote_pid_to_str): Enable "process" style ptid string for target remote. (remote_supports_multi_process): Remove restriction on target remote mode.
2015-12-14Target remote mode fork and exec test updatesDon Breazeal18-65/+49
This patch updates tests for fork and exec events in target remote mode. In the majority of cases this was a simple matter of removing some code that disabled the test for target remote. In a few cases the test needed to be disabled; in those cases the gdb_protocol was checked instead of using the [is_remote target] etc. In a couple of cases we needed to use clean_restart, since target remote doesn't support the run command, and in one case we had to modify an expect expression to allow for a "multiprocess-style" ptid. Tested with the patch that implemented target remote mode fork and exec event support. gdb/testsuite/ChangeLog: * gdb.base/execl-update-breakpoints.exp (main): Enable for target remote. * gdb.base/foll-exec-mode.exp (main): Disable for target remote. * gdb.base/foll-exec.exp (main): Enable for target remote. * gdb.base/foll-fork.exp (main): Likewise. * gdb.base/foll-vfork.exp (main): Likewise. * gdb.base/multi-forks.exp (main): Likewise, and use clean_restart. (proc continue_to_exit_bp_loc): Use clean_restart. * gdb.base/pie-execl.exp (main): Disable for target remote. * gdb.base/watch-vfork.exp (main): Enable for target remote. * gdb.mi/mi-nsthrexec.exp (main): Likewise. * gdb.threads/execl.exp (main): Likewise. * gdb.threads/fork-child-threads.exp (main): Likewise. * gdb.threads/fork-plus-threads.exp (main): Disable for target remote. * gdb.threads/fork-thread-pending.exp (main): Enable for target remote. * gdb.threads/linux-dp.exp (check_philosopher_stack): Allow pid.tid style ptids, instead of just tid. * gdb.threads/thread-execl.exp (main): Enable for target remote. * gdb.threads/watchpoint-fork.exp (main): Likewise. * gdb.trace/report.exp (use_collected_data): Allow pid.tid style ptids, instead of just tid.
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate ↵Matthew Wahab8-1021/+1088
instructions. ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Scalar Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Hd>, <Hs>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift by immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD scalar shift by immediate group. Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab10-1262/+1344
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch extends instructions in the group Adv.SIMD Shift By Immediate to support FP16, making this support available when +simd+fp16 is enabled. The new instructions legal make some uses of the 4h vector type that had been invalid. This patch adjusts a test that checks for these uses. The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, #<imm> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace tests for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_VSHIFT_H): New. (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf and fcvtzu to the Adv.SIMD shift by immediate group. Change-Id: I3480f63883d54db46562573185da6982f2365ee8
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab8-1101/+1223
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Scalar Pairwise, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar Pairwise instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_PAIR_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp, fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group. Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab7-8/+33
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type, 2H. This patch adds support for this vector type to binutils. The patch adds a new operand qualifier to the enum aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation used by aarch64-dis.c:get_vreg_qualifier_from_value, called when decoding an instruction. Since the new vector type is only used in FP16 scalar pairwise instructions which do not require the function, this patch adjusts the function to ignore the new qualifier. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to take into account new vector type 2H. (vectype_to_qualifier): Likewise. include/opcode/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (enum aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_2H. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.coM> * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment and adjust calculation to ignore qualifier for type 2H. * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
2015-12-14[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.Matthew Wahab2-6/+35
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type. This patch reworks code in the assembler to allow the addition of the new type. The new vector type requires the addtion of a new operand qualifier to the enum aarch64_opnd_qualifier which is defined include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_. The correctness of the GAS utility function tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and ordering of this group. In particular, it makes assumptions about the positions of the members of the group that are not true if a qualifier for type 2H is added before the qualifier for 4H. This patch reworks the function to weaken its assumptions, making it calculate positions in the group from the type (B, H, S, D, Q) and register width. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand qualifier from per-type base and offet. Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab8-1535/+1577
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds an FP16 instruction to the group Adv.SIMD Modified Immediate, making it available when +simd+fp16 is enabled. The instruction added is: FMOV. The form of this instructions is <OP> <Hd>, #<imm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SIMD_IMM_H): New. (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD modified immediate group. Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab10-1664/+1776
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Adv.SIMD Across Lanes, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV. The general form for these instructions is <OP> <Hd>, <V>.<T> where T is 4h or 8h. The new instructions valid make uses of the 8H and 4H that were previously illegal. The patch adjusts a test for illegal uses of vector types to take this into account. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes instructions. * gas/aarch64/illegal.d: Update expected output. * gas/aarch64/illegal.s: Replace test for illegal use of 'h' specifier. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_XLANES_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv, fminnmv, fminv to the Adv.SIMD across lanes group. Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab8-1215/+1312
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <Hd>, <Hs>, <V>.h[<idx>] gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the scalar indexed element group. Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab8-1580/+1700
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Indexed Element, making them available when +simd+fp16 is enabled. The instructions added are: FMLA, FMLS, FMUL and FMULX. The general form for these instructions is <OP> <V>.<T>, <V>.<T>, <V>.h[<idx>] where T is 4h or 8h gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_ELEMENT_FP_H): New. (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and fmulx to the vector indexed element group. Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab8-1238/+1650
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX. The general form for these instructions is <OP> <Hd>, <Hs> or <OP> <Hd>, <Hs>, #0.0 Tested the series for aarch64-none-linux-gnu with cross-compiled check-binutils and check-gas. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_SISD_FCMP_H_0): new. (QL_S_2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe, frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu, fcvtzu and frsqrte to the scalar two register misc. group. Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab9-1776/+2377
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Two Register Misc, making them available when +simd+fp16 is enabled. The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS, FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU, SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc. instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V2SAMEH): New. (aarch64_opcode_table): Add fp16 versions of frintn, frintm, fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp, frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte and fsqrt to the vector register misc. group. Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab8-1081/+1268
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Scalar Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FRECPS and FRSQRTS. The general form for these instructions is <OP> <Hd>, <Hs>, <Hm> gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same instructions. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt to the scalar three same group. Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab8-1363/+1907
ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch adds FP16 instructions to the group Vector Three Register Same, making them available when +simd+fp16 is enabled. The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA, FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE, FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS. The general form for these instructions is <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T> where T is 4h or 8h. gas/testsuite/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/advsimd-fp16.d: New. * gas/aarch64/advsimd-fp16.s: New. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-tbl.h (QL_V3SAMEH): New. (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd, fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts, fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd, fcmgt, facgt and fminp to the vector three same group. Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
2015-12-14[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab2-0/+8
ARMv8.2 adds 16-bit floating point operations as an optional extension to floating point and Adv.SIMD support. This patch set adds the 16-bit Adv.SIMD vector and scalar instructions to binutils, making them available when both +simd and +fp16 architecture extensions are enabled. The series also adds support for a new vector type, 2H, used by the FP16 scalar pairwise instructions. The patches in this series: - Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding routines. - Add FP16 instructions in the group Vector Three Register Same. - Add FP16 instructions in the group Scalar Three Register Same. - Add FP16 instructions in the group Vector Two Register Misc. - Add FP16 instructions in the group Scalar Two Register Misc. - Add FP16 instructions in the group Vector Indexed Element. - Add FP16 instructions in the group Scalar Indexed Element. - Add FP16 instructions in the group Adv.SIMD Across Lanes. - Add FP16 instructions in the group Adv.SIMD Modified Immediate. - Rework some code for handling vector types to weaken its assumptions about available vector-types. - Add support for the 2H vector type. - Add FP16 instructions in the group Adv.SIMD Scalar Pairwise. - Add FP16 instructions in the group Adv.SIMD Shift By Immediate. - Add a FP16 instructions in the group Adv.SIMD Scalar Shift By Immediate. This patch adds the feature macro SIMD_F16 to the AArch64 encoding/decoding routines. It is used to decide when the new instructions are available to the assembler and is true when both +simd and +fp16 are selected. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-tbl.h (aarch64_feature_simd_f16): New. (SIMD_F16): New. Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f
2015-12-14[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab2-6/+15
A mistake with rebasing the ARMv8.2 AT instruction patch left this part + /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */ + if ((reg->value == CPENS (0, C7, C9, 0) + || reg->value == CPENS (0, C7, C9, 1)) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) + return FALSE; in aarch64_pstatefield_supported_p rather than in aarch64_sys_ins_reg_supported_p, where it was supposed to be. The patch adding support for id_aa64mmfr2_el1, also had the effect of removing a conditional branch in aarch64_sys_reg_supported_p. The effect of both of these is to suppress an error if some ARMv8.2 system registers are used with the wrong -march settings. This patch fixes these mistakes. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly removed statement. (aarch64_pstatefield_supported_p): Move feature checks for AT registers .. (aarch64_sys_ins_reg_supported_p): .. to here. Change-Id: I48783d118eaaf0f3312e8b08a8340ef7af4e36a4
2015-12-14gdb: Use TYPE_LENGTH macroAndrew Burgess3-8/+16
Fixes a couple of places where we access the length field of the type structure directly, rather than using the TYPE_LENGTH macro. gdb/ChangeLog: * i386-tdep.c (i386_mpx_info_bounds): Use TYPE_LENGTH. (i386_mpx_set_bounds): Likewise. * solib-darwin.c (darwin_load_image_infos): Likewise. (darwin_solib_read_all_image_info_addr): Likewise.
2015-12-14gas: free allocated symbol name in .cfi_label handlingJan Beulich2-0/+5
I've just noticed this further oversights of the original commit.
2015-12-14nm: basic COFF symbol type support for SysV-style symbol table dumpingJan Beulich2-4/+63
2015-12-14Automatic date update in version.inGDB Administrator1-1/+1
2015-12-13Remove const from return type of get_output_view.Cary Coutant3-8/+15
gold/ * object.h (Object::get_output_view): remove const from return type. (Object::do_get_output_view): Likewise. (Sized_relobj_file::do_get_output_view): Likewise. * reloc.cc (Sized_relobj_file::do_get_output_view): Likewise.
2015-12-13Automatic date update in version.inGDB Administrator1-1/+1
2015-12-12Fix SH gas testsuite invalid assembly exposed by ec9ab52cAlan Modra3-2/+7
* gas/sh/tlsd.s: Use .tdata not .tbss. * gas/sh/tlsnopic.s: Likewise.
2015-12-12Enable 2 operand form of powerpc mfcr with -manyAlan Modra2-3/+8
This is a workaround for a gcc bug. PR 19359 * ppc-opc.c (insert_fxm): Remove "ignored" from error message. (powerpc_opcodes): Remove single-operand mfcr.
2015-12-12Automatic date update in version.inGDB Administrator1-1/+1
2015-12-11gdb: Extend help text for 'list' command.Andrew Burgess2-2/+11
Reference the 'listsize' setting in the help text for the 'list' command to help users find this setting. gdb/ChangeLog: * cli/cli-cmds.c (_initialize_cli_cmds): Extend help text for 'list' command.
2015-12-11gdb: Add an error when 'list -' reaches the start of a file.Andrew Burgess4-4/+33
When a a user uses 'list +' to list forward through a source file they eventually reach the end of the source file. Subsequent uses of 'list +' result in an error message like this, that let the user know they are at the end of the source file: Line number XXX out of range; FILENAME has YYY lines. Compare this to the current behaviour of 'list -' which lists backwards through a source file. When the user reaches the beginning of the source file, subsequent uses of 'list -' result in the command silently returning. This can be confusing if the previous uses of 'list -' have scrolled off the users display, the user receives no reminder that the have already seen the start of the file. After this commit a use of 'list -' when the user has already seen the start of a file will receive the following error: Already at the start of FILENAME. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Add an error when trying to use '-' to scan read off the start of the source file. gdb/testsuite/ChangeLog: * gdb.base/list.exp (test_list_forward): Add end of file error test. (test_repeat_list_command): Add end of file error test. (test_list_backwards): Add beginning of file error test.
2015-12-11gdb: 'list' command, tweak handling of +/- arguments.Andrew Burgess4-3/+32
There is an inconsistency with the handling of the special +/- arguments to the list command. For the very first time that list is used (after the inferior has changed locations) then only the first character of the argument string is checked, so 'list +BLAH' will operate as 'list +' and 'list -----FOO' will operate as 'list -'. This compares to each subsequent use of list, where the whole argument string is checked, so 'list +BLAH' will try to list lines of code around the function '+BLAH'. This commit unifies the behaviour so that the whole argument string is checked, in order to list the next 10, or previous 10 lines from a file only 'list +' and 'list -' are now valid. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Check that the argument string is a single character, either '+' or '-'. gdb/testsuite/ChangeLog: * gdb.base/list.exp (test_list_invalid_args): New function, defined, and called.
2015-12-11gdb: Make test names unique in list.exp.Andrew Burgess2-2/+10
gdb/testsuite/ChangeLog: * gdb.base/list.exp (test_list): Make test names unique.
2015-12-11gdb: Small code restructure for list_command.Andrew Burgess2-17/+16
Move handling of special +/- arguments to the list_command function inside a single if block, this helps group all related functionality together. There should be no user visible changes after this commit. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Move all handling of +/- arguments into a single if block.
2015-12-11gdb: Use NULL instead of 0 for pointer comparison.Andrew Burgess2-2/+7
Small code cleanup, use NULL instead of 0 when checking pointers. There should be no user visible changes after this commit. gdb/ChangeLog: * cli/cli-cmds.c (list_command): Use NULL instead of 0 when checking pointers.
2015-12-11gdb: Make lines_to_list variable static.Andrew Burgess2-1/+5
Small clean up, make variable static. gdb/ChangeLog: * source.c (lines_to_list): Make static.
2015-12-11Pass relocations to Target::do_calls_non_split.Cary Coutant7-4/+32
gold/ * target.h (Target::calls_non_split): Add prelocs, reloc_count parameters. (Target::do_calls_non_split): Likewise. * target.cc (Target::do_calls_non_split): Likewise. * reloc.cc (Sized_relobj_file::split_stack_adjust_reltype): Adjust call to Target::calls_non_split. * i386.cc (Target_i386::do_calls_non_split): Add prelocs, reloc_count parameters. * powerpc.cc (Target_powerpc::do_calls_non_split): Likewise. * x86_64.cc (Target_x86_64::do_calls_non_split): Likewise.
2015-12-11Make output views accessible to Target during do_relocate().Cary Coutant4-1/+87
gold/ * object.cc (Sized_relobj_file::Sized_relobj_file): Initialize output_views_. * object.h (Object::get_output_view): New function. (Object::do_get_output_view): New function. (Sized_relobj_file::do_get_output_view): New function. (Sized_relobj_file::output_views_): New data member. * reloc.cc: (Sized_relobj_file::do_relocate): Store pointer to output views in class object. (Sized_relobj_file::do_get_output_view): New function.
2015-12-11Remove gdb.base/coremaker2.cYao Qi2-75/+4
I happen to find that coremaker2.c isn't used in the testsuite (if I don't miss anything). I don't believe it until I see this ChangeLog entry, 1999-11-18 Fred Fish <fnf@cygnus.com> * gdb.base/coremaker2.c: Add sample program for generating cores that is more self contained than coremaker.c. Eventually I'll add more code to this and tie it into the testsuite. looks Fred didn't "tie it into testsuite" later. gdb/testsuite: 2015-12-11 Yao Qi <yao.qi@linaro.org> * gdb.base/coremaker2.c: Remove.
2015-12-11Understand arm breakpoints in aarch64_breakpoint_atYao Qi2-6/+16
AArch64 GDBserver can debug ARM program, and it should recognize various arm breakpoint instructions. This patch should be included in 17b1509a. gdb/gdbserver: 2015-12-11 Yao Qi <yao.qi@linaro.org> * linux-aarch64-low.c (aarch64_breakpoint_at): Call arm_breakpoint_at if the process is 32-bit.
2015-12-11Use arm_eabi_breakpoint on aarch32Yao Qi2-3/+8
Nowdays, GDBserver chooses arm breakpoint instructions by checking macro __ARM_EABI__. When aarch64 GDBserver debugs arm program, arm_eabi_breakpoint is still needed, but __ARM_EABI__ isn't defined in aarch64 compiler. This causes GDBserver chooses the wrong breakpoint instruction for arm program. This patch fixes it. gdb/gdbserver: 2015-12-11 Yao Qi <yao.qi@linaro.org> * linux-aarch32-low.c [__aarch64__]: Use arm_abi_breakpoint arm breakpoint.
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab13-28/+135
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds the instruction to binutils as a HINT alias that takes an operand. A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the operand to PSB. A parser for the operand type is added to the assembler and a printer to the disassembler. The operand name "csync" is added to the list of HINT options with HINT number #17. Encoding and decoding of the operand is handled by the ins_hint/ext_hint functions added in the preceding patches. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_hint_opt_hsh): New. (parse_barrier_psb): New. (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB. (md_begin): Set up aarch64_hint_opt_hsh. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: Enable the statistical profiling extension. Update the expected output. * gas/aarch64/system-2.s: Add tests for PSB CSYNC. * gas/aarch64/system.d: Update the expected output. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): Add "csync". (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_feature_stat_profile): New. (STAT_PROFILE): New. (aarch64_opcode_table): Add "psb". (AARCH64_OPERANDS): Add "BARRIER_PSB". Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab10-4/+75
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds support for aliases of HINT which take an operand, adding a table to store operand names and their matching hint number as well as encoding and decoding functions for such operands. Parsing and printing the operands are deferred to any support added for aliases with such operands. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_hint_options): Declare. (aarch64_opnd_info): Add field hint_option. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm.c (aarch64_ins_hint): New. * aarch64-asm.h (aarch64_ins_hint): Declare. * aarch64-dis.c (aarch64_ext_hint): New. * aarch64-dis.h (aarch64_ext_hint): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): New. * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
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