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2023-12-28gold: Handle R_X86_64_CODE_4_GOTPCRELXH.J. Lu8-10/+54
Handle R_X86_64_CODE_4_GOTPCRELX and convert mov name@GOTPCREL(%rip), %r31 to lea name@GOTPCREL(%rip), %r31 if the instruction is encoded with the REX2 prefix when possible. elfcpp/ * x86_64.h (R_X86_64_CODE_4_GOTPCRELX): New. gold/ * x86_64.cc (Target_x86_64::can_convert_mov_to_lea): Handle R_X86_64_CODE_4_GOTPCRELX. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::possible_function_pointer_reloc): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. * testsuite/x86_64_mov_to_lea1.s: Add a test for R_X86_64_CODE_4_GOTPCRELX. * testsuite/x86_64_mov_to_lea2.s: Likewise. * testsuite/x86_64_mov_to_lea3.s: Likewise. * testsuite/x86_64_mov_to_lea4.s: Likewise. * testsuite/x86_64_mov_to_lea5.s: Likewise. * testsuite/x86_64_mov_to_lea.sh: Updated.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu19-27/+382
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-12-28gas: Mention initial support for Intel APX in NEWSH.J. Lu1-0/+2
2023-12-28x86: Add NT_X86_SHSTK noteSchimpe, Christina2-0/+5
Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to support Intel SHSTK in Linux kernel. For now only userspace shadow stack and kernel IBT are supported by the linux kernel. This note should be used instead of NT_X86_CET introduced in the commit "x86: Add NT_X86_CET note", as it is outdated and only used by old binutils versions.
2023-12-28Support APX JMPABS for disassemblerHu, Lin17-2/+122
gas/ChangeLog: * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto. opcodes/ChangeLog: * i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs. (print_insn): Add #UD exception for jmpabs. (dis386): Modify a1 unit for support jmpabs. * i386-mnem.h: Regenerated. * i386-opc.tbl: New insns. * i386-tbl.h: Regenerated.
2023-12-28Support APX NDD optimized encoding.Hu, Lin14-0/+362
This patch aims to optimize: add %r16, %r15, %r15 -> add %r16, %r15 gas/ChangeLog: * config/tc-i386.c (check_Rex_required): New function. (can_convert_NDD_to_legacy): Ditto. (match_template): If we can optimzie APX NDD insns, so rematch template. * testsuite/gas/i386/x86-64.exp: Add test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto.
2023-12-28Support APX pushp/poppCui, Lili12-1062/+1154
gas/ChangeLog: * config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires rex2.w == 1." * testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto. opcodes/ChangeLog: * i386-dis.c (putop): print pushp and popp. * i386-opc.tbl: Added new insns. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-tbl.h: Regenerated.
2023-12-28Support APX Push2/Pop2Mo, Zewei19-1960/+2291
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28Support APX NDDkonglin114-430/+2102
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28Add tests for APX GPR32 with extend evex prefixCui, Lili12-0/+1498
gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't support gpr32. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add new test. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili11-4196/+4847
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili2-0/+292
opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili26-11903/+12808
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-28sim: pru: Fix emulation of carry bitDimitar Dimitrov2-4/+424
The PRU architecture documentation [1] was used for the initial GNU simulator implementation. But recently [2] TI confirmed the carry behaviour was wrongly documented. In reality, the PRU carry behaves like the carry in ARM processors. This patch fixes simulator to align with latest recommendations from TI. The new carry.s test was also validated to pass on real hardware - a BeaglePlay board [3]. That test is a bit long because TI still has not released official updates for the PRU documents. And I wanted to ensure simulator handles all edge cases exactly as the real hardware does. [1] https://www.ti.com/lit/pdf/spruij2 [2] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1244359/sk-am64b-am64x-pru-assembler-how-works-this-bloody-carry [3] https://www.beagleboard.org/boards/beagleplay Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2023-12-28RISC-V: PR31179, The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objectsNelson Chu8-15/+89
* Problematic fix commit, 2029e13917d53d2289d3ebb390c4f40bd2112d21 RISC-V: Clarify the behaviors of SET/ADD/SUB relocations * Bugzilla, https://sourceware.org/bugzilla/show_bug.cgi?id=31179#c5 The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it non-zero by accident in assembler before. This causes troubles by applying the above commit, since the calculation is changed to support .reloc *SUB* relocations with non-zero addend. We encourage people to rebuild their stuff to get the non-zero addend of SUB_ULEB128, but that might need some times, so report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use, it may acceptable that stop supproting them until people rebuld their stuff, maybe half-year or a year later. Or maybe we should teach people that don't write the .reloc R_RISCV_SUB* with non-zero constant, and then report warnings/errors in assembler. bfd/ * elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of R_RISCV_SUB_ULEB128. (riscv_elf_relocate_section): Report warnings to inform people need to rebuild their stuff if --check-uleb128 is enabled. So that can get the right non-zero addend of R_RISCV_SUB_ULEB128. * elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128. ld/ * NEWS: Updated. * emultempl/riscvelf.em: Added linker risc-v target options, --[no-]check-uleb128, to enable/disable checking if the addend of uleb128 is non-zero or not. So that people will know they need to rebuild the objects with binutils 2.42 and up, to get the right zero addend of SUB_ULEB128 relocation, or they may get troubles if using .reloc. * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
2023-12-28Automatic date update in version.inGDB Administrator1-1/+1
2023-12-27asan: buffer overflow in loongarch_elf_rtype_to_howtoAlan Modra1-21/+11
Seen when running ld-loongarch-elf/tlsdesc-dso test. elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for type 'loongarch_reloc_howto_type [124]' So either the loongarch_howto_table needs three more LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure it's worth wasting a little more space to get faster lookup. * elfxx-loongarch.c (loongarch_howto_table): Add LOONGARCH_EMPTY_HOWTO entries for 121..123. (loongarch_elf_rtype_to_howto): Don't support slow lookup. Assert exact table size and r_type indexing. Omit return cast. (loongarch_reloc_name_lookup): Omit assertion and return cast. (loongarch_reloc_type_lookup): Likewise.
2023-12-27PR31191, objcopy leaves temporary filesAlan Modra1-23/+24
Fix the ENOTDIR rmdir too. PR 31191 * objcopy.c (copy_archive): Localise uses of "l". Remove const from name_list.name. Unlink output element on bfd_close error, and NULL list->name to indicate file is removed. Adjust cleanup to prevent rmdir on non-existent file.
2023-12-26sim: common: pull in newlib extensions for Linux compatibilityMike Frysinger2-1/+122
Since newlib allows people to opt-in to extra errno names, pull them into our table too. The values don't conflict with each other -- the newlib names & values are distinct from newlib's Linux compatibility.
2023-12-27Automatic date update in version.inGDB Administrator1-1/+1
2023-12-26Automatic date update in version.inGDB Administrator1-1/+1
2023-12-25binutils: SECURITY: use https URIMike Frysinger1-2/+2
2023-12-25LoongArch: Add testsuit for DESC and tls transition and tls relaxation.Lulu Cai23-0/+472
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang13-543/+795
The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.
2023-12-25LoongArch: Add tls transition support.Lulu Cai2-1/+221
Transitions between DESC->IE/LE and IE->LE are supported now. 1. For DESC -> LE: pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 2. For DESC -> IE: pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 3. For IE -> LE: pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) add.d $a0,$a0,$tp 4. When a tls variable is accessed using both DESC and IE, DESC transitions to IE and uses the same GOT entry as IE.
2023-12-25LoongArch: Add support for TLSDESC in ld.Lulu Cai1-22/+146
1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic relocation, which relocation is placed at .rela.dyn. TLSDESC always allocates two GOT slots and one dynamic relocation space to TLSDESC. 2. When using multiple ways to access the same TLS variable, a maximum of 5 GOT slots are used. For example, using GD, TLSDESC, and IE to access the same TLS variable, GD always uses the first two of the five GOT, TLSDESC uses the third and fourth, and IE uses the last.
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai7-4/+349
The normal DESC instruction sequence is: pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL add.d $a0,$a0,$tp
2023-12-25Automatic date update in version.inGDB Administrator1-1/+1
2023-12-25Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">Alan Modra1-14/+16
This fixes the buffer overflow added in commit 22b78fad28, and a few other problems. * loongarch-coder.c (loongarch_split_args_by_comma): Don't overflow buffer when args == "". Don't remove unbalanced quotes. Don't trim last arg if max number of args exceeded.
2023-12-24gdb: make value::allocate_register_lazy store id of next non-inline frameSimon Marchi4-25/+21
Some spots loop on the frame chain to find the first next non-inline frame, and pass that as the "next frame" to value::allocate_register_lazy / value::allocate_register. This is necessary if the value is used in the process of computing the id of "this frame". If the frame next to "this frame" is inlined into "this frame", then you that next frame won't have a computed id yet. You have to go past that to find the next non-inline frame, which will have a computed id. In other cases, it's fine to store the id of an inline frame as the "next frame id" in a register struct value. When trying to unwind a register from it, it will just call inline_frame_prev_register, which will forward the request to the next next frame, until we hit the next physical frame. I think it would make things simpler to just never store the id of an inline frame as the next frame id of register struct values, and go with the first next non-inline frame directly. This way, we don't have to wonder which code paths have to skip inline frames when creating register values and which don't. So, change value::allocate_register_lazy to do that work, and remove the loops for the callers that did it. Change-Id: Ic88115dac49dc14e3053c95f92050062b24b7310
2023-12-24gdb: remove VALUE_REGNUM, add value::regnumSimon Marchi7-36/+26
Remove VALUE_REGNUM, replace it with a method on struct value. Set `m_location.reg.regnum` directly from value::allocate_register_lazy, which is fine because allocate_register_lazy is a static creation function for struct value. Change-Id: Id632502357da971617d9dce1e2eab9b56dbcf52d
2023-12-24gdb: remove VALUE_NEXT_FRAME_ID, add value::next_frame_idSimon Marchi4-36/+21
Remove VALUE_NEXT_FRAME_ID, replace it with a method on struct value. Set `m_location.reg.next_frame_id` directly from value::allocate_register_lazy, which is fine because allocate_register_lazy is a static creation function for struct value. Change-Id: Ic9f0f239c166a88dccfee836f9f51871e67548e6
2023-12-24gdb: implement address_from_register using value_from_registerSimon Marchi1-37/+4
As explained in the comment removed by the previous commit "gdb: pass non-nullptr frame to gdbarch_value_from_register in address_from_register", address_from_register copies some implementation bits from value_from_register: /* This routine may be called during early unwinding, at a time where the ID of FRAME is not yet known. Calling value_from_register would therefore abort in get_frame_id. However, since we only need a temporary value that is never used as lvalue, we actually do not really need to set its VALUE_NEXT_FRAME_ID. Therefore, we re-implement the core of value_from_register, but use the null_frame_id. */ This is no longer relevant, since we now create a value with a valid next frame id, so change address_from_register to use value_from_register. Change-Id: I189bd96f28735ed9f47750ffd73764c459ec6f43
2023-12-24gdb: remove read_frame_register_value's frame parameterSimon Marchi2-13/+13
By now, all register struct values should have a valid next frame id (assuming they are created using value::allocate_register or value::allocate_register_lazy), so there should be no need to pass a frame alongside the value to read_frame_register_value. Remove the frame parameter and adjust read_frame_register_value accordingly. While at it, make read_frame_register_value static, it's only used in findvar.c. Change-Id: I118959ef8c628499297c67810916e8ba9934bfac
2023-12-24gdb: add type parameter to value::allocate_register and add ↵Simon Marchi4-35/+37
value::allocate_register_lazy Some places that create register struct values don't use register_type to obtain the value type. This prevents them from using the current version of value::allocate_register. One spot (value_of_register_lazy) also creates a lazy register value. Add a value::allocate_register_lazy method. Add some type parameters to value::allocate_register and value::allocate_register_lazy, to let the caller specify the type to use for the value. The parameters default to nullptr, in which case we use register_type to obtain the type. Change-Id: I640ec0a5a0f4a55eba12d515dbfd25933229f8ec
2023-12-24gdb: pass non-nullptr frame to gdbarch_value_from_register in ↵Simon Marchi2-20/+9
address_from_register address_from_register used to pass null_frame_id to gdbarch_value_from_register as "this frame"'s id, because it's possible for it to be called during unwind, when "this frame"'s id is not yet known. This create an oddity where those register struct values are created without a valid next frame id. I would much prefer for things to be consistent and have all register struct values to have a valid next frame id. Since gdbarch_value_from_register takes a frame_info_ptr now, rather than a frame_id, we can pass down "this frame", even if it doesn't have a valid id. gdbarch_value_from_register implementations can obtain the next frame from it. However, it's possible for the "this frame"'s next frame to be an inline frame, inlined in "this frame", in which case that next frame's id is also not known. So, loop until we get to the next non-inline frame (which is actually the frame where registers for "this frame" are unwound from). This is the same thing that we do in value_of_register_lazy, for the same reason. A later patch will factor out this "while next frame is inline" loop to apply it to all register struct values, so this is somewhat temporary. Change-Id: If487c82620cc5a4a4ea5807f0a0bad80ab984078
2023-12-24gdb: pass frame_info_ptr to gdbarch_value_from_registerSimon Marchi7-38/+33
Pass a frame_info_ptr rather than a frame_id. This avoids having to do a frame lookup on the callee side, when we can just pass the frame down directly. I think this fixes a bug in rs6000-tdep.c where the id of the wrong frame was set to `VALUE_NEXT_FRAME_ID (v)`. Change-Id: I77039bc87ea8fc5262f16d0e1446515efa21c565
2023-12-24gdb: don't set frame id after calling cooked_read_valueSimon Marchi1-1/+0
I don't think that setting the next frame id is needed there, all code paths in cooked_read_value do set it properly, AFAIK. Change-Id: Idb9d9e6f89c2c95c5ebfeec2a63fde89ed84cf3d
2023-12-24sim: cris: rvdummy: delete unused variableMike Frysinger1-1/+0
2023-12-24sim: cgen: mark cgen_rtx_error noreturnMike Frysinger1-1/+1
Since this function never returns, mark it as such to fix some unused variable warnings in error code paths. For example, cris triggers: sim/cris/semcrisv10f-switch.c:3558:11: error: variable 'tmp_newval' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized] Even though it has an "else" path that calls this error function.
2023-12-24sim: cgen: regenerate decode tablesMike Frysinger9-5827/+5827
Integrate some changes from upstream cgen that tightened up the generated output. Shouldn't be any functional changes here.
2023-12-24sim: sh: refine pwsb & pwad nopsMike Frysinger1-0/+2
Since these insns don't do anything and are effectively ignored, return early to avoid doing any common processing at the end as that requires initializing variables like "res" with something.
2023-12-24sim: sh: fix plds Dz,MACL implementationMike Frysinger1-1/+1
The plds Dz,MACL insn stores the Dz bit into MACL. The current code was storing the "res" variable into Dz and then into MACL, but not setting "res" to anything. Delete that logic and make it match the existing plds Dz,MACH insn.
2023-12-24Automatic date update in version.inGDB Administrator1-1/+1
2023-12-23sim: warnings: rework individual flag disable into dedicated varsMike Frysinger4-51/+157
The -Wshadow=local is too new for some compilers, so move it to a var that we test at configure time.
2023-12-22gprofng: fix build problems on linux-muslVladimir Mezentsev11-25/+41
ino64_t, off64_t, fpos64_t, stat64, __u64 are not defined on linux-musl. Fixed by declaring these types for linux-musl. 2023-12-21 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> PR gprofng/30779 PR gprofng/29593 * common/gp-defs.h: Define ino64_t, off64_t, fpos64_t for linux-musl. * libcollector/unwind.c: Define __u64 for linux-musl. * src/util.h: Define dbe_stat_t. * src/ClassFile.cc: Use dbe_stat_t instead of "struct stat64". * src/Dbe.cc: Likewise. * src/DbeFile.cc: Likewise. * src/DbeFile.h: Likewise. * src/DbeSession.cc: Likewise. * src/Experiment.cc: Likewise. * src/checks.cc: Likewise. * src/util.cc: Likewise.
2023-12-22sim: sh: fix -Wshadow=local warningsMike Frysinger1-2/+2
Rename the var to avoid shadowing & clobbering the higher context.
2023-12-22sim: riscv: fix -Wshadow=local warningsMike Frysinger1-6/+4
Inline the one usage of sd in these macros to avoid possible shadowing.
2023-12-22sim: ppc: fix -Wshadow=local warningsMike Frysinger1-3/+3
Use a local name in the macro to avoid shadowing wherever it's used.
2023-12-22sim: mips: fix -Wshadow=local warningsMike Frysinger1-5/+2
Delete redundant decls when the existing scope has the same var and type available for use.
generated by cgit v1.1 at 2024-11-24 21:24:37 +0000