Age | Commit message (Collapse) | Author | Files | Lines |
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DWARF2_FRAME_REG_SAVED_VAL_OFFSET and
DWARF2_FRAME_REG_SAVED_VAL_EXP.
* dwarf2-frame.c (execute_cfa_program): Handle val_offset,
val_offset_sf and val_expression.
(dwarf2_frame_prev_register): Handle the new reg rules.
(dwarf2_frame_this_id): Use pc instead of function entry point.
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(dwarf2_frame_sniffer): Use it.
(decode_frame_entry_1): Set it according to augmentation "S".
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calling check_multiply_halfregs ().
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* m2-typeprint.c (m2_record_fields): Move variable declarations
to the begining of the block.
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* elf.c (assign_file_positions_for_load_sections): Retrieve
maxpagesize from m->p_align if it is valid. Set p_vaddr,
p_paddr and p_align earlier. Revert 2006-05-19 change to p_align.
(copy_elf_program_header): Copy p_align. Set p_align_valid.
include/elf/
* internal.h (elf_segment_map): Add p_align and p_align_valid.
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* elf64-x86-64.c (ELF_MINPAGESIZE): Changed to 0x1000.
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* elf64-x86-64.c (ELF_MINPAGESIZE): Set to 0x100000.
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2006-05-25 H.J. Lu <hongjiu.lu@intel.com>
* elf64-x86-64.c (ELF_MAXPAGESIZE): Updated to 0x200000.
ld/
2006-05-25 H.J. Lu <hongjiu.lu@intel.com>
* emulparams/elf_x86_64.sh (MAXPAGESIZE): Updated to 0x200000.
ld/testsuite/
2006-05-25 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/tlsbin.dd: Updated for 2MB maximum page size.
* ld-x86-64/tlsbin.rd: Likewise.
* ld-x86-64/tlsbin.sd: Likewise.
* ld-x86-64/tlsbin.td: Likewise.
* ld-x86-64/tlsbindesc.dd: Likewise.
* ld-x86-64/tlsbindesc.rd: Likewise.
* ld-x86-64/tlsbindesc.sd: Likewise.
* ld-x86-64/tlsbindesc.td: Likewise.
* ld-x86-64/tlsdesc.dd: Likewise.
* ld-x86-64/tlsdesc.pd: Likewise.
* ld-x86-64/tlsdesc.rd: Likewise.
* ld-x86-64/tlsdesc.sd: Likewise.
* ld-x86-64/tlsdesc.td: Likewise.
* ld-x86-64/tlsgdesc.dd: Likewise.
* ld-x86-64/tlspic.dd: Likewise.
* ld-x86-64/tlspic.rd: Likewise.
* ld-x86-64/tlspic.sd: Likewise.
* ld-x86-64/tlspic.td: Likewise.
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(ignore_section_sym): New function.
(elf_map_symbols): Use ignore_section_sym to discard some syms.
(_bfd_elf_symbol_from_bfd_symbol): Ensure section belongs to
bfd before using elf_section_syms.
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* config.bfd: (sh-*-linux*): Treat as 64bit target.
(sh*l*-*-netbsdelf*): Likewise.
(sh-*-netbsdelf*): Likewise.
(shl*-*-elf*): Likewise.
(sh[1234]l*-*-elf*): Likewise.
(sh3el*-*-elf*): Likewise.
(shl*-*-kaos*): Likewise.
(sh-*-elf*): Likewise.
(sh[1234]*-elf*): Likewise.
(sh-*-rtems*): Likewise.
(sh-*-kaos*): Likewise.
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* m68k.h (mcf_mask): Define.
opcodes/
* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
and fmovem entries. Put register list entries before immediate
mask entries. Use "l" rather than "L" in the fmovem entries.
* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
out from INFO.
(m68k_scan_mask): New function, split out from...
(print_insn_m68k): ...here. If no architecture has been set,
first try printing an m680x0 instruction, then try a Coldfire one.
gas/testsuite/
* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
* gas/m68k/mcf-fpu.d: Adjust accordingly.
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* Makefile.def (bfd, opcodes): Fix lib_path.
* Makefile.tpl (POSTSTAGE1_FLAGS_TO_PASS): Replace ADAC with ADAFLAGS.
(restrap): Move under "@if gcc-bootstrap". Fix typo.
* Makefile.in: Regenerate.
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thrown away.
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vector and scalar Multiply 16-Bit Operands instructions.
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2006-05-24 H.J. Lu <hongjiu.lu@intel.com>
PR ld/1485
* config.bfd: Set want64 to true if 64bit bfd is used.
(sh-*-linux*): Use targ64_selvecs for 64bit targets.
(sh*l*-*-netbsdelf*): Likewise.
(sh-*-netbsdelf*): Likewise.
(shl*-*-elf*): Likewise.
(sh[1234]l*-*-elf*): Likewise.
(sh3el*-*-elf*): Likewise.
(shl*-*-kaos*): Likewise.
(sh-*-elf*): Likewise.
(sh[1234]*-elf*): Likewise.
(sh-*-rtems*): Likewise.
(sh-*-kaos*): Likewise.
ld/
2006-05-24 H.J. Lu <hongjiu.lu@intel.com>
PR ld/1485
* configure.in: Use ${srcdir}/../bfd/config.bfd to check 64bit
bfd. Support 64bit host for --enable-targets=all.
* configure: Regenerated.
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bfd/
* elf-bfd.h (elf_backend_data): Add elf_backend_output_arch_local_syms
* elf32-arm.c (output_arch_syminfo): Define.
(elf32_arm_ouput_plt_map_sym, elf32_arm_output_plt_map,
elf32_arm_output_arch_local_syms): New functions.
(elf_backend_output_arch_local_syms): Define.
* elflink.c (bfd_elf_final_link): Call
elf_backend_output_arch_local_syms.
* elfxx-target.h (elf_backend_output_arch_local_syms): Provide default
definition.
(elfNN_bed): Add elf_backend_output_arch_local_syms.
ld/testsuite/
* ld-arm/arm-app-abs32.d: Update expected output.
* ld-arm/arm-app.d: Ditto.
* ld-arm/arm-lib-plt32.d: Ditto.
* ld-arm/arm-lib.d: Ditto.
* ld-arm/mixed-app-v5.d: Ditto.
* ld-arm/mixed-app.d: Ditto.
* ld-arm/mixed-lib.d: Ditto.
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* elf32-arm.c (put_arm_insn, put_thumb_insn): New functions.
(elf32_thumb_to_arm_stub, elf32_arm_to_thumb_stub,
elf32_arm_finish_dynamic_symbol): Use them.
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PR ld/2655
PR ld/2657
* ld-elf/eh1.d: New file.
* ld-elf/eh1.s: Likewise.
* ld-elf/eh1a.s: Likewise.
* ld-elf/eh2.d: Likewise.
* ld-elf/eh2a.s: Likewise.
* ld-elf/eh3.d: Likewise.
* ld-elf/eh3.s: Likewise.
* ld-elf/eh3a.s: Likewise.
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PR ld/2655
PR ld/2657
* elf-eh-frame.c (_bfd_elf_write_section_eh_frame): Properly
update CIE/FDE length. Don't pad to the section alignment.
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include additional registers.
* mt-tdep.c (mt_gdb_regnums): Add ZI2, ZQ2, Ichannel2,
Iscramb2, Qscramb2, Qchannel2.
(mt_register_name): Likewise.
(mt_copro_register_type): Describe ZI2 and ZQ2.
* mt-tdep.c (mt_gdb_regnums): Define
MT_COPRO_PSEUDOREG_MAC_REGNUM.
(mt_register_name): Use it.
(mt_copro_register_type): Likewise.
(mt_register_type): Likewise.
(mt_pseudo_register_read): Likewise. Read the MAC register, not
the coprocessor register.
(mt_pseudo_register_write): Likewise.
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* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
ISA_HAS_MXHC1): New macros.
(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments.
(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
(mips_after_parse_args): Change default handling of float register
size to account for 32bit code with 64bit FP. Better sanity checking
of ISA/ASE/ABI option combinations.
(s_mipsset): Support switching of GPR and FPR sizes via
.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
options.
(mips_elf_final_processing): We should record the use of 64bit FP
registers in 32bit code but we don't, because ELF header flags are
a scarce ressource.
(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
missing -march options. Document .set arch=CPU. Move .set smartmips
to ASE page. Use @code for .set FOO examples.
[ gas/testsuite/Changelog ]
* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
output.
* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
catch assembler warnings.
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if needed.
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deteted entries in .eh_frame section.
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* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
* config/tc-bfin.c (bfin_name_is_register): Remove.
(bfin_equals): Remove.
* config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
(bfin_name_is_register): Remove declaration.
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instead of _GLOBAL_OFFSET_TABLE_.
(bfin_relocate_section): Ditto.
(_bfin_create_got_section): Ditto.
(elf32_bfinfdpic_create_dynamic_sections): Use
__PROCEDURE_LINKAGE_TABLE_ instead of _PROCEDURE_LINKAGE_TABLE_.
(bfin_finish_dynamic_symbol): Use __DYNAMIC instead of _DYNAMIC.
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function syms over other syms.
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