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2006-04-27 PR binutils/2584Kaz Kojima2-24/+73
* tekhex.c (getvalue): Change return type to bfd_boolean and add the new parameter. Return false if the unexpected character is found. (getsym): Likewise. (first_phase): Change return type to bfd_boolean and return false if the unexpected character is found. Replace abort with returning false. (pass_over): Change return type to bfd_boolean and the type of the second argument to bfd_boolean (*) (bfd *, int, char *). Return false if FUNC returns false. (tekhex_object_p): Return NULL if pass_over fails.
2006-04-27 * coff-rs6000.c (xcoff_write_archive_contents_old): Warning fix.Alan Modra2-2/+6
2006-04-27*** empty log message ***gdbadmin1-1/+1
2006-04-27daily updateAlan Modra1-1/+1
2006-04-262006-04-20 Michael Snyder <msnyder@redhat.com>Michael Snyder2-1/+5
* remote.c: Fix spelling error in comment.
2006-04-26 * mips.h: Improve comments describing the bitfield instructionThiemo Seufer2-6/+12
fields.
2006-04-26 * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...Julian Brown2-26/+80
(is_quarter_float): Rename from above. Simplify slightly. (parse_qfloat_immediate): Parse a "quarter precision" floating-point number. (parse_neon_mov): Parse floating-point constants. (neon_qfloat_bits): Fix encoding. (neon_cmode_for_move_imm): Tweak to use floating-point encoding in preference to integer encoding when using the F32 type.
2006-04-26 * gas/testsuite/gas/arm/neon-const.s: New testcase. Neon floating-pointJulian Brown4-2/+572
constants. * gas/testsuite/gas/arm/neon-const.d: Expected output of above. * gas/testsuite/gas/arm/neon-cov.d: Expect floating-point disassembly for VMOV.F32.
2006-04-26 * arm-dis.c (print_insn_neon): Disassemble floating-point constantJulian Brown2-2/+30
VMOV.
2006-04-26 * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (soJulian Brown2-330/+905
zero-initialising structures containing it will lead to invalid types). (arm_it): Add vectype to each operand. (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias defined field. (neon_typed_alias): New structure. Extra information for typed register aliases. (reg_entry): Add neon type info field. (arm_reg_parse): Remove RTYPE argument (revert to previous arguments). Break out alternative syntax for coprocessor registers, etc. into... (arm_reg_alt_syntax): New function. Alternate syntax handling broken out from arm_reg_parse. (parse_neon_type): Move. Return SUCCESS/FAIL. (first_error): New function. Call to ensure first error which occurs is reported. (parse_neon_operand_type): Parse exactly one type. (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move. (parse_typed_reg_or_scalar): New function. Handle core of both arm_typed_reg_parse and parse_scalar. (arm_typed_reg_parse): Parse a register with an optional type. (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar result. (parse_scalar): Parse a Neon scalar with optional type. (parse_reg_list): Use first_error. (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse. (neon_alias_types_same): New function. Return true if two (alias) types are the same. (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type of elements. (insert_reg_alias): Return new reg_entry not void. (insert_neon_reg_alias): New function. Insert type/index information as well as register for alias. (create_neon_reg_alias): New function. Parse .dn/.qn directives and make typed register aliases accordingly. (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start of line. (s_unreq): Delete type information if present. (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls. (s_arm_unwind_save_mmxwcg): Likewise. (s_arm_unwind_movsp): Likewise. (s_arm_unwind_setfp): Likewise. (parse_shift): Likewise. (parse_shifter_operand): Likewise. (parse_address): Likewise. (parse_tb): Likewise. (tc_arm_regname_to_dw2regnum): Likewise. (md_pseudo_table): Add dn, qn. (parse_neon_mov): Handle typed operands. (parse_operands): Likewise. (neon_type_mask): Add N_SIZ. (N_ALLMODS): New macro. (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error. (el_type_of_type_chk): Add some safeguards. (modify_types_allowed): Fix logic bug. (neon_check_type): Handle operands with types. (neon_three_same): Remove redundant optional arg handling. (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm) (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute) (do_neon_step): Adjust accordingly. (neon_cmode_for_logic_imm): Use first_error. (do_neon_bitfield): Call neon_check_type. (neon_dyadic): Rename to... (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield to allow modification of type of the destination. (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly. (do_neon_compare): Make destination be an untyped bitfield. (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX. (neon_mul_mac): Return early in case of errors. (neon_move_immediate): Use first_error. (neon_mac_reg_scalar_long): Fix type to include scalar. (do_neon_dup): Likewise. (do_neon_mov): Likewise (in several places). (do_neon_tbl_tbx): Fix type. (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane) (do_neon_ld_dup): Exit early in case of errors and/or use first_error. (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL. Handle .dn/.qn directives. (REGDEF): Add zero for reg_entry neon field.
2006-04-26 * gas/arm/neon-psyn.s: Basic test of programmers syntax.Julian Brown3-1/+121
* gas/arm/neon-psyn.d: Expected output of above.
2006-04-26 * readelf.c (arm_attr_tag_VFP_arch): Add VFPv3.Julian Brown2-1/+6
2006-04-26 * config/tc-arm.c (limits.h): Include.Julian Brown2-128/+4073
(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1) (fpu_vfp_v3_or_neon_ext): Declare constants. (neon_el_type): New enumeration of types for Neon vector elements. (neon_type_el): New struct. Define type and size of a vector element. (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per instruction. (neon_type): Define struct. The type of an instruction. (arm_it): Add 'vectype' for the current instruction. (isscalar, immisalign, regisimm, isquad): New predicates for operands. (vfp_sp_reg_pos): Rename to... (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn tags. (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ (Neon D or Q register). (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D register. (GE_OPT_PREFIX_BIG): Define constant, for use in... (my_get_expression): Allow above constant as argument to accept 64-bit constants with optional prefix. (arm_reg_parse): Add extra argument to return the specific type of register in when either a D or Q register (REG_TYPE_NDQ) is requested. Can be NULL. (parse_scalar): New function. Parse Neon scalar (vector reg and index). (parse_reg_list): Update for new arm_reg_parse args. (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists. (parse_neon_el_struct_list): New function. Parse element/structure register lists for VLD<n>/VST<n> instructions. (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args. (s_arm_unwind_save_mmxwr): Likewise. (s_arm_unwind_save_mmxwcg): Likewise. (s_arm_unwind_movsp): Likewise. (s_arm_unwind_setfp): Likewise. (parse_big_immediate): New function. Parse an immediate, which may be 64 bits wide. Put results in inst.operands[i]. (parse_shift): Update for new arm_reg_parse args. (parse_address): Likewise. Add parsing of alignment specifiers. (parse_neon_mov): Parse the operands of a VMOV instruction. (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST, OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC, OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64, OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ. (parse_operands): Handle new codes above. (encode_arm_vfp_sp_reg): Rename to... (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if selected VFP version only supports D0-D15. (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z) (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2) (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst) (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new encode_arm_vfp_reg name, and allow 32 D regs. (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm) (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D regs. (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16) (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle constant-load and conversion insns introduced with VFPv3. (neon_tab_entry): New struct. (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and those which are the targets of pseudo-instructions. (neon_opc): Enumerate opcodes, use as indices into... (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB. (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT) (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE) (NEON_ENC_DUP): Define meaningful helper macros to look up values in neon_enc_tab. (neon_shape): Enumerate shapes (permitted register widths, etc.) for Neon instructions. (neon_type_mask): New. Compact type representation for type checking. (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common permitted type combinations. (N_IGNORE_TYPE): New macro. (neon_check_shape): New function. Check an instruction shape for multiple alternatives. Return the specific shape for the current instruction. (neon_modify_type_size): New function. Modify a vector type and size, depending on the bit mask in argument 1. (neon_type_promote): New function. Convert a given "key" type (of an operand) into the correct type for a different operand, based on a bit mask. (type_chk_of_el_type): New function. Convert a type and size into the compact representation used for type checking. (el_type_of_type_ckh): New function. Reverse of above (only when a single bit is set in the bit mask). (modify_types_allowed): New function. Alter a mask of allowed types based on a bit mask of modifications. (neon_check_type): New function. Check the type of the current instruction against the variable argument list. The "key" type of the instruction is returned. (neon_dp_fixup): New function. Fill in and modify instruction bits for a Neon data-processing instruction depending on whether we're in ARM mode or Thumb-2 mode. (neon_logbits): New function. (neon_three_same, neon_two_same, do_neon_dyadic_i_su) (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm) (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes) (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits) (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size) (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su) (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) (do_neon_addsub_if_i, neon_exchange_operands, neon_compare) (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul) (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul) (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv) (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri) (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun) (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn) (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt) (neon_move_immediate, do_neon_mvn, neon_mixed_length) (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long) (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull) (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov) (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp) (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est) (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx) (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave) (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup) (do_neon_ldx_stx): New functions. Neon bit encoding and encoding helpers. (parse_neon_type): New function. Parse Neon type specifier. (opcode_lookup): Allow parsing of Neon type specifiers. (REGNUM2, REGSETH, REGSET2): New macros. (reg_names): Add new VFPv3 and Neon registers. (NUF, nUF, NCE, nCE): New macros for opcode table. (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh, fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd, fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd. Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl, vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif, vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla, vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt, vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli, vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal, vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn, vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup, vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe, vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr, vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd], fto[us][lh][sd]. (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args. (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8. (arm_option_cpu_value): Add vfp3 and neon. (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix VFPv1 attribute.
2006-04-26 * gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction.Julian Brown23-232/+2666
* gas/arm/copro.d: Update accordingly. * gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode. * gas/arm/neon-cond.d: Expected results of above. * gas/arm/neon-cov.s: New test. Coverage of Neon instructions. * gas/arm/neon-cov.d: Expected results of above. * gas/arm/neon-ldst-es.s: New test. Element and structure loads and stores. * gas/arm/neon-ldst-es.d: Expected results of above. * gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads and stores. * gas/arm/neon-ldst-rm.d: Expected results of above. * gas/arm/neon-omit.s: New test. Omission of optional operands. * gas/arm/neon-omit.d: Expected results of above. * gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP instructions. * gas/arm/vfp3-32drs.d: Expected results of above. * gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and conversion instructions. * gas/arm/vfp3-const-conv.d: Expected results of above.
2006-04-26 * opcode/arm.h (FPU_VFP_EXT_V3): Define constant.Julian Brown2-1/+17
(FPU_NEON_EXT_V1): Likewise. (FPU_VFP_HARD): Update. (FPU_VFP_V3): Define macro. (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
2006-04-26 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convertJulian Brown2-368/+1096
%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?]. Add unified load/store instruction names. (neon_opcode_table): New. (arm_opcodes): Expand meaning of %<bitfield>['`?]. (arm_decode_bitfield): New. (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. (print_insn_neon): New. (print_insn_arm): Adjust print_insn_coprocessor call. Call print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. (print_insn_thumb32): Likewise.
2006-04-262006-04-26 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu6-0/+547
PR binutils/2593 * binutils-all/copy-1.d: New file. * binutils-all/copy-1.s: Likewise. * binutils-all/copy-2.d: Likewise. * binutils-all/objcopy.exp: Add run_dump_test "copy-1" and run_dump_test "copy-2". * lib/utils-lib.exp (run_dump_test): New. (slurp_options): Likewise. (regexp_diff): Likewise. (file_contents): Likewise. (verbose_eval): Likewise.
2006-04-262006-04-26 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-7/+21
PR binutils/2593 * elf.c (_bfd_elf_new_section_hook): Don't set section ELF type and flags if its BFD flags have been set. (_bfd_elf_init_private_section_data): Don't copy the output ELF section type from input if it has been set to something different.
2006-04-26Add missing changelog entryAndreas Jaeger4-0/+47
2006-04-26daily updateAlan Modra1-1/+1
2006-04-26*** empty log message ***gdbadmin1-1/+1
2006-04-252006-04-25 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu4-4/+10
* ld-alpha/tlsbin.rd: Updated for readelf change. * ld-alpha/tlsbinr.rd: Likewise. * ld-alpha/tlspic.rd: Likewise.
2006-04-25Regenerate libbfd.h.H.J. Lu1-0/+2
2006-04-25From Masaki MURANAKA <monaka@monami-software.com>:Mark Kettenis2-1/+7
* mips-mdebug-tdep.c (mips_mdebug_frame_prev_register): Change type of last argument to `gdb_byte *'
2006-04-252006-04-11 Jim Blandy <jimb@codesourcery.com>Jim Blandy2-0/+249
Add support for 'target remote |' on MinGW. * ser-mingw.c (struct pipe_state): New structure. (make_pipe_state, free_pipe_state, cleanup_pipe_state) (pipe_windows_open, pipe_windows_close, pipe_windows_read) (pipe_windows_write, pipe_wait_handle): New functions. (_initialize_ser_windows): Register a "pipe" interface based on them.
2006-04-252006-04-25 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu6-5/+68
PR binutils/2467 * elf.c (_bfd_elf_close_and_cleanup): Check elf_tdata (abfd) is NULL first. * elf32-arm.c (elf32_arm_close_and_cleanup): Check if abfd->sections is NULL. (elf32_arm_bfd_free_cached_info): New. (bfd_elf32_bfd_free_cached_info): Defined. * elfxx-target.h (bfd_elfNN_bfd_free_cached_info): Default it to _bfd_free_cached_info. * libbfd-in.h (_bfd_free_cached_info): New. * libbfd: Regenerated. * opncls.c (_bfd_delete_bfd): Check if abfd->memory is NULL. (_bfd_free_cached_info): New.
2006-04-25 * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"Bob Wilson2-26/+65
syntax instead of hardcoded opcodes with ".w18" suffixes. (wide_branch_opcode): New. (build_transition): Use it to check for wide branch opcodes with either ".w18" or ".w15" suffixes.
2006-04-25 * config/tc-xtensa.c (xtensa_create_literal_symbol,Bob Wilson2-4/+6
xg_assemble_literal, xg_assemble_literal_space): Do not set the frag's is_literal flag.
2006-04-25PR 2587Nick Clifton3-1/+14
* Makefile.am: Add empty rule for .m -> .o build in order to work around bug in gmake shipped by Apple. * Makefile.in: Regenerate.
2006-04-25 * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.Bob Wilson2-0/+8
2006-04-252006-04-25 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-0/+12
PR binutils/2467 * binutils-all/objcopy.exp (strip_test): Also test "strip -g" on archive.
2006-04-25Remove spurious entryMichael Snyder1-8/+0
2006-04-25daily updateAlan Modra1-1/+1
2006-04-25*** empty log message ***gdbadmin1-1/+1
2006-04-24forgotten changelog entryMichael Snyder1-0/+21
2006-04-24 * floatformat.c (floatformat_to_double): Fix (biased) exponent=0 case.Julian Brown2-1/+5
2006-04-24 * ser-mingw.c: Include <conio.h>.Daniel Jacobowitz5-71/+259
(struct ser_console_state, struct net_windows_state): Add exit_select, have_stopped, thread. (pipe_select_thread, console_select_thread) (net_windows_select_thread): Don't create a local state copy or close stop_select. Exit on exit_select instead of stop_select. Set have_stopped. (console_select_thread): Don't report control keypresses as pending input. (pipe_select_thread): Allow stop_select to interrupt sleeping. (set_console_wait_handle): Create exit_select and have_stopped. Save the thread handle. Check _kbhit before starting a thread. (ser_console_done_wait_handle): New. (ser_console_close): Close new handles. Wait for the thread to exit. (new_windows_select_thread): Assert that an event occurred. (net_windows_wait_handle): Check for pending input before starting a thread. (net_windows_done_wait_handle): New. (net_windows_open): Create exit_select and have_stopped. Save the thread handle. (net_windows_close): Close new handles. Wait for the thread to exit. (_intiialize_ser_windows): Register done_wait_handle methods. * serial.c [USE_WIN32API] (serial_done_wait_handle): New. * serial.h [USE_WIN32API] (struct serial_ops): Add done_wait_handle. [USE_WIN32API] (serial_done_wait_handle): New prototype. * mingw-hdep.c (gdb_select): Use serial_done_wait_handle.
2006-04-24daily updateAlan Modra1-1/+1
2006-04-24*** empty log message ***gdbadmin1-1/+1
2006-04-23 * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,Kazu Hirata15-29/+37
config/tc-cris.c, config/tc-crx.c, config/tc-i386.c, config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h, config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c, config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
2006-04-23 * Makefile.in (tmp-ld-decode): Fix dependencies.Andreas Schwab2-3/+9
(tmp-ld-cache): Likewise. (tmp-ld-insn): Likewise.
2006-04-23 * rs6000-tdep.c: Include "reggroups.h" only once.Andreas Schwab3-2/+6
* Makefile.in (rs6000-tdep.o): Update dependencies.
2006-04-23daily updateAlan Modra1-1/+1
2006-04-23*** empty log message ***gdbadmin1-1/+1
2006-04-222006-04-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney3-43/+31
* gdb.texinfo (Contributors): Credit frame unwinder contributors. * gdbint.texinfo (Algorithms): Fix errors in frame documentation.
2006-04-22*** empty log message ***gdbadmin1-1/+1
2006-04-22daily updateAlan Modra1-1/+1
2006-04-212006-04-21 Frederic Riss <frederic.riss@st.com>Frederic Riss2-29/+42
* dwarf2read.c (dwarf2_start_subfile): Change prototype to accept compilation directory as last argument. Always pass comp_dir as second argument to start_subfile and prepend dirname to the filename when necessary. Remove now superfluous search for pre-existing subfile. (dwarf_decode_lines): Pass the compilation directory to dwarf2_start_subfile.
2006-04-21 * elf.c (assign_file_positions_except_relocs): Move code settingAlan Modra2-54/+61
file position of non-loaded sections.. (assign_file_positions_for_segments): ..to here.
2006-04-212006-04-20 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-2/+44
PR ld/2537 * elf.c (bfd_section_from_shdr): Allow sections reserved for applications. Issue an error on sections we don't know how to handle.