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2018-03-06Automatic date update in version.inusers/ibm/binutils-2_25GDB Administrator1-1/+1
2018-03-06MIPS/GAS: Fix an ISA override not lifting ABI restrictionsMaciej W. Rozycki46-8/+778
Correct a regression introduced with commit 919731affbef ("Add MIPS .module directive") causing code like: .set mips3 dli $2, 0x9000000080000000 to fail assembly with the following error message produced: Error: number (0x9000000080000000) larger than 32 bits if built with `mips3' selected as the global ISA (e.g. `-march=mips3'). This is because a `.set' directive doing an ISA override does not lift the ABI restriction on register sizes if the ISA remains unchanged. Previously the directive always set register sizes from the ISA chosen, which is what some code expects. Restore the old semantics then. gas/ * config/tc-mips.c (code_option_type): New enum. (parse_code_option): Return status indicating option type. (s_mipsset): Update `parse_code_option' call site accordingly. Always set register sizes from the ISA with ISA overrides. (s_module): Update `parse_code_option' call site. * testsuite/gas/mips/isa-override-1.d: New test. * testsuite/gas/mips/micromips@isa-override-1.d: New test. * testsuite/gas/mips/mips1@isa-override-1.d: New test. * testsuite/gas/mips/mips2@isa-override-1.d: New test. * testsuite/gas/mips/mips32@isa-override-1.d: New test. * testsuite/gas/mips/mips32r2@isa-override-1.d: New test. * testsuite/gas/mips/mips32r3@isa-override-1.d: New test. * testsuite/gas/mips/mips32r5@isa-override-1.d: New test. * testsuite/gas/mips/mips32r6@isa-override-1.d: New test. * testsuite/gas/mips/mips64r2@isa-override-1.d: New test. * testsuite/gas/mips/mips64r3@isa-override-1.d: New test. * testsuite/gas/mips/mips64r5@isa-override-1.d: New test. * testsuite/gas/mips/mips64r6@isa-override-1.d: New test. * testsuite/gas/mips/r3000@isa-override-1.d: New test. * testsuite/gas/mips/r3900@isa-override-1.d: New test. * testsuite/gas/mips/r5900@isa-override-1.d: New test. * testsuite/gas/mips/octeon@isa-override-1.d: New test. * testsuite/gas/mips/octeon3@isa-override-1.d: New test. * testsuite/gas/mips/isa-override-2.l: New list test. * testsuite/gas/mips/mips1@isa-override-2.l: New list test. * testsuite/gas/mips/mips2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r3@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r5@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r6@isa-override-2.l: New list test. * testsuite/gas/mips/r3000@isa-override-2.l: New list test. * testsuite/gas/mips/r3900@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-1.l: New stderr output. * testsuite/gas/mips/isa-override-1.s: New test source. * testsuite/gas/mips/r5900@isa-override-1.s: New test source. * testsuite/gas/mips/isa-override-2.s: New test source. * testsuite/gas/mips/mips1@isa-override-2.s: New test source. * testsuite/gas/mips/mips2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r3@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r5@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r6@isa-override-2.s: New test source. * testsuite/gas/mips/r3000@isa-override-2.s: New test source. * testsuite/gas/mips/r3900@isa-override-2.s: New test source. * testsuite/gas/mips/octeon3@isa-override-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. (cherry picked from commit 5475e3249a6ab15afa0fe00456ada988d940a302)
2018-03-06[Testsuite] treate -specs as both cflags & ldflagsJiong Wang2-1/+17
Backport from master 2014-11-11 Jiong Wang <jiong.wang@arm.com> ld/testsuite/ * lib/ld-lib.exp (run_ld_link_exec_tests): Append board_cflags if gcc driver used as link tool. (run_cc_link_exec_tests): Likewise.
2018-03-06[Testsuite] Fix running unique tests on ARMJiong Wang4-3/+13
Backport from master: 2014-10-30 Will Newton <will.newton@linaro.org> ld/testsuite/ChangeLog: * ld-unique/unique.exp: Use a wider glob for matching ARM targets. * ld-unique/unique.s: Use % instead of @ in .type directive. * ld-unique/unique_shared.s: Likewise.
2018-03-06PR gold/17473: Fix gold build with system C++ headers that use <ctype.h>.Roland McGrath2-1/+12
gold/ PR gold/17473 * binary.cc: Move #include "safe-ctype.h" to be last #include. (cherry picked from commit 95c29a83ebadd0038fd304539a83c5e90798c1b9)
2018-03-06Remove one unnecessary iteration in insertion sortAlan Modra2-4/+8
PR 18867 * elflink.c (elf_link_adjust_relocs): Correct start of insertion sort main loop.
2018-03-06Fix slowdown in ld -r for most common case of out-of-order relocsAlan Modra2-15/+58
I chose insertion sort since relocs are mostly sorted, but there is a common case we can handle better; A run of relocs put out of order due to not linking input files in order. PR 18867 * elflink.c (elf_link_adjust_relocs): Modify insertion sort to insert a run. Return status in case of malloc failure. Adjust callers.
2018-03-06Don't sort ld -r output relocs on alphaAlan Modra2-0/+19
LITERAL/LITUSE relocs must be kept together. PR 18867 * elf64-alpha.c (elf64_alpha_sort_relocs_p): New function. (elf_backend_sort_relocs_p): Define.
2018-03-06Use stable sort for ld -r relocsAlan Modra2-72/+88
A number of targets emit multiple relocs at a given r_offset, and depend on those relocs staying in their original order. PR 18867 * elflink.c (cmp_ext32l_r_offset, cmp_ext32b_r_offset): Delete. (cmp_ext64l_r_offset, cmp_ext64b_r_offset): Delete. (ext32l_r_offset, ext32b_r_offset, ext64l_r_offset, ext64b_r_offset): New functions. (elf_link_adjust_relocs): Use an insertion sort to sort relocs.
2018-03-06Make arm_unaligned_reloc test less sensitive to disassembler output format.Doug Kwan3-13/+24
2015-07-21Bump version to 2.25.2Tristan Gingold13-61/+86
bfd/ 2015-07-21 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.25.2 * configure: Regenerate. binutils/ 2015-07-21 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2015-07-21 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2015-07-21 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2015-07-21 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2015-07-21 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2015-07-21Release 2.25.1, add generated filesbinutils-2_25_1Tristan Gingold18-754/+790
2015-07-21Automatic date update in version.inGDB Administrator1-1/+1
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2015-07-17Correct readelf dynamic section buffer overlow testAlan Modra2-3/+9
PR binutils/18672 * readelf.c (get_32bit_dynamic_section): Correct buffer limit test. (get_64bit_dynamic_section): Likewise.
2015-07-16Automatic date update in version.inGDB Administrator1-1/+1
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2015-07-11Automatic date update in version.inGDB Administrator1-1/+1
2015-07-10Fix an opd->adjust index in elf64-ppc.cRichard Sandiford9-1/+143
bfd/ * elf64-ppc.c (toc_adjusting_stub_needed): Use the symbol value plus addend rather than the original st_value when looking up entries in opd->adjust. ld/testsuite/ * ld-powerpc/tocopt6-inc.s, ld-powerpc/tocopt6a.s, ld-powerpc/tocopt6b.s, ld-powerpc/tocopt6c.s, ld-powerpc/tocopt6.d: New test. * ld-powerpc/powerpc.exp (ppc64elftests): Add it.
2015-07-10Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra10-8/+42
Back in the day support for these processors was added, we probably didn't want to waste PPC_OPCODE bits on minor variations. I've had a complaint that disassembly of mfspr/mtspr was wrong for power8. This patch fixes that problem. Note that since -m860/-m850/-m821 are new gas options enabling the mpc8xx specific mfspr/mtspr variants it is possible that this change will break some mpc8xx assembly code. ie. you might need to modify makefiles to pass -m860 to gas. include/opcode/ * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. opcodes/ * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. gas/ * config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860. * doc/c-ppc.texi (PowerPC-Opts): Likewise. gas/testsuite/ * gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
2015-07-10PPC sync instruction accepts invalid and incompatible operandsPeter Bergner5-17/+55
ISA 2.07 added a new category called Elemental Memory Barriers that modifies the sync instruction to accept an additional operand ESYNC. Edmar added support for this insruction varient here: https://sourceware.org/ml/binutils/2012-02/msg00221.html Looking at this closer, I see that the insert_ls() function is misnamed (since it's attached to the ESYNC operand, not the LS operand) but more importantly, it is silently modifying the LS operand value behind the users back when the LS operand is either invalid or is incompatible with the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly states that assemblers that support the ESYNC operand should report all invalid uses of LS and ESYNC. This patch changes the assembler to error out on invalid and incompatible operand usage. opcodes/ * ppc-opc.c (insert_ls): Test for invalid LS operands. (insert_esync): New function. (LS, WC): Use insert_ls. (ESYNC): Use insert_esync. gas/testsuite/ * gas/ppc/e6500.s <sync>: Fix invalid test. * gas/ppc/e6500.d: Likewise.
2015-07-10Allow for optional operands with non-zero default values.Peter Bergner11-32/+74
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand with the value of either a 0 or 1. It also defines an extended mnemonic with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1". I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the problem is, optional operands that are ommitted always default to the value 0, which is wrong in this case. I have added support for allowing non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE that specifies that the default operand value to be used is stored in the SHIFT field of the operand field immediately following this one. This fixes the rfebb issue. I also fixed the mftb and mfcr instructions so they use the same mechanism. This allows us to flag invalid uses of mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd]. include/opcode/ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. (ppc_optional_operand_value): New inline function. opcodes/ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. * ppc-opc.c (FXM4): Add non-zero optional value. (TBR): Likewise. (SXL): Likewise. (insert_fxm): Handle new default operand value. (extract_fxm): Likewise. (insert_tbr): Likewise. (extract_tbr): Likewise. gas/ * config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value. Allow for optional operands without insert functions. gas/testsuite/ * gas/ppc/power8.d: Fixup rfebb test results. * gas/ppc/a2.s: Fix invalid mfcr test. * gas/ppc/a2.d: Likewise.
2015-07-10ppc476 linker workaround shared lib fixes againAlan Modra6-32/+70
Huh, I can't even write a binary search properly. bfd/ * elf32-ppc.c (ppc_elf_relocate_section): Correct binary search of dynamic relocs. ld/testsuite/ * ld-powerpc/ppc476-shared.s: Repeat dynamic reloc generating insns. * ld-powerpc/ppc476-shared.d: Update. * ld-powerpc/ppc476-shared2.d: Update.
2015-07-10Remove unused MTMSRD_L macro and re-add accidentally deleted comment.Peter Bergner2-2/+6
In the commit that added PowerPC Pair Singles, Ben accidentally removed a comment and re-added an unused MTMSRD_L macro Alan had recently deleted. This was probably just an oversite when he was refreshing his patch to trunk. opcodes/ * ppc-opc.c: Add comment accidentally removed by old commit. (MTMSRD_L): Delete.
2015-07-10ppc476 linker workaround shared lib fixesAlan Modra8-0/+128
When building a shared lib from non-PIC objects, we'll get dynamic text relocations. These need to move with any insns we move. Otherwise the dynamic reloc will modify the branch, resulting in crashes and other unpleasant behaviour. Also, ld -r --ppc476-workaround used with sufficiently aligned PIC objects needs a fix for emitted REL16 relocs. bfd/ * elf64-ppc.c (ppc_elf_relocate_section): Move dynamic text relocs with insns moved by --ppc476-workaround. Correct output of REL16 relocs. ld/testsuite/ * ld-powerpc/ppc476-shared.s, * ld-powerpc/ppc476-shared.lnk, * ld-powerpc/ppc476-shared.d, * ld-powerpc/ppc476-shared2.d: New tests. * ld-powerpc/powerpc.exp: Run them.
2015-07-10Add hwsync extended mnemonic.Peter Bergner6-4/+30
This commit adds a new extended menmonic for "sync 0" (same as "sync"). The ISA documentation doesn't explicitly mention hwsync as an extended mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as the operation that gets performed when the sync's L field is 0. This is only enabled for POWER4 and later. opcodes/ * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. gas/testsuite/ * gas/ppc/a2.d: Fixup test case due to new extended mnemonic. * gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests. * gas/ppc/power4.d: Likewise.
2015-07-10Non-alloc sections don't belong in PT_LOAD segmentsAlan Modra4-7/+28
Taking them out showed a bug in the powerpc64 backend with .branch_lt being removed from output_bfd but not from previously set up segment section maps. Removing the bfd sections meant their sh_flags (and practically everything else) remaining zero, ie. not SHF_ALLOC, triggering complaints about "`.branch_lt' can't be allocated in segment". include/elf/ * internal.h (ELF_SECTION_IN_SEGMENT_1): Ensure PT_LOAD and similar segments only contain alloc sections. ld/ * emultempl/ppc64elf.em (gld${EMULATION_NAME}_after_allocation): Call gld${EMULATION_NAME}_map_segments regardless of need_laying_out.
2015-07-10Align .TOC. for PowerPC64Alan Modra32-175/+200
This change, with prerequisite 0e5fabeb, provides a toc base aligned to 256 bytes rather than 8 bytes. This is necessary for a minor gcc optimisation, allowing use of d-form instructions to correctly access toc-relative items larger than 8 bytes. bfd/ * elf64-ppc.c (TOC_BASE_ALIGN): Define. (ppc64_elf_next_toc_section): Align multi-got toc base. (ppc64_elf_set_toc): Likewise initial toc base and .TOC. symbol. ld/ * emulparams/elf64ppc.sh (GOT): Align. ld/testsuite/ * ld-powerpc/ambiguousv1.d: Update for aligned .got. * ld-powerpc/ambiguousv1b.d: Likewise. * ld-powerpc/ambiguousv2.d: Likewise. * ld-powerpc/defsym.d: Likewise. * ld-powerpc/elfv2-2exe.d: Likewise. * ld-powerpc/elfv2exe.d: Likewise. * ld-powerpc/elfv2so.d: Likewise. * ld-powerpc/relbrlt.d: Likewise. * ld-powerpc/tls.g: Likewise. * ld-powerpc/tlsexe.d: Likewise. * ld-powerpc/tlsexe.g: Likewise. * ld-powerpc/tlsexe.r: Likewise. * ld-powerpc/tlsexetoc.d: Likewise. * ld-powerpc/tlsexetoc.g: Likewise. * ld-powerpc/tlsexetoc.r: Likewise. * ld-powerpc/tlsso.d: Likewise. * ld-powerpc/tlsso.g: Likewise. * ld-powerpc/tlsso.r: Likewise. * ld-powerpc/tlstoc.g: Likewise. * ld-powerpc/tlstocso.d: Likewise. * ld-powerpc/tlstocso.g: Likewise. * ld-powerpc/tlstocso.r: Likewise. * ld-powerpc/tocopt.d: Likewise. * ld-powerpc/tocopt2.d: Likewise. * ld-powerpc/tocopt3.d: Likewise. * ld-powerpc/tocopt4.d: Likewise. * ld-powerpc/tocopt5.d: Likewise.
2015-07-10Rewrite relro adjusting codeAlan Modra4-42/+49
The linker tries to put the end of the last section in the relro segment exactly on a page boundary, because the relro segment itself must end on a page boundary. If for any reason this can't be done, padding is inserted. Since the end of the relro segment is typically between .got and .got.plt, padding effectively increases the size of the GOT. This isn't nice for targets and code models with limited GOT addressing. The problem with the current code is that it doesn't cope very well with aligned sections in the relro segment. When making .got aligned to a 256 byte boundary for PowerPC64, I found that often the initial alignment attempt failed and the fallback attempt to be less than adequate. This is a particular problem for PowerPC64 since the distance between .got and .plt affects the size of plt call stubs, leading to "stubs don't match calculated size" errors. So this rewrite takes a direct approach to calculating a new relro base. Starting from the last section in the segment, we calculate where it must start to position its end on the boundary, or as near as possible considering alignment requirements. The new start then becomes the goal for the previous section to end, and so on for all sections. This of course ignores the possibility that user scripts will place . = ALIGN(xxx); in the relro segment, or provide section address expressions. In those cases we might fail, but the old code probably did too, and a fallback is provided. ld/ * ldexp.h (struct ldexp_control): Delete dataseg.min_base. Add data_seg.relro_offset. * ldexp.c (fold_binary <DATA_SEGMENT_ALIGN>): Don't set min_base. (fold_binary <DATA_SEGMENT_RELRO_END>): Do set relro_offset. * ldlang.c (lang_size_sections): Rewrite code adjusting relro segment base to line up last section on page boundary.
2015-07-10powerpc: Only initialise opcode indices onceAnton Blanchard2-25/+33
The gdb TUI is calling gdb_print_insn() (which calls disassemble_init_powerpc()) enough to show up high in profiles. As suggested by Alan, only initialise if the indices are empty. * ppc-dis.c (disassemble_init_powerpc): Only initialise powerpc_opcd_indices and vle_opcd_indices once.
2015-07-10powerpc: Add slbfee. instructionAnton Blanchard2-0/+8
* ppc-opc.c (powerpc_opcodes): Add slbfee.
2015-07-10Make powerpc bfd ld reloc overflow vs undefined symbols match goldAlan Modra3-40/+36
* elf64-ppc.c (ppc64_elf_relocate_section): Report overflow to stubs, even those for undefined weak symbols. Otherwise, don't report relocation overflow on branches to undefined strong symbols. Fix memory leak. * elf32-ppc.c (ppc_elf_relocate_section): Don't report relocation overflow on branches to undefined strong symbols.
2015-07-10Fix powerpc gas abort on invalid instruction fixupsAlan Modra2-3/+30
* config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups. (md_apply_fix): Report an error on data-only fixups used with insns.
2015-07-10Automatic date update in version.inGDB Administrator1-1/+1
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2015-07-062015-07-06 Doug Kwan <dougkwan@google.com>Doug Kwan12-4/+54
Apply from master 2015-06-29 Doug Kwan <dougkwan@google.com> * testsuite/arm_bl_out_of_range.s: Align stub table so that it appears at address expected by test. * testsuite/arm_cortex_a8_b.s: Ditto. * testsuite/arm_cortex_a8_b_cond.s: Ditto. * testsuite/arm_cortex_a8_bl.s: Ditto. * testsuite/arm_cortex_a8_blx.s: Ditto. * testsuite/arm_cortex_a8_local.s: Ditto. * testsuite/arm_fix_v4bx.s: Ditto. * testsuite/arm_unaligned_reloc.s: Ditto. * testsuite/thumb_bl_out_of_range.s: Ditto. * testsuite/thumb_bl_out_of_range_local.s: Ditto. * testsuite/thumb_blx_out_of_range.s: Ditto.
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