| Age | Commit message (Collapse) | Author | Files | Lines |
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[Changes in V4]
- New testcases for FP callee-saved registers.
scfi-callee-saved-fp-1.s uses D registers, scfi-callee-saved-fp-2.s
uses Q registers and is run with -mbig-endian.
- Added new ops (movk, prfm) to ginsn-misc-1. These ops are not
relevant for SCFI correctness; this testcase merely
ensures graceful handling of ginsn creation for such insns.
- Fixed ginsn-ldst-1 as it included some load / store ops with D
registers, which we now handle. Also added some insns using W and S
registers.
- Added a new test scfi-diag-3 where SCFI machinery reports the
following error when it sees an SVE memory op with callee-saved
register:
"Error: SCFI: unhandled op 0xe5e0e000 may cause incorrect CFI"
[End of changes in V4]
[No changes in V3]
[Changes in V2]
- new testcase scfi-cfg-4.s for the changes in cmp_scfi_state.
- new testcase ginsn-arith-1.s for ginsn creation for various add sub insns.
- removed redundant insns from ginsn-misc-1.s, some of those insns are
now in ginsn-arith-1.s.
- added more ld st opts in ginsn-ldst-1.s testcase.
[End of changes in V2]
Similar to the x86_64 testcases, some .s files contain the corresponding
CFI directives. This helps in validating the synthesized CFI by running
those tests with and without the --scfi=experimental command line
option.
GAS issues some diagnostics, enabled by default, with
--scfi=experimental. The diagnostics have been added with an intent to
help user correct inadvertent errors in their hand-written asm. An
error is issued when GAS finds that input asm is not amenable to
accurate CFI synthesis. The existing scfi-diag-*.s tests in the
gas/testsuite/gas/scfi/x86_64 directory test some SCFI diagnostics
already:
- (#1) "Warning: SCFI: Asymetrical register restore"
- (#2) "Error: SCFI: usage of REG_FP as scratch not supported"
- (#3) "Error: SCFI: unsupported stack manipulation pattern"
- (#4) "Error: untraceable control flow for func 'XXX'"
In the newly added aarch64 testsuite, further tests for additional
diagnostics have been added:
- scfi-diag-1.s in this patch highlights an aarch64-specific diagnostic:
(#5) "Warning: SCFI: ignored probable save/restore op with reg offset"
Additionally, some testcases are added to showcase the (currently)
unsupported patterns, e.g., scfi-unsupported-1.s
mov x16, 4384
sub sp, sp, x16
gas/testsuite/:
* gas/scfi/README: Update comment to include aarch64.
* gas/scfi/aarch64/scfi-aarch64.exp: New file.
* gas/scfi/aarch64/ginsn-arith-1.l: New test.
* gas/scfi/aarch64/ginsn-arith-1.s: New test.
* gas/scfi/aarch64/ginsn-cofi-1.l: New test.
* gas/scfi/aarch64/ginsn-cofi-1.s: New test.
* gas/scfi/aarch64/ginsn-ldst-1.l: New test.
* gas/scfi/aarch64/ginsn-ldst-1.s: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-1.d: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-1.l: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-1.s: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-2.d: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-2.l: New test.
* gas/scfi/aarch64/scfi-callee-saved-fp-2.s: New test.
* gas/scfi/aarch64/scfi-cb-1.d: New test.
* gas/scfi/aarch64/scfi-cb-1.l: New test.
* gas/scfi/aarch64/scfi-cb-1.s: New test.
* gas/scfi/aarch64/scfi-cfg-1.d: New test.
* gas/scfi/aarch64/scfi-cfg-1.l: New test.
* gas/scfi/aarch64/scfi-cfg-1.s: New test.
* gas/scfi/aarch64/scfi-cfg-2.d: New test.
* gas/scfi/aarch64/scfi-cfg-2.l: New test.
* gas/scfi/aarch64/scfi-cfg-2.s: New test.
* gas/scfi/aarch64/scfi-cfg-3.d: New test.
* gas/scfi/aarch64/scfi-cfg-3.l: New test.
* gas/scfi/aarch64/scfi-cfg-3.s: New test.
* gas/scfi/aarch64/scfi-cfg-4.l: New test.
* gas/scfi/aarch64/scfi-cfg-4.s: New test.
* gas/scfi/aarch64/scfi-cond-br-1.d: New test.
* gas/scfi/aarch64/scfi-cond-br-1.l: New test.
* gas/scfi/aarch64/scfi-cond-br-1.s: New test.
* gas/scfi/aarch64/scfi-diag-1.l: New test.
* gas/scfi/aarch64/scfi-diag-1.s: New test.
* gas/scfi/aarch64/scfi-diag-2.l: New test.
* gas/scfi/aarch64/scfi-diag-2.s: New test.
* gas/scfi/aarch64/scfi-diag-3.l: New test.
* gas/scfi/aarch64/scfi-diag-3.s: New test.
* gas/scfi/aarch64/scfi-ldrp-1.d: New test.
* gas/scfi/aarch64/scfi-ldrp-1.l: New test.
* gas/scfi/aarch64/scfi-ldrp-1.s: New test.
* gas/scfi/aarch64/scfi-ldrp-2.d: New test.
* gas/scfi/aarch64/scfi-ldrp-2.l: New test.
* gas/scfi/aarch64/scfi-ldrp-2.s: New test.
* gas/scfi/aarch64/scfi-strp-1.d: New test.
* gas/scfi/aarch64/scfi-strp-1.l: New test.
* gas/scfi/aarch64/scfi-strp-1.s: New test.
* gas/scfi/aarch64/scfi-strp-2.d: New test.
* gas/scfi/aarch64/scfi-strp-2.l: New test.
* gas/scfi/aarch64/scfi-strp-2.s: New test.
* gas/scfi/aarch64/scfi-unsupported-1.l: New test.
* gas/scfi/aarch64/scfi-unsupported-1.s: New test.
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[Changes in V4]
- Use data types uniformly. Use 'unsigned int' instead of 'uint32_t'
for DWARF register numbers. Use offsetT where applicable.
- Minor code restructuring in aarch64_ginsn_safe_to_skip_p (). Move
common code out of switch case.
- Add FP/Advanced SIMD registers to callee-saved registers too.
Updated commit log to include some of the details.
- Check for opnd type AARCH64_OPND_QLF_W or AARCH64_OPND_QLF_S_S in
aarch64_ginsn_ldstp () to detect 32-bit word operations.
- Skip generating ginsns for movk, movz, movn. These do more work than
just simple mov; Skip generating ginsn altogether for these.
- ginsn_dw2_regnum () is now switch case on opnd_class. Each case
exposed by the current set of ginsn creation logic is handled.
- Skip Z register usage altogether for now. Skip sve_misc iclass but
error out if callee-saved FP/Advanced SIMD registers or stack
management are involved.
[End of changes in V4]
[No changes in V3]
[Changes in V2]
- Factored out the ginsn creation functionality from tc-aarch64.c into
tc-aarch64-ginsn.c.
- The switch case in aarch64_ginsn_new now is based on iclass rather
than (earlier) opcode.
- Rename aarch64_ginsn_jump / aarch64_ginsn_jump_cond to
aarch64_ginsn_branch_uncond / aarch64_ginsn_branch_cond respectively.
- Explicitly whitelist irg insn.
- Other minor code comment and readability fixes.
[End of changes in V2]
For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in
GAS works on the generic GAS insns (ginsns). This patch adds support in
the aarch64 backend to create ginsns for a subset of the supported
machine instructions. The subset includes the minimal necessary
instructions to ensure SCFI correctness:
- Any potential register saves and unsaves. Hence, process instructions
belonging to a variety of iclasses involving str, ldr, stp, ldp.
- Any change of flow instructions. This includes all conditional and
unconditional branches, call (bl, blr, etc.) and return.
- Most importantly, any instruction that could affect the two registers
of interest: REG_SP, REG_FP. This set includes all pre-indexed and
post-indexed memory operations, with writeback, on the stack. This
set must also include other instructions (e.g., arithmetic insns)
where the destination register is one of the afore-mentioned registers.
With respect to callee-saved registers in Aarch64, FP/Advanced SIMD
registers D8-D15 are included along with the relevant GPRs. Calculating
offsets for loads and stores especially for Q registers needs special
attention here.
As an example,
str q8, [sp, #16]
On big-endian:
STR Qn stores as a 128-bit integer (MSB first), hence, should record
D8 as being saved at sp+24 rather than sp+16.
On little-endian:
should record D8 as being saved at sp+16
D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used;
hence, they remain "interesting" for SCFI purposes in such cases. A CFI
save slot always represents the low 64 bits, regardless of whether a
save occurs on D, Q or Z registers. Currently, the ginsn creation
machinery can handle D and Q registers on little-endian and big-endian.
Apart from creating ginsn, another key responsibility of the backend is
to make sure there are safeguards in place to detect and alert if an
instruction of interest may have been skipped. This is done via
aarch64_ginsn_unhandled () (similar to the x86 backend). This function
, hence, is also intended to alert when future ISA changes may otherwise
render SCFI results incorrect, because of missing ginsns for the newly
added machine instructions.
At this time, becuase of the complexities wrt endianness in handling Z
register usage, skip sve_misc opclass altogether for now. The SCFI
machinery will error out (using the aarch64_ginsn_unhandled () code
path) though if Z register usage affects correctness.
The current SCFI machinery does not currently synthesize the
PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The
support for this is planned for near future.
SCFI is enabled for ELF targets only.
gas/
* config/tc-aarch64-ginsn.c: New file.
* config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c
file. Invoke aarch64_ginsn_new.
* config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI
enablement.
(TARGET_USE_SCFI): Likewise.
(SCFI_MAX_REG_ID): New definition.
(REG_FP): Likewise.
(REG_LR): Likewise.
(REG_SP): Likewise.
(SCFI_INIT_CFA_OFFSET): Likewise.
(SCFI_CALLEE_SAVED_REG_P): Likewise.
(aarch64_scfi_callee_saved_p): New declaration.
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[New in V4]
Enforce some checks on the newly added subclass flags:
- If a subclass is set of one insn of an iclass, every insn of that
iclass must have non-zero subclass field.
- For all other iclasses, the subclass bits are zero for all insns.
include/
* opcode/aarch64.h (enum aarch64_insn_class): Identify the
maximum iclass enum value.
opcodes/
* aarch64-gen.c (iclass_has_subclasses_p): New array of bool.
(read_table): Enforce checks on subclass flags.
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[Changes in V4]
- Use F_SUBCLASS_OTHER for instructions where F_BRANCH_CALL or
F_BRANCH_RET does not apply.
[End of changes in V4]
[No changes in V3]
[New in V2]
Use the two new subclass flags: F_BRANCH_CALL, F_BRANCH_RET, to indicate
call to and return from subroutine respectively.
opcodes/
* aarch64-tbl.h: Use the new F_BRANCH_* flags.
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[Changes in V4]
- Specify subclasses only for those iclasses relevent to SCFI:
addsub_imm, and addsub_ext
[End of changes in V4]
[No changes in V3]
[New in V2]
Use the three new subclass flags: F_ARITH_ADD, F_ARITH_SUB,
F_ARITH_MOV, to indicate add, sub and mov ops respectively.
opcodes/
* aarch64-tbl.h: Use the new F_ARITH_* flags.
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[Changes in V4]
- Specify subclasses only for those iclasses relevent to SCFI:
ldst_imm9, ldst_pos, ldstpair_indexed, ldstpair_off
[End of changes in V4]
[Changes in V3]
- Use F_LDST_SWAP for lse_atomic ld/st ops. Use of F_LDST_LOAD or
F_LDST_STORE was incorrect.
[End of changes in V3]
[New in V2]
The existing iclass information tells us the general shape and purpose
of the instructions. In some cases, however, we need to further disect
the iclass on the basis of other finer-grain information. E.g., for the
purpose of SCFI, we need to know whether a given insn with iclass
of ldst_* is a load or a store.
opcodes/
* aarch64-tbl.h: Use the new F_LDST_* flags.
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[New in V4]
The existing iclass information tells us the general shape and purpose
of the instructions. In some cases, however, we need to further disect
the iclass on the basis of other finer-grain information. E.g., for the
purpose of SCFI, we need to know whether a given insn with iclass of
ldst_* is a load or a store. Similarly, whether a particular arithmetic
insn is an add or sub or mov, etc.
This patch defines new flags to demarcate the insns. Also provide an
access function for subclass lookup.
Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
one instruction with a non-zero subclass, all instructions of the iclass
must have a non-zero subclass information. If none of the defined
subclasses are applicable (or not required for SCFI purposes),
F_SUBCLASS_OTHER can be used for such instructions.
include/
* opcode/aarch64.h (F_SUBCLASS): New flag.
(F_SUBCLASS_OTHER): Likewise.
(F_LDST_LOAD): Likewise.
(F_LDST_STORE): Likewise.
(F_LDST_SWAP): Likewise.
(F_ARITH_ADD): Likewise.
(F_ARITH_SUB): Likewise.
(F_ARITH_MOV): Likewise.
(F_BRANCH_CALL): Likewise.
(F_BRANCH_RET): Likewise.
(F_MAX_SUBCLASS): Likewise.
(aarch64_opcode_subclass_p): New definition.
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[No changes in V3, V4]
[New in V2]
- This patch is orthogonal to aarch64 support. It is included here
because the testcase added for it is aarch64 specific. It is a
bugfix really.
[End of New in V2]
When the SCFI machinery detects that a register has been restored from
stack, it makes some state changes in the SCFI state object.
Prior to the patch, scfi_state_restore_reg () was setting a value of
(reg, CFI_IN_REG) for (base, state) respectively. This was causing
issues in the cmp_scfi_state () function:
- The default state of all (callee-saved) regs at the beginning of
function is set to (0, CFI_UNDEFINED).
- If a register is saved and restored on some control path, the state
of reg is (reg, CFI_IN_REG) on that path.
- On another control path where the register was perhaps not
used (or saved/restored on stack) remains (0, CFI_UNDEFINED).
- The two states should be treated equal, however, at the point in
program after the register has been restored.
Fix this by resetting the state to (0, CFI_UNDEFINED) in
scfi_state_restore_reg ().
A testcase (scfi-cfg-4.s) for this is added in a subsequent commit.
gas/
* scfi.c (scfi_state_restore_reg): Reset to 0, CFI_UNDEFINED
for base, state.
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The "DWARF parse during linker error" and "Build warn libbar.so" tests
require debug information.
configure defaults to "-O2 -g" but if overriding *FLAGS when building
tests, this might be lost. Explicitly pass -g given these tests require
it.
Originally reported downstream in Gentoo at https://bugs.gentoo.org/934149.
ld/
* testsuite/ld-elf/dwarf.exp: Pass -g for "DWARF parse during linker error".
* testsuite/ld-elf/shared.exp: Ditto for "Build warn libbar.so".
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The new -march=armv9.5-a flag enables access to the
mandatory cpa, lut and faminmax extensions.
Existing test cases for features are extended to verify they
work without additional flags.
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Old enough tools demand no blank between @option and the opening figure
brace. Re-wrap the paragraph as well while at it.
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old object files
R_LARCH_SOP_PUSH_ABSOLUTE with -fPIC was heavily used in the era of gas-2.38.
We do not check this relocation to prevent broken links with old object
files.
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With both sources being registers, these insns are almost commutative;
the only extra adjustment needed is inversion of the encoded condition.
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The same properties apply there.
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..., for differing only in the resulting EFLAGS, which are left
untouched anyway. That's a shorter encoding, available as long as
certain constraints on operands are met; see code comments. (SHL-by-1
forms may then be subject to further optimization that was introduced
earlier.)
Note that kind of as a side effect this also converts multiplication by
1 to shift by 0, which is a plain move or even no-op anyway. That could
be further shrunk (as could be presence of shifts/rotates by 0 in the
original code as well as a fair set of other {nf}-form insns), yet the
expectation (for now) is that people won't write such code in the first
place.
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Avoid changing the encoding when there's no size gain: If there's a REX
or REX2 prefix anyway and the base opcode wouldn't be changed, dropping
just REX.W / REX2.W has no (size) effect. (Same for the AND-by-imm7 case
in the same big conditional.)
While there also pull out the .qword check: For the 2-register-operands
case whether that's done on the 1st or 2nd operand doesn't matter. Due
to reduction in necessary parentheses this improves readability a tiny
bit.
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..., as that leaves EFLAGS untouched anyway. That's a shorter encoding,
available as long as certain constraints on operand size and registers
are met; see code comments.
Note that this requires deferring to derive encoding_evex from {nf}
presence, as in optimize_encoding() we want to avoid touching the insns
when {evex} was also used.
Note further that this requires want_disp32() to now also consider the
opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still
report the original mnemonic (or else things can get confusing). While
there, correct adjacent mis-indentation.
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Unlike for the legacy forms, where there's a difference in the resulting
EFLAGS.CF, for the NF variants the immediate can be got rid of in that
case by switching to a 1-bit rotate in the opposite direction.
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Unlike for the legacy forms, where there's a difference in the resulting
EFLAGS, for the NF variants we can safely replace ones using 0x80 by the
respectively other insn while negating the immediate, saving 3 immediate
bytes (just 1 though for 16-bit operand size). Similarly we can replace
ones using 1 / -1 by INC/DEC (eliminating the immediate).
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... for the purposes of get_line_sb() and _find_end_of_line(): They
support \@ just like macros do, and hence the special casing there also
needs applying.
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Allow to add implicit extensions by using the syntax of `.option arch, +-', so
that the table is shrinked and more readable.
bfd/
* elfxx-riscv.c (check_implicit_always): Removed the unused IMPLICIT
parameter.
(check_implicit_for_i): Likewise.
(riscv_implicit_subsets): Shrink the table by allowing the syntax of
`.option arch, +-' for implicit extensions.
(riscv_update_subset1): New function, called from riscv_update_subset
or riscv_parse_add_implicit_subsets. It basically does the same thing
as riscv_update_subset function before.
(riscv_parse_add_implicit_subsets): Updated.
(riscv_update_subset): Updated.
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When pcrel access overflow, the riscv_zero_pcrel_hi_reloc may convert pcrel
relocation to absolutly access if possible at the relocate stage. We used to
encode the target address into r_sym of R_RISCV_HI20 if it is converted from
R_RISCV_PCREL_HI20. But that may cause segfault if --emit-relocs is set,
since r_sym becomes an address rather than a symbol index. Although the
relocate result is correct, it does not meet the definition, so may cause
unexpected behaviors.
This patch encodes the target address into r_addend, rather than r_sym, if
riscv_zero_pcrel_hi_reloc converts the relocation. Besdies, since the
corresponding pcrel_lo relocation are also changed to absolutly access,
we should also update them to R_RISCV_LO12_I/S.
bfd/
PR 27180
* elfnn-riscv.c (riscv_pcrel_hi_reloc): New boolean `absolute', to
inform corresponding pcrel_lo that the pcrel_hi relocation was already
converted to hi20 relocation.
(riscv_record_pcrel_hi_reloc): Likewise, record `absolute'.
(riscv_pcrel_lo_reloc): Removed `const' for Elf_Internal_Rela *reloc,
since we may need to convert it from pcrel_lo to lo relocation.
(riscv_record_pcrel_lo_reloc): Likewise. Convert pcrel_lo to lo
relocation if corresponding pcrel_hi was converted to hi relocation.
(riscv_zero_pcrel_hi_reloc): Encode target absolute address into
r_addend rather than r_sym. Clear the `addr' to avoid duplicate
relocate in the perform_relocation.
(riscv_elf_relocate_section): Updated.
ld/
PR 27180
* testsuite/ld-riscv-elf/pcrel-lo-addend-3a-emit-relocs.d: New testcase.
Segfault without applying this patch.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
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This patch update the cas instruction in Zabha extension [1],
when both Zabha and Zacas extension enabled.
[1] https://github.com/riscv/riscv-zabha/tags
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension case.
gas/ChangeLog:
* testsuite/gas/riscv/zabha-32.d: New instructions.
* testsuite/gas/riscv/zabha.d: Ditto.
* testsuite/gas/riscv/zabha.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes.
(MASK_AMOCAS_B): Ditto.
(MATCH_AMOCAS_H): Ditto.
(MASK_AMOCAS_H): Ditto.
(DECLARE_INSN): New instructions.
* opcode/riscv.h (enum riscv_insn_class): New class case.
opcodes/ChangeLog:
* riscv-opc.c: New instructions.
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We should set BFD_DECOMPRESS to decompress sections unless dumping the
section contents when reading build-id debuglink.
PR binutils/31925
* objdump.c (open_debug_file): Set BFD_DECOMPRESS to decompress
sections unless dumping the section contents.
* testsuite/binutils-all/objdump.exp (test_build_id_debuglink):
Add a compress option.
Run test_build_id_debuglink with none and zlib.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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Like the previous commit, add two overloads of gdb_tilde_expand, one
takes std::string and other takes gdb::unique_xmalloc_ptr<char>. Make
use of these overloads throughout GDB and gdbserver.
There should be no user visible changes after this commit.
Approved-By: Tom Tromey <tom@tromey.com>
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Add two overloads of gdb_abspath, one which takes std::string and one
which takes gdb::unique_xmalloc_ptr<char>, then make use of these
overloads throughout GDB and gdbserver.
There should be no user visible changes after this commit.
Approved-By: Tom Tromey <tom@tromey.com>
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PR 31728
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gracefully.
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There is no need to loop over the headers twice. Remove that leftover
from the previous scheme. Also, the previous scheme silently ignored
a section being mentioned in two or more SHT_GROUP sections.
* elf.c (process_sht_group_entries): Prevent sections from
belonging to two groups.
(_bfd_elf_setup_sections): Process groups in a single loop
over headers.
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This patch delays setting up elf_next_in_group, elf_sec_group and
elf_group_name when reading ELF object files until after all ELF
sections have been processed by bfd_section_from_shdr. This is simpler
and more robust than the current scheme of driving the whole process
on detecting a section with SHF_GROUP set.
* elf-bfd.h (struct elf_obj_tdata): Delete group_sect_ptr,
num_group and group_search_offset.
* elf.c (Elf_Internal_Group): Delete.
(setup_group): Delete function.
(IS_VALID_GROUP_SECTION_HEADER): Delete macro.
(is_valid_group_section_header),
(process_sht_group_entries): New functions.
(_bfd_elf_setup_sections): Handle group sections here..
(_bfd_elf_make_section_from_shdr): ..rather than here.
(bfd_section_from_shdr): Don't check SHT_GROUP validity here.
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PR 20814
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Simplify a gdb_test_multiple in test-case gdb.base/bg-execution-repeat.exp
using "gdb_test -no-prompt-anchor".
Suggested-By: Guinevere Larsen <blarsen@redhat.com>
Tested on x86_64-linux.
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I ran into the following test failure with test-case
gdb.base/bg-execution-repeat.exp:
...
(gdb) PASS: gdb.base/bg-execution-repeat.exp: c&: repeat bg command
^M
Breakpoint 2, foo () at bg-execution-repeat.c:23^M
23 return 0; /* set break here */^M
print 1^M
$1 = 1^M
(gdb) PASS: gdb.base/bg-execution-repeat.exp: c&: input still accepted
FAIL: gdb.base/bg-execution-repeat.exp: c&: breakpoint hit 2 (timeout)
...
The failure can be easily reproduced by adding a sleep 5 here:
...
+ sleep 5
gdb_test "print 1" " = 1" "input still accepted"
...
There's a race in the test-case, between:
- the command handled in the foreground: the "print 1" command, and
- the command handled in the background: the continue command.
The current way of dealing with this is by putting the inferior to sleep for 5
seconds:
...
foo ();
sleep (5);
foo ();
...
with the aim that the "print 1" command will win the race.
This method is both slow and unreliable.
Fix this by making the inferior wait till the "print 1" command is done.
This reduces running time from ~11s to ~1s.
I also verified that the test-case still triggers on the original problem by
applying this gdb/infcmd.c patch:
...
-strip_bg_char (const char *args, int *bg_char_p)
+strip_bg_char (const char *_args, int *bg_char_p)
{
- const char *p;
+ char *args = const_cast<char *>(_args);
+ char *p;
if (args == nullptr || *args == '\0')
{
@@ -210,6 +211,7 @@ strip_bg_char (const char *args, int *bg_char_p)
p--;
while (p > args && isspace (p[-1]))
p--;
+ *p = '\0';
...
Tested on x86_64-linux, with make-check-all.sh.
PR testsuite/31794
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31794
Reviewed-By: Guinevere Larsen <blarsen@redhat.com>
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Update some of the content to make the specification document hopefully
clearer:
- Fix some typos.
- Use Title case consistently for headings.
- Update text around detection of foreign endianness.
- Split the structure field "Name" in each table to two separate
colunms for additional attention: "Type" and "Name".
- Rename "SFrame endianness" section to "SFrame magic number and
endianness"
- Update text around provisions for extending SFrame for future
ABIs/architectures. Make it clear by tagging all provisions with an
explicit index item "Provisions for future ABIs".
- Add a paragraph on sort order of SFrame FDEs.
- Add a statement for SFRAME_F_FRAME_POINTER flag.
- Add a statement to assert that SFrame version 1 is now obsolete and
should not be used.
libsframe/
* doc/sframe-spec.texi: Small improvements for readability.
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Following feedback received shortly after the initial commit of the
aarch64 instructions for scaling and converting fp8 instructions, this
patch addresses the issues raised in the relevant feedback.
This includes the following changes:
* Standardize all FP8 qualifier-set names. This has resulted in the
renaming of QL_V2FP8B8H to QL_V2_HB_LOWER and, likewise, QL_V28H16B
to QL_V2_HB_FULL.
* Update `FP8_INSN' aarch64_opcode_table[] entries to reflect the new
standardized qualifier-set names mentioned above and, in the case of
the "fcvtn" entries, also add a leading 0 to their opcode values so
they are given as 8 hexadecimal digits in length to ensure
consistency in formatting relative to other entries in the table.
* Revise the added test-cases so that when checking operand fields in
the disassembled binaries, all bits for these fields get tested to
ensure they can be toggled on/off by the relevant operand arguments.
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We have recently updated the interface for raising exceptions to use
long [1] and updated mach_port_t to be "unsigned int". This patches fixes
those problems and will help us port GDB to Hurd x86_64.
Tested on Hurd i686 and x86_64.
[1] https://git.savannah.gnu.org/cgit/hurd/gnumach.git/tree/include/mach/exc.defs
Approved-By: Simon Marchi <simon.marchi@efficios.com>
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The AArch64 instruction table (aarch64-tbl.h) defines the operand
ADDR_SIMPLE as "address with base register (no offset)". During assembly
it is correctly encoded as address with base register (addr.base_regno)
in parse_operands. In warn_unpredictable_ldst it is erroneously treated
as register number (reg.regno).
This resolves the assembler test case "Diagnostics Quality" to
erroneously fail when changing the union in struct aarch64_opnd_info
from union to struct for debugging purposes.
gas/
* config/tc-aarch64.c: Treat operand ADDR_SIMPLE as address with
base register.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The AArch64 instruction table (aarch64-tbl.h) defines the operand
Rt_IN_SYS_ALIASES as register number. During assembly it is correctly
encoded as register number (reg.regno) in parse_operands. During
disassembly it is first correctly decoded as register number (reg.regno)
in aarch64_ext_regno called by aarch64_extract_operand, but then
erroneously treated as immediate value (imm.value) in
aarch64_print_operand.
This resolves the assembler test case "gas/aarch64/brbe-brb-inst" to
erroneously fail on s390. On AArch64 - being little-endian - the struct
aarch64_opnd_info union fields reg.regno and imm.value share their
least-significant bits. On s390 - being big-endian - they do not.
opcodes/
PR binutils/31919
* aarch64-opc.c: Treat operand Rt_IN_SYS_ALIASES as register
number.
Bug: https://sourceware.org/PR31919
Fixes: 72476aca8f58 ("aarch64: add Branch Record Buffer extension instructions")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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I noticed that the 'all-doc' build target doesn't build all the doc
formats, 'man' and 'html' are missing.
This commit updates 'all-doc' so that all formats are built.
This doesn't change the default 'all' target, which is the default
target used when building GDB itself, the 'all' target continues to
just build the 'info' docs.
There should be no difference in the actual generated output after
this commit, I'm just changing what gets built.
Approved-By: Tom Tromey <tom@tromey.com>
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After this commit:
commit 0700386f142f0b0d3d0021995970a1b41c36cc92 (gdb-tmp-c)
Date: Wed May 8 19:12:57 2024 +0100
gdb/doc: fix parallel build of pdf and dvi files
When building the dvi or pdf targets you'd get errors like this:
mkdir: cannot create directory ‘texi2dvi_tmpdir/gdb_dvi’: No such file or directory
mkdir: cannot create directory ‘texi2dvi_tmpdir/gdb_pdf’: No such file or directory
fixed by ensuring the directory is created before calling texi2dvi.
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This patch adds missing contraints to FEAT_B16B16 sve2 instructions
bfclamp, bfmla and bfmls and add negative tests for all the bfloat
instructions.
The bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.*
to maintain consistency in the testsuite.
The bfloat16-1-invalid.* tests are modified so that "selected
processor does not support" is generated by the assembler, since
+b16b16 is not passed in the command line.
The bfloat16-2-invalid.* testcase includes the wrong operands
bfloat16 tests.
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This patch adds some extra tests for the sve2p1 "addqv, andqv, smaxqv,
sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and
fminqv" instructions.
The patch also adds couple of negative testcases, sve2p1-1-bad.d testcase
without "+sve2p1" option and sve2p1-2-bad.d testcase with wrong operands
for sve2p1 instructions.
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The current implementation for the following SVE2p1 instructions add a
constraint in aarch64_opcode_table[] array, so that these instruction
might be immediately preceded in program order by a MOVPRFX instruction.
As per the spec these instruction does not immediately preceded in
program order by a MOVPRFX instruction and to fix this issue, SVE2p1_INSNC
macro is replaced with SVE2p1_INSN macro for the entries of these
instructions in aarch64_opcode_table[] array.
List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv,
eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and fminqv.
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This patch fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q
as mentioned below, for the issues reported here.
https://sourceware.org/pipermail/binutils/2024-February/132408.html
1) Previously all the ld[1-4]q/st[1-4]q instructions are wrongly added as
predicated instructions and this issue is fixed in this patch by replacing
"SVE2p1_INSNC" with "SVE2p1_INSN" macro.
2) Wrong first operand in all the ld[1-4]q/st[1-4]q instructions is fixed
by replacing "SVE_Zt" with "SVE_ZtxN".
3) Wrong operand qualifiers in ld1q and st1q instructions are also fixed in
this patch.
4) In ld1q/st1q the index in the second argument is optional and if index
is xzr and is skipped in the assembly, the index field is ignored by the
disassembler.
Fixing above mentioned issues helps with following:
1) ld1q and st1q first register operand accepts enclosed figure braces.
2) ld2q, ld3q, ld4q, st2q, st3q, and st4q instructions accepts wrapping
sequence of vector registers.
For the instructions ld[2-4]q/st[2-4]q, tests for wrapping sequence of vector
registers are added along with short-form of operands for non-wrapping sequence.
I have added test using following logic:
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #0, MUL VL] //raw insn encoding (all zeroes)
ld2q {Z31.Q, Z0.Q}, p0/Z, [x0, #0, MUL VL] // encoding of <Zt1>
ld2q {Z0.Q, Z1.Q}, p7/Z, [x0, #0, MUL VL] // encoding of <Pg>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x30, #0, MUL VL] // encoding of <Xm>
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #-16, MUL VL] // encoding of <imm> (low value)
ld2q {Z0.Q, Z1.Q}, p0/Z, [x0, #14, MUL VL] // encoding of <imm> (high value)
ld2q {Z31.Q, Z0.Q}, p7/Z, [x30, #-16, MUL VL] // encoding of all fields (all ones)
ld2q {Z30.Q, Z31.Q}, p1/Z, [x3, #-2, MUL VL] // random encoding.
For all the above form of instructions the hyphenated form is preferred for
disassembly if there are more than two registers in the list, and the register
numbers are monotonically increasing in increments of one.
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