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2016-06-09sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi2-0/+7
include/ChangeLog: 2016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h: Add missing documentation for hyperprivileged registers in rd (%) and rs1 ($).
2016-06-09[AARCH64][GAS] Fix two -Wstack-usage warnings.Renlin Li2-7/+10
Warning triggerd by gcc 5 with -O0 flag. error: stack usage might be unbounded [-Werror=stack-usage=] gas/ 2016-06-08 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (print_operands): Substitute size. (output_operand_error_record): Likewise.
2016-06-09Automatic date update in version.inGDB Administrator1-1/+1
2016-06-08i386: Test external function reference without PLTH.J. Lu29-0/+876
To call an external function, the direct branch to the PLT entry can be replaced by an indirect branch via the GOT slot, which is similar to the first instruction in the PLT slot. Instead using the PLT slot as function address, the function address is retrieved from the GOT slot. The R_386_GOT32X relocation can be used to compute the address of the symbol’s GOT entry without base register when PIC is disabled. In non-PIC executable, call/jmp *func@GOT should be used for indirect branch via the GOT slot and movl func@GOT, %eax should be used to load function address. Unlike PIC case, no register is needed to access GOT. If linker determines the function is defined locally, it converts indirect branch via the GOT slot to direct branch with a nop prefix and converts load via the GOT slot to load immediate or lea. * testsuite/ld-i386/libno-plt-1b.dd: New file. * testsuite/ld-i386/libno-plt-1b.rd: Likewise. * testsuite/ld-i386/no-plt-1a.dd: Likewise. * testsuite/ld-i386/no-plt-1a.rd: Likewise. * testsuite/ld-i386/no-plt-1b.dd: Likewise. * testsuite/ld-i386/no-plt-1b.rd: Likewise. * testsuite/ld-i386/no-plt-1c.dd: Likewise. * testsuite/ld-i386/no-plt-1c.rd: Likewise. * testsuite/ld-i386/no-plt-1d.dd: Likewise. * testsuite/ld-i386/no-plt-1d.rd: Likewise. * testsuite/ld-i386/no-plt-1e.dd: Likewise. * testsuite/ld-i386/no-plt-1e.rd: Likewise. * testsuite/ld-i386/no-plt-1f.dd: Likewise. * testsuite/ld-i386/no-plt-1f.rd: Likewise. * testsuite/ld-i386/no-plt-1g.dd: Likewise. * testsuite/ld-i386/no-plt-1g.rd: Likewise. * testsuite/ld-i386/no-plt-1h.dd: Likewise. * testsuite/ld-i386/no-plt-1h.rd: Likewise. * testsuite/ld-i386/no-plt-1i.dd: Likewise. * testsuite/ld-i386/no-plt-1i.rd: Likewise. * testsuite/ld-i386/no-plt-1j.dd: Likewise. * testsuite/ld-i386/no-plt-1j.rd: Likewise. * testsuite/ld-i386/no-plt-check1a.S: Likewise. * testsuite/ld-i386/no-plt-check1b.S: Likewise. * testsuite/ld-i386/no-plt-extern1a.S: Likewise. * testsuite/ld-i386/no-plt-extern1b.S: Likewise. * testsuite/ld-i386/no-plt-func1.c: Likewise. * testsuite/ld-i386/no-plt-main1.c: Likewise. * testsuite/ld-i386/no-plt.exp: Likewise.
2016-06-08Update test nameH.J. Lu2-1/+6
* testsuite/ld-x86-64/tls.exp (run_cc_link_tests): Update test name.
2016-06-08Support i386 TLS code sequences without PLTH.J. Lu32-65/+2751
We can generate i386 TLS code sequences for general and local dynamic models without PLT, which uses indirect call via GOT: call *___tls_get_addr@GOT(%reg) where EBX register isn't required as GOT base, instead of direct call: call ___tls_get_addr[@PLT] which requires EBX register as GOT base. Since direct call is 4-byte long and indirect call, is 5-byte long, the extra one byte must be handled properly. For general dynamic model, 7-byte lea instruction before call instruction is replaced by 6-byte one to make room for indirect call. For local dynamic model, we simply use 5-byte indirect call. TLS linker optimization is updated to recognize new instruction patterns. For local dynamic model to local exec model transition, we generate a 6-byte lea instruction as nop, instead of a 1-byte nop plus a 4-byte lea instruction. Since linker may convert call ___tls_get_addr[@PLT] to addr32 call ____tls_get_addr when producing static executable, both patterns are recognized. bfd/ * elf64-i386.c (elf_i386_link_hash_entry): Add tls_get_addr. (elf_i386_link_hash_newfunc): Initialize tls_get_addr to 2. (elf_i386_check_tls_transition): Check indirect call and direct call with the addr32 prefix for general and local dynamic models. Set the tls_get_addr feild. (elf_i386_convert_load_reloc): Always use addr32 prefix for indirect ___tls_get_addr call via GOT. (elf_i386_relocate_section): Handle GD->LE, GD->IE and LD->LE transitions with indirect call and direct call with the addr32 prefix. ld/ * testsuite/ld-i386/i386.exp: Run libtlspic2.so, tlsbin2, tlsgd3, tlsld2, tlsgd4, tlspie3a, tlspie3b and tlspie3c. * testsuite/ld-i386/pass.out: New file. * testsuite/ld-i386/tls-def1.c: Likewise. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-i386/tls-ld1.S: Likewise. * testsuite/ld-i386/tls-main1.c: Likewise. * testsuite/ld-i386/tls.exp: Likewise. * testsuite/ld-i386/tlsbin2-nacl.rd: Likewise. * testsuite/ld-i386/tlsbin2.dd: Likewise. * testsuite/ld-i386/tlsbin2.rd: Likewise. * testsuite/ld-i386/tlsbin2.sd: Likewise. * testsuite/ld-i386/tlsbin2.td: Likewise. * testsuite/ld-i386/tlsbinpic2.s: Likewise. * testsuite/ld-i386/tlsgd3.dd: Likewise. * testsuite/ld-i386/tlsgd3.s: Likewise. * testsuite/ld-i386/tlsgd4.d: Likewise. * testsuite/ld-i386/tlsgd4.s: Likewise. * testsuite/ld-i386/tlsld2.s: Likewise. * testsuite/ld-i386/tlspic2-nacl.rd: Likewise. * testsuite/ld-i386/tlspic2.dd: Likewise. * testsuite/ld-i386/tlspic2.rd: Likewise. * testsuite/ld-i386/tlspic2.sd: Likewise. * testsuite/ld-i386/tlspic2.td: Likewise. * testsuite/ld-i386/tlspic3.s: Likewise. * testsuite/ld-i386/tlspie3.s: Likewise. * testsuite/ld-i386/tlspie3a.d: Likewise. * testsuite/ld-i386/tlspie3b.d: Likewise. * testsuite/ld-i386/tlspie3c.d: Likewise.
2016-06-08Support any relocation orderH.J. Lu8-23/+34
* testsuite/ld-x86-64/no-plt-1a.rd: Support any relocation order. * testsuite/ld-x86-64/no-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1c.rd: Likewise. * testsuite/ld-x86-64/no-plt-1d.rd: Likewise. * testsuite/ld-x86-64/no-plt-1e.rd: Likewise. * testsuite/ld-x86-64/no-plt-1f.rd: Likewise. * testsuite/ld-x86-64/no-plt-1g.rd: Likewise. * testsuite/ld-x86-64/no-plt.exp: Fix a typo.
2016-06-08Add missing ChangeLog entriesH.J. Lu1-0/+24
2016-06-08X86-64: Test external function reference without PLTH.J. Lu21-0/+557
To call an external function, the direct branch to the PLT entry can be replaced by an indirect branch via the GOT slot, which is similar to the first instruction in the PLT slot. Instead using the PLT slot as function address, the function address is retrieved from the GOT slot. If linker determines the function is defined locally, it converts indirect branch via the GOT slot to direct branch with a nop prefix and converts load via the GOT slot to load immediate or lea, * testsuite/ld-x86-64/libno-plt-1b.dd: Likewise. * testsuite/ld-x86-64/libno-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1a.dd: Likewise. * testsuite/ld-x86-64/no-plt-1a.rd: Likewise. * testsuite/ld-x86-64/no-plt-1b.dd: Likewise. * testsuite/ld-x86-64/no-plt-1b.rd: Likewise. * testsuite/ld-x86-64/no-plt-1c.dd: Likewise. * testsuite/ld-x86-64/no-plt-1c.rd: Likewise. * testsuite/ld-x86-64/no-plt-1d.dd: Likewise. * testsuite/ld-x86-64/no-plt-1d.rd: Likewise. * testsuite/ld-x86-64/no-plt-1e.dd: Likewise. * testsuite/ld-x86-64/no-plt-1e.rd: Likewise. * testsuite/ld-x86-64/no-plt-1f.dd: Likewise. * testsuite/ld-x86-64/no-plt-1f.rd: Likewise. * testsuite/ld-x86-64/no-plt-1g.dd: Likewise. * testsuite/ld-x86-64/no-plt-1g.rd: Likewise. * testsuite/ld-x86-64/no-plt-check1.S: Likewise. * testsuite/ld-x86-64/no-plt.exp: Likewise. * testsuite/ld-x86-64/no-plt-extern1.S: Likewise. * testsuite/ld-x86-64/no-plt-func1.c: Likewise. * testsuite/ld-x86-64/no-plt-main1.c: Likewise.
2016-06-08Automatic date update in version.inGDB Administrator1-1/+1
2016-06-07bfd/s390: Misc minor fixes.Marcin Kościelnicki3-5/+13
The only non-comment fix here is in the code writing out the 3 fixed .got.plt entries - it mistakenly put a 64-bit 0 at offsets 8 and 12 instead of 8 and 16. bfd/ChangeLog: * elf32-s390.c (elf_s390_finish_dynamic_symbol): Fix comment. * elf64-s390.c (elf_s390x_plt_entry): Fix comment. (elf_s390_relocate_section): Fix comment. (elf_s390_finish_dynamic_sections): Fix initialization of fixed .got.plt entries.
2016-06-07mi/mi-interp.c: Add missing bracesSimon Marchi2-10/+20
gdb/ChangeLog: * mi/mi-interp.c (mi_record_changed): Add missing braces.
2016-06-07ld/testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfailMaciej W. Rozycki2-2/+6
Revert the addition of `ft32-*-*' to this test case made with commit d1f70bdcab6c ("Fix lots of linker testsuite failures for the FT32 target.") as this case scores an XPASS now. ld/ * testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfail.
2016-06-07Fix PLT first entry GOT operand calculation.Andreas Krebbel7-3/+76
Embedding the .plt section in another revealed a bug in the way the larl operand of the first magic plt entry is being calculated. Fixed with the attached patch. bfd/ChangeLog: * elf64-s390.c (elf_s390_finish_dynamic_sections): Subtract plt section offset when calculation the larl operand in the first PLT entry. ld/ChangeLog: * testsuite/ld-s390/pltoffset-1.dd: New test. * testsuite/ld-s390/pltoffset-1.ld: New test. * testsuite/ld-s390/pltoffset-1.s: New test. * testsuite/ld-s390/s390.exp: Run new test.
2016-06-07PowerPC VLEAlan Modra18-3720/+3866
VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07Frame static link: Handle null pointer.Bernhard Heckel2-0/+5
2016-06-07 Bernhard Heckel <bernhard.heckel@intel.com> gdb/Changelog: * findvar.c (follow_static_link): Check for valid pointer.
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab9-9/+93
This patch adds the architecture extension "+ras" to enable RAS support. It is enabled by default for -march=armv8.2-a and available but disabled by default for armv8-a and armv8.1-a. gas/ * config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras. (arm_ext_ras): Renamed from arm_ext_v8_2. (insns): Update for arm_ext_v8_2 renaming. (arm_extensions): Add "ras". * doc/c-arm.texi (ARM Options): Add an entry for "ras". * testsuite/gas/arm/armv8-a+ras.d: New. * testsuite/gas/arm/armv8_2-a.d: Add explicit command line options. include/ * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding entries. (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS. opcodes/ * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with ARM_EXT_RAS in relevant entries.
2016-06-07Automatic date update in version.inGDB Administrator1-1/+1
2016-06-06Add method/format information to =record-startedSimon Marchi13-11/+94
Eclipse CDT now supports enabling execution recording using two methods (full and btrace) and both formats for btrace (bts and pt). In the event that recording is enabled behind the back of the GUI (by the user on the command line, or a script), we need to know which method/format are being used, so it can be correctly reflected in the interface. This patch adds this information to the =record-started async record. Before: =record-started,thread-group="i1" After: =record-started,thread-group="i1",method="btrace",format="bts" =record-started,thread-group="i1",method="btrace",format="pt" =record-started,thread-group="i1",method="full" The "format" field is only present when the current method supports multiple formats (only the btrace method as of now). gdb/ChangeLog: * NEWS: Mention the new fields in =record-started. * common/btrace-common.h (btrace_format_short_string): New function declaration. * common/btrace-common.c (btrace_format_short_string): New function. * mi/mi-interp.c (mi_record_changed): Output method and format fields in the =record-started record. * record-btrace.c (record_btrace_open): Adapt record_changed notification. * record-full.c (record_full_open): Likewise. * record.c (cmd_record_stop): Likewise. gdb/doc/ChangeLog: * gdb.texinfo (GDB/MI Async Records): Document method and format fields in =record-started. * observer.texi (record_changed): Add method and format parameters. gdb/testsuite/ChangeLog: * gdb.mi/mi-record-changed.exp: Adjust =record-started output matching.
2016-06-06Support x86-64 TLS code sequences without PLTH.J. Lu48-112/+2789
We can generate x86-64 TLS code sequences for general and local dynamic models without PLT, which uses indirect call via GOT: call *__tls_get_addr@GOTPCREL(%rip) instead of direct call: call __tls_get_addr[@PLT] Since direct call is 4-byte long and indirect call, is 5-byte long, the extra one byte must be handled properly. For general dynamic model, one 0x66 prefix before call instruction is removed to make room for indirect call. For local dynamic model, we simply use 5-byte indirect call. TLS linker optimization is updated to recognize new instruction patterns. For local dynamic model to local exec model transition, we generate 4 0x66 prefixes, instead of 3, before mov instruction in 64-bit and generate a 5-byte nop, instead of 4-byte, before mov instruction in 32-bit. Since linker may convert call *__tls_get_addr@GOTPCREL(%rip) to addr32 call __tls_get_addr when producing static executable, both patterns are recognized. bfd/ * elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr. (elf_x86_64_link_hash_newfunc): Initialize tls_get_addr to 2. (elf_x86_64_check_tls_transition): Check indirect call and direct call with the addr32 prefix for general and local dynamic models. Set the tls_get_addr feild. (elf_x86_64_convert_load_reloc): Always use addr32 prefix for indirect __tls_get_addr call via GOT. (elf_x86_64_relocate_section): Handle GD->LE, GD->IE and LD->LE transitions with indirect call and direct call with the addr32 prefix. ld/ * testsuite/ld-x86-64/pass.out: New file. * testsuite/ld-x86-64/tls-def1.c: Likewise. * testsuite/ld-x86-64/tls-gd1.S: Likewise. * testsuite/ld-x86-64/tls-ld1.S: Likewise. * testsuite/ld-x86-64/tls-main1.c: Likewise. * testsuite/ld-x86-64/tls.exp: Likewise. * testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.dd: Likewise. * testsuite/ld-x86-64/tlsbin2.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.sd: Likewise. * testsuite/ld-x86-64/tlsbin2.td: Likewise. * testsuite/ld-x86-64/tlsbinpic2.s: Likewise. * testsuite/ld-x86-64/tlsgd10.dd: Likewise. * testsuite/ld-x86-64/tlsgd10.s: Likewise. * testsuite/ld-x86-64/tlsgd11.dd: Likewise. * testsuite/ld-x86-64/tlsgd11.s: Likewise. * testsuite/ld-x86-64/tlsgd12.d: Likewise. * testsuite/ld-x86-64/tlsgd12.s: Likewise. * testsuite/ld-x86-64/tlsgd13.d: Likewise. * testsuite/ld-x86-64/tlsgd13.s: Likewise. * testsuite/ld-x86-64/tlsgd14.dd: Likewise. * testsuite/ld-x86-64/tlsgd14.s: Likewise. * testsuite/ld-x86-64/tlsgd5c.s: Likewise. * testsuite/ld-x86-64/tlsgd6c.s: Likewise. * testsuite/ld-x86-64/tlsgd9.dd: Likewise. * testsuite/ld-x86-64/tlsgd9.s: Likewise. * testsuite/ld-x86-64/tlsld4.dd: Likewise. * testsuite/ld-x86-64/tlsld4.s: Likewise. * testsuite/ld-x86-64/tlsld5.dd: Likewise. * testsuite/ld-x86-64/tlsld5.s: Likewise. * testsuite/ld-x86-64/tlsld6.dd: Likewise. * testsuite/ld-x86-64/tlsld6.s: Likewise. * testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise. * testsuite/ld-x86-64/tlspic2.dd: Likewise. * testsuite/ld-x86-64/tlspic2.rd: Likewise. * testsuite/ld-x86-64/tlspic2.sd: Likewise. * testsuite/ld-x86-64/tlspic2.td: Likewise. * testsuite/ld-x86-64/tlspic3.s: Likewise. * testsuite/ld-x86-64/tlspie2.s: Likewise. * testsuite/ld-x86-64/tlspie2a.d: Likewise. * testsuite/ld-x86-64/tlspie2b.d: Likewise. * testsuite/ld-x86-64/tlspie2c.d: Likewise. * testsuite/ld-x86-64/tlsgd5.dd: Updated. * testsuite/ld-x86-64/tlsgd6.dd: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run libtlspic2.so, tlsbin2, tlsgd5b, tlsgd6b, tlsld4, tlsld5, tlsld6, tlsgd9, tlsgd10, tlsgd11, tlsgd14, tlsgd12, tlsgd13, tlspie2a, tlspie2b and tlspie2c.
2016-06-062016-06-06 Christian Groessler <chris@groessler.org>Christian Groessler1-60/+59
* ChangeLog: Fix entry from 2016-06-04.
2016-06-05fixup another old style function definitionTrevor Saunders2-2/+5
gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * itbl-parse.y (yyerror): Use modern argument declaration style.
2016-06-05sh{,64}: make arg type enumTrevor Saunders3-9/+23
The values are always members of the enum, except the two places -1 is assigned only to playcate -Wuninitialized because gcc isn't or at least didn't used to be smart enough to figure out its only used if it was set. gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sh.c (parse_reg): Change type of mode argument to sh_arg_type. (get_operand): Adjust. (insert): Change type of how to bfd_reloc_code_real_type. (insert4): Likewise. * config/tc-sh64.c (shmedia_get_operand): Adjust. (shmedia_parse_reg): Change type of mode to shmedia_arg_type.
2016-06-06Automatic date update in version.inGDB Administrator1-1/+1
2016-06-05nds32: constify ptr_argTrevor Saunders2-1/+6
it points to the result of strchr on a const char *, so it aliases something that is const. Further its only passed to a function that expects a const char *, so there's no reason for it to not be const. gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg const char *.
2016-06-05Automatic date update in version.inGDB Administrator1-1/+1
2016-06-04ld/testsuite/ld-z8k/test-ld.sh: Remove. Checked in by mistake.Christian Groessler1-19/+0
2016-06-04Add z8k ld testsuite and fix range check in coff-z8k.cChristian Groessler63-1/+9986
bfd/ * coff-z8k.c (extra_case): Fix range check for R_JR relocation. ld/ * ld/testsuite/ld-z8k/0filler.s: New file. * ld/testsuite/ld-z8k/branch-target.s: New file. * ld/testsuite/ld-z8k/branch-target2.s: New file. * ld/testsuite/ld-z8k/calr-back-8001.d: New file. * ld/testsuite/ld-z8k/calr-back-8002.d: New file. * ld/testsuite/ld-z8k/calr-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/calr-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/calr-forw-8001.d: New file. * ld/testsuite/ld-z8k/calr-forw-8002.d: New file. * ld/testsuite/ld-z8k/calr-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/calr-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/calr-opcode.s: New file. * ld/testsuite/ld-z8k/dbjnz-forw-8001.d: New file. * ld/testsuite/ld-z8k/dbjnz-forw-8002.d: New file. * ld/testsuite/ld-z8k/dbjnz-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/dbjnz-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/dbjnz-opcode.s: New file. * ld/testsuite/ld-z8k/djnz-back-8001.d: New file. * ld/testsuite/ld-z8k/djnz-back-8002.d: New file. * ld/testsuite/ld-z8k/djnz-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/djnz-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/djnz-forw-8001.d: New file. * ld/testsuite/ld-z8k/djnz-forw-8002.d: New file. * ld/testsuite/ld-z8k/djnz-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/djnz-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/djnz-opcode.s: New file. * ld/testsuite/ld-z8k/filler.s: New file. * ld/testsuite/ld-z8k/jr-back-8001.d: New file. * ld/testsuite/ld-z8k/jr-back-8002.d: New file. * ld/testsuite/ld-z8k/jr-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/jr-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/jr-forw-8001.d: New file. * ld/testsuite/ld-z8k/jr-forw-8002.d: New file. * ld/testsuite/ld-z8k/jr-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/jr-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/jr-opcode.s: New file. * ld/testsuite/ld-z8k/ldr-back-8001.d: New file. * ld/testsuite/ld-z8k/ldr-back-8002.d: New file. * ld/testsuite/ld-z8k/ldr-back-fail-8001.d: New file. * ld/testsuite/ld-z8k/ldr-back-fail-8002.d: New file. * ld/testsuite/ld-z8k/ldr-forw-8001.d: New file. * ld/testsuite/ld-z8k/ldr-forw-8002.d: New file. * ld/testsuite/ld-z8k/ldr-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/ldr-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/ldr-opcode.s: New file. * ld/testsuite/ld-z8k/ldrb-forw-8001.d: New file. * ld/testsuite/ld-z8k/ldrb-forw-8002.d: New file. * ld/testsuite/ld-z8k/ldrb-forw-fail-8001.d: New file. * ld/testsuite/ld-z8k/ldrb-forw-fail-8002.d: New file. * ld/testsuite/ld-z8k/ldrb-opcode.s: New file. * ld/testsuite/ld-z8k/ldrb-opcode2.s: New file. * ld/testsuite/ld-z8k/other-file.s: New file. * ld/testsuite/ld-z8k/reloc.dd: New file. * ld/testsuite/ld-z8k/reloc.ld: New file. * ld/testsuite/ld-z8k/relocseg.dd: New file. * ld/testsuite/ld-z8k/relocseg.ld: New file. * ld/testsuite/ld-z8k/relocseg1.dd: New file. * ld/testsuite/ld-z8k/test-ld.sh: New file. * ld/testsuite/ld-z8k/this-file.s: New file. * ld/testsuite/ld-z8k/z8k.exp: New file.
2016-06-04Automatic date update in version.inGDB Administrator1-1/+1
2016-06-03Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.Peter Bergner9-5/+137
opcodes/ PR binutils/20196 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable opcodes for E6500. gas/ PR binutils/20196 * gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx, stbcx., sthcx., stwcx., stdcx.>: Add tests. * gas/testsuite/gas/ppc/e6500.d: Likewise. * gas/testsuite/gas/ppc/power8.s: Likewise. * gas/testsuite/gas/ppc/power8.d: Likewise. * gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx., stdcx.>: Add tests. * gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu10-31/+158
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode. AMD64 supports indirect branches with 16-bit address via the data size prefix while the data size prefix is ignored by Intel64. gas/ PR binutis/18386 * testsuite/gas/i386/i386.exp: Run x86-64-branch-4. * testsuite/gas/i386/x86-64-branch.d: Updated. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. * testsuite/gas/i386/x86-64-branch-4.l: New file. * testsuite/gas/i386/x86-64-branch-4.s: Likewise. opcodes/ PR binutis/18386 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. (indir_v_mode): New. Add comments for '&'. (reg_table): Replace "{T|}" with "{&|}" on call and jmp. (putop): Handle '&'. (intel_operand_size): Handle indir_v_mode. (OP_E_register): Likewise. * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 64-bit indirect call/jmp for AMD64. * i386-tbl.h: Regenerated
2016-06-03[AArch64][gas] Add support for Cortex-A73Kyrylo Tkachov3-0/+8
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry. * doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
2016-06-03[ARM][gas] Add support for Cortex-A73Kyrylo Tkachov3-0/+8
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry. * doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
2016-06-03Fix C++ build for CygwinJon Turney4-4/+14
gdb/ChangeLog: 2016-06-02 Jon Turney <jon.turney@dronecode.org.uk> * windows-nat.c (handle_output_debug_string): Return type of gdb_signal_from_host() is gdb_signal, not an int. (windows_get_exec_module_filename): Add pointer casts for C++. gdb/gdbserver/ChangeLog: 2016-06-02 Jon Turney <jon.turney@dronecode.org.uk> * win32-low.c (win32_create_inferior): Add pointer casts for C++.
2016-06-03Update x86 linker tests for --disable-x86-relax-relocationsH.J. Lu14-19/+35
Pass -mrelax-relocations=yes to x86 linker tests, which require relax relocations, to support --disable-x86-relax-relocations. * testsuite/ld-i386/i386.exp: Assemble gotpc1.o and pr19319b.o with -mrelax-relocations=yes. * testsuite/ld-i386/lea1a.d (as): Add -mrelax-relocations=yes. * testsuite/ld-i386/lea1b.d (as): Likewise. * testsuite/ld-i386/lea1d.d (as): Likewise. * testsuite/ld-i386/lea1e.d (as): Likewise. * testsuite/ld-i386/lea1f.d (as): Likewise. * testsuite/ld-i386/load7.d (as): Likewise. * testsuite/ld-i386/mov1b.d (as): Likewise. * testsuite/ld-i386/pr19175.d (as): Likewise. * testsuite/ld-ifunc/ifunc-13-i386.d (as): Likewise. * testsuite/ld-ifunc/ifunc-21-i386.d (as): Likewise. * testsuite/ld-ifunc/ifunc-22-i386.d (as): Likewise. * testsuite/ld-x86-64/x86-64.exp: Assemble gotpcrel1a.o, gotpcrel1b.o and gotpcrel1c.o with -mrelax-relocations=yes.
2016-06-03Automatic date update in version.inGDB Administrator1-1/+1
2016-06-02Fix PR python/18984Tom Tromey4-2/+16
This fixes PR python/18984. The bug is that gdbpy_solib_name uses GDB_PY_LL_ARG, whereas it should use GDB_PY_LLU_ARG to avoid overflow. Built and tested on x86-64 Fedora 23. 2016-06-02 Tom Tromey <tom@tromey.com> PR python/18984: * python/python.c (gdbpy_solib_name): Use GDB_PY_LLU_ARG. 2016-06-02 Tom Tromey <tom@tromey.com> PR python/18984: * gdb.python/py-shared.exp: Add solib_name test.
2016-06-02Add "arm_any" architecture type to allow -m option to various binutils to ↵Nick Clifton2-15/+26
match any ARM architecture. PR target/20088 * cpu-arm.c (processors): Add "arm_any" type to match any ARM architecture. (arch_info_struct): Likewise. (architectures): Likewise.
2016-06-02Also check that the group header's sh_info field is valid.Nick Clifton2-2/+3
PR 20089 * objcopy.c (group_signature): Fail if the input symbol table has not been loaded, or if the sh_info field of the group header is 0.
2016-06-02Fix a seg-fault when stripping a corrupt binary.Nick Clifton2-0/+8
PR 20089 * objcopy.c (group_signature): Fail if the input symbol table has not been loaded.
2016-06-02mi-memory-changed.exp: Fix filename passed to untestedSimon Marchi2-1/+5
gdb/testsuite/ChangeLog: * gdb.mi/mi-memory-changed.exp: Fix filename passed to untested.
2016-06-02Allow ARC Linux targets that do not use uclibc.Vineet Gupta6-3/+15
bfd * config.bfd: Replace -uclibc with *. gas * configure.tgt: Replace -uclibc with *. ld * configure.tgt: Replace -uclibc with *.
2016-06-02Replace data32 with data16 in commentsH.J. Lu2-6/+10
The 0x66 prefix is data16, not data32 in 64-bit. * elf64-x86-64.c: Replace data32 with data16 in comments.
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess10-163/+1030
gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-02Fix a bug displaying the interpretation of a CFA block that just contains ↵Nick Clifton2-1/+14
DW_CFA_NOP instructions. * dwarf.c (display_debug_frames): Do not display any interpretation if the block consists solely of DW__CFA_NOPs.
2016-06-02Revert PR16467 changeAlan Modra4-28/+100
This reverts the pr16467 change, which was incorrect due to faulty analysis of the pr16467 testcase. The failure was not due to a mismatch in symbol type (ifunc/non-ifunc) but due to a symbol loop being set up. See https://sourceware.org/ml/binutils/2016-06/msg00013.html for some rambling on versioned symbols and ELF shared library symbol overriding that explain this patch. bfd/ PR ld/20159 PR ld/16467 * elflink.c (_bfd_elf_merge_symbol): Revert PR16467 change. (_bfd_elf_add_default_symbol): Don't indirect to/from defined symbol given a version by a script different to the version of the symbol being added. (elf_link_add_object_symbols): Use _bfd_elf_strtab_save and _bfd_elf_strtab_restore. Don't fudge dynstr references. * elf-strtab.c (_bfd_elf_strtab_restore_size): Delete. (struct strtab_save): New. (_bfd_elf_strtab_save, _bfd_elf_strtab_restore): New functions. * elf-bfd.h (_bfd_elf_strtab_restore_size): Delete. (_bfd_elf_strtab_save, _bfd_elf_strtab_restore): Declare.
2016-06-01ns32k: remove dupplicate definition of input_line_pointerTrevor Saunders2-1/+4
gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ns32k.c: Remove definition of input_line_pointer.
2016-06-01add more extern CTrevor Saunders18-0/+143
opcodes/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * nds32-asm.h: Add extern "C". * sh-opc.h: Likewise. bfd/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf32-hppa.h: Add extern "C". * elf32-nds32.h: Likewise. * elf32-tic6x.h: Likewise. include/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf/mips.h: Likewise. * elf/sh.h: Likewise. * opcode/d10v.h: Likewise. * opcode/d30v.h: Likewise. * opcode/ia64.h: Likewise. * opcode/mips.h: Likewise. * opcode/ppc.h: Likewise. * opcode/sparc.h: Likewise. * opcode/tic6x.h: Likewise. * opcode/v850.h: Likewise.
2016-06-01avr: replace sentinal with iteration from 0 to ARRAY_SIZETrevor Saunders2-4/+8
This seems a little easier to understand than using a sentinal, and will hopefully let the compiler optimize the loop better. It also has the effect that we stop initializing a field of the sentinal that is an enum with zero. gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-avr.c (avr_parse_cons_expression): Replace iteration to sentinal with iteration to array size.
2016-06-01xtensa: typedef enums when defining themTrevor Saunders2-10/+11
I think this is the more typical way to do this. Its also slightly shorter and less repeditive. gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/xtensa-relax.h: Move typedefs of enums to the enums definition.
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