Age | Commit message (Collapse) | Author | Files | Lines |
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2007-02-23 Carlos O'Donell <carlos@codesourcery.com>
* dwarf2.c (_bfd_dwarf2_find_nearest_line): Assume 32-bit
DWARF even with 64-bit addresses.
(_bfd_dwarf2_find_nearest_line): Likewise.
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* elf.c (copy_private_bfd_data): Always rewrite the program headers when a
Solaris interpreter segment is involved.
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(md_assemble): Likewise.
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(MASK_SS_L2RDRD): New.
* s390-opc.txt (pka): Use it.
* gas/s390/esa-g5.s: Adjust for corrected PKA syntax.
* gas/s390/esa-g5.d: Adjust for corrected PKA syntax.
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(spu_target_ops): Add spu_arch_string.
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bfd/
* elflink.c (gc_mark_hook_fn): Remove.
(_bfd_elf_gc_mark): Rename gc_mark_hook_fn to elf_gc_mark_hook_fn.
(bfd_elf_gc_sections): Ditto. Call gc_mark_extra_sections.
* elf-bfd.h (elf_gc_mark_hook_fn): Define.
(elf_backend_data): Add gc_mark_extra_sections.
* elfxx-target.h (elf_backend_gc_mark_extra_sections): Provide default
definition.
(elfNN_bed): Add elf_backend_gc_mark_extra_sections.
* elf32-arm.c (elf32_arm_gc_mark_extra_sections): New function.
(elf_backend_gc_mark_extra_sections): Define.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests): Add gc-unwind.h.
* ld-arm/gc-unwind.s: New file.
* ld-arm/gc-unwind.d: New file.
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BREAKPOINT_HIT and STOP_UNKNOWN.
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mips*el-*-linux-*, mips*-*-linux-*): Set
targ_extra_libpath=$targ_extra_emuls.
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(install_reloc): New function, extracted from..
(write_relocs): ..here. Combine RELOC_EXPANSION_POSSIBLE code
with !RELOC_EXPANSION_POSSIBLE code. Don't add fr_offset when
testing frag size. Set SEC_RELOC here.
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* config/tc-avr.h (TC_FX_SIZE_SLACK): Define.
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* dsp2.igen: Fix copyright notice.
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* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
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* MAINTAINERS: Disable -Werror for cris simulator. Build
sparc64-solaris2.10 instead of the broken sparc-elf.
* solib-frv.c: Include "solib.h".
* Makefile.in (solib-frv.o): Update.
* mt-tdep.c (mt_gdbarch_init): Correct typo in floatformats patch.
* xtensa-tdep.c (xtensa_regset_from_core_section): Cast size_t to int.
(xtensa_frame_this_id, xtensa_frame_prev_register)
(xtensa_push_dummy_call): Use %p.
sim/v850/
* Makefile.in (interp.o): Uncomment and update.
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translation marker from untranslatable strings.
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(m68k_cpus): Add 5210a..5211a, 52230..52235 5224..5225.
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to %llu and cast parameters to unsigned long long.
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jumps with hazard barrier.
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after each call to sim_io_write.
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* s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed.
(INSTR_RRF_U0RF, MASK_RRF_U0RF): Added.
* s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr,
cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF.
2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/esa-g5.d (cfxbr, cfebr, cfdbr): Exchanged floating
point and fixed point operands.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/zarch-z900.d (cfdr, cfer, cfxr, cgdbr, cgebr, cgxbr,
cgdr, cger, cgxr): Likewise.
* gas/s390/zarch-z900.s: Likewise.
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by this simulator.
(decode_coproc): Recognise additional CP0 Config registers
correctly.
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uninterpreted formats. If fmt is one of the uninterpreted types
don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
fmt_word, and fmt_uninterpreted_64 like fmt_long.
(store_fpr): When writing an invalid odd register, set the
matching even register to fmt_unknown, not the following register.
* interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
the the memory window at offset 0 set by --memory-size command
line option.
(sim_store_register): Handle storing 4 bytes to an 8 byte floating
point register.
(sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
register.
(sim_monitor): When returning the memory size to the MIPS
application, use the value in STATE_MEM_SIZE, not an arbitrary
hardcoded value.
(cop_lw): Don' mess around with FPR_STATE, just pass
fmt_uninterpreted_32 to StoreFPR.
(cop_sw): Similarly.
(cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
(cop_sd): Similarly.
* mips.igen (not_word_value): Single version for mips32, mips64
and mips16.
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* s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type.
* s390-opc.c (s390_operands): Add RO_28 as optional gpr.
(INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc
and sfpc.
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* configure: Regenerate.
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* elflink.c (bfd_elf_size_dynamic_sections): Heed default_execstack.
* elfxx-target.h (elf_backend_default_execstack): Define to 1.
(elfNN_bed): Init new field.
* elf64-ppc.c (elf_backend_default_execstack): Define to 0.
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MBytes.
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* configure: Rebuilt.
config/ChangeLog:
* acx.m4 (NCN_STRICT_CHECK_TOOLS): Mark environment variable as
precious. Prefer it over a cached value. Use cached value
verbosely.
(NCN_STRICT_CHECK_TARGET_TOOLS): Likewise. Don't override
environment variable with build-time tools.
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and fix its quoting.
* configure: Rebuilt.
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(Files): Add section name to argument list for pxref.
(Non-debug DLL symbols): Don't use `see' for pxref.
(Embedded Processors): Fix typo.
(GDB/MI Breakpoint Commands): Execution commands generate
*stopped not ^done.
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(write_relocs): Reinstate check for fixup within frag.
* config/tc-bfin.h (TC_FX_SIZE_SLACK): Define.
* config/tc-h8300.h (TC_FX_SIZE_SLACK): Define.
* config/tc-mmix.h (TC_FX_SIZE_SLACK): Define.
* config/tc-sh.h (TC_FX_SIZE_SLACK): Define.
* config/tc-xstormy16.h (TC_FX_SIZE_SLACK): Define.
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configuration.
* configure: Regenerate.
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