aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2019-05-14[gdb/doc] Mention index cache in concept and command indexTom de Vries2-0/+8
The "automatic symbol index cache" entry in the docs is missing entries in the concept and command indices. Add them. gdb/doc/ChangeLog: 2019-05-14 Tom de Vries <tdevries@suse.de> * gdb.texinfo (Automatic symbol index cache): Add concept and command index entries.
2019-05-14Add missing verilogtest.s file.Nick Clifton1-0/+12
2019-05-14Add file name styling to "info sharedlibrary"Tom Tromey4-1/+34
This changes "info sharedlibrary" to add styling to the file name. Tested on x86-64 Fedora 29. gdb/ChangeLog 2019-05-14 Tom Tromey <tromey@adacore.com> * solib.c (info_sharedlibrary_command): Style the file name. gdb/testsuite/ChangeLog 2019-05-14 Tom Tromey <tromey@adacore.com> * gdb.base/info-shared.exp (check_info_shared): Add "info shared" styling test.
2019-05-14Fix illegal memory access triggered when attempting to assemble a bogus i386 ↵Nick Clifton2-0/+12
source file. PR 24538 * config/tc-i386-intel.c (i386_intel_simplify_register): Reject illegal register numbers.
2019-05-14Add new option to objcopy: --verilog-data-width. Use this option to set the ↵Jamey Hicks11-12/+179
size of byte bundles generated in verilog format files. PR 19921 binutils* objcopy.c: Add new option --verilog-data-width. Use it to set the value of VerilogDataWidth. * doc/binutils.texi: Document the new option. * testsuite/binutils-all/objcopy.exp: Run tests of new option. * testsuite/binutils-all/verilog-1.hex: New file. * testsuite/binutils-all/verilog-2.hex: New file. * testsuite/binutils-all/verilog-4.hex: New file. * testsuite/binutils-all/verilog-8.hex: New file. * NEWS: Mention the new feature. bfd * verilog.c: (VerilogDataWidth): New variable. (verilog_write_record): Emit bytes in VerilogDataWidth bundles.
2019-05-14A series of fixes to addres problems detected by compiling the assembler ↵Nick Clifton31-139/+178
with address sanitization enabled. PR 24538 gas * macro.c (get_any_string): Increase size of buffer used to hold decimal value of expression result. * dw2gencfi.c (get_debugseg_name): Handle an empty name. * dwarf2dbg.c (get_filenum): Catch integer wraparound when extending allocate file array. (dwarf2_directive_filename): Add extra checks of the computed file number. * config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into warning hash table. (s_arm_eabi_attribute): Check for obj_elf_vendor_attribute returning -1. * config/tc-i386.c (i386_output_nops): Catch an attempt to generate nops of negative lengths. * as.h (MAX_LITTLENUMS): Move definition to here from... * config/atof-ieee.c: ...here. * config/tc-aarch64.c: ...here. * config/tc-arc.c: ...here. * config/tc-arm.c: ...here. * config/tc-epiphany.c: ...here. * config/tc-i386.c: ...here. * config/tc-ia64.c: ...here. (And correct the value). * config/tc-m32c.c: ...here. * config/tc-m32r.c: ...here. * config/tc-metag.c: ...here. * config/tc-microblaze.c: ...here. * config/tc-nds32.c: ...here. * config/tc-or1k.c: ...here. * config/tc-score.c: ...here. * config/tc-score7.c: ...here. * config/tc-tic4x.c: ...here. * config/tc-tilegx.c: ...here. * config/tc-tilepro.c: ...here. * config/tc-visium.c: ...here. * config/tc-sh.c (md_assemble): Add check for an instruction with no opcodes. * config/tc-mips.c (mips_lookup_insn): Add check for very short instruction name. * config/tc-tic54x.c: Use unsigned chars to access is_end_of_line array. (tic54x_start_line_hook): Check for an empty line. (next_line_shows_parallel): Do not walk off the end of the string. (tic54x_macro_start): Check for too much macro nesting. (tic54x_start_label): Add label_start parameter. Use this parameter to check the first character of the label. * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass line_start variable to tic54x_start_label. PR 24538 opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the end of the table prematurely.
2019-05-14AArch64: Add half float view to V registersAlan Hayward10-0/+43
AArch64 can fill the vector registers with half precision floats. Add a view for this. Add builtin type ieee half and connect this to the existing floatformats_ieee_half. gdb/ChangeLog: 2019-05-14 Alan Hayward <alan.hayward@arm.com> * aarch64-tdep.c (aarch64_vnh_type): Add half view. (aarch64_vnv_type): Likewise. * target-descriptions.c (make_gdb_type): Add TDESC_TYPE_IEEE_HALF. * common/tdesc.c: Likewise. * common/tdesc.h (enum tdesc_type_kind): Likewise. * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate. * features/aarch64-fpu.xml: Add ieee half view. * features/aarch64-sve.c (create_feature_aarch64_fpu): Likewise. * gdbtypes.c (gdbtypes_post_init): Add builtin_half * gdbtypes.h (struct builtin_type): Likewise. (struct objfile_type): Likewise.
2019-05-14[gdb/testsuite] Fix base address selection entry encoding in dw2-skip-prologue.STom de Vries2-1/+6
A base address selection entry in a location list consist of two (constant or relocated) address offsets. The two offsets are the same size as an address on the target machine. The test-case gdb.dwarf2/dw2-skip-prologue.S encodes a base address selection entry using .4byte, which is incorrect for 8-byte pointer size. [ Which triggers an assert in dwz, see PR dwz/24172. ] Fix this by using PTRBYTE instead. Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-05-14 Tom de Vries <tdevries@suse.de> * gdb.dwarf2/dw2-skip-prologue.S (.debug_loc): Fix base address selection entry encoding.
2019-05-14[gdb/doc] Fix "maint info selftests" command index entryTom de Vries2-1/+6
Currently, the entry for the command "maint info selftests" in the Command, Variable, and Function Index is listed at '"', rather than next to the other "maint info" commands. Fix this by removing the superfluous quoting in the @kindex entry. gdb/doc/ChangeLog: 2019-05-14 Tom de Vries <tdevries@suse.de> * gdb.texinfo (Maintenance Commands): Remove superfluous quoting on command index entry for "maint info selftests".
2019-05-14Automatic date update in version.inGDB Administrator1-1/+1
2019-05-13Automatic date update in version.inGDB Administrator1-1/+1
2019-05-12Fix two langauge -> language typosSimon Marchi3-2/+8
2019-05-12Automatic date update in version.inGDB Administrator1-1/+1
2019-05-11Document the GDB 8.3 release in gdb/ChangeLogJoel Brobecker1-0/+4
gdb/ChangeLog: GDB 8.3 released.
2019-05-10Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6Faraz Shahbazker9-14/+71
Release 6 of the MIPS architecture does not have an ADDI instruction. ADD/SUB instructions with immediate operands can be expanded to load and immediate value and then perform the operation. gas/ * config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>: Add expansions for MIPS r6. * testsuite/gas/mips/add.s: Enable tests for R6. * testsuite/gas/mips/daddi.s: Annotate to test DADD for R6. * testsuite/gas/mips/mipsr6@add.d: Likewise. * gas/testsuite/gas/mips/mipsr6@dadd.d: New test. * gas/testsuite/gas/mips/mips.exp: Run the new test. opcodes/ * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB macros for R6.
2019-05-11PowerPC objdump -MrawAlan Modra2-3/+10
* ppc-dis.c (print_insn_powerpc) Don't skip optional operands when -Mraw is in effect.
2019-05-11Automatic date update in version.inGDB Administrator1-1/+1
2019-05-11Fix problem with ICF where diffs in EH frame info is ignored.Joshua Oreman9-34/+438
PR gold/21066 * gc.h (gc_process_relocs): Track relocations in .eh_frame sections when ICF is enabled, even though the .eh_frame sections themselves are not foldable. * icf.cc (get_section_contents): Change arguments to permit operation on just part of a section. Include extra identity regions in the referring section's contents recursively. (match_sections): Lock object here instead of in get_section_contents so that get_section_contents can operate recursively. (Icf::add_ehframe_links): New method. (Icf::find_identical_sections): Pass .eh_frame sections to add_ehframe_links(). Increase default iteration count from 2 to 3 because handling exception info typically requires one extra iteration. * icf.h (Icf::extra_identity_list_): New data member with accessor. (is_section_foldable_candidate): Include .gcc_except_table sections. * options.h: Update documentation for new default ICF iteration count. * testsuite/Makefile.am (icf_test_pr21066): New test case. * testsuite/Makefile.in: Regenerate. * testsuite/icf_test_pr21066.cc: New source file. * testsuite/icf_test_pr21066.sh: New test script.
2019-05-10Fix GDB build when using --disable-gdbmiSimon Marchi7-32/+39
Since commit b4be1b064860 ("Fix MI output for multi-location breakpoints") we get this error when building with --disable-gdbmi: CXXLD gdb /home/smarchi/src/binutils-gdb/gdb/breakpoint.c:6358: error: undefined reference to 'mi_multi_location_breakpoint_output_fixed(ui_out*)' This is due to breakpoint.c using a function defined in mi/mi-main.c, even though mi/mi-main.c isn't included in the build. To fix it, use the flags feature of ui_out. mi_ui_out has the new fix_multi_location_breakpoint_output flag set for versions >= 3. Also, move the global variable fix_multi_location_breakpoint_output to breakpoint.c, so it can be read there even when we build without MI. I renamed it to fix_multi_location_breakpoint_output_globally so it doesn't clash with the new enumerator. gdb/ChangeLog: * breakpoint.h (fix_multi_location_breakpoint_output_globally): New variable declaration. * breakpoint.c (fix_multi_location_breakpoint_output_globally): New variable. (print_one_breakpoint): Use ui_out::test_flags and new global variable to compute use_fixed_output. * mi/mi-main.h (mi_multi_location_breakpoint_output_fixed): Remove. * mi/mi-main.c (fix_multi_location_breakpoint_output): Remove. (mi_multi_location_breakpoint_output_fixed): Remove. (mi_cmd_fix_multi_location_breakpoint_output): Adjust to set the new variable. * mi/mi-out.c (mi_ui_out::mi_ui_out): Set fix_multi_location_breakpoint_output flag if version >= 3. * ui-out.h (enum ui_out_flag) <fix_multi_location_breakpoint_output>: New enumerator.
2019-05-10cc-with-tweaks: show dwz stderr and verify resultSimon Marchi2-2/+36
When running the gdb.base/index-cache.exp test case with the cc-with-dwz-m board, I noticed that the final executable didn't actually contain a .gnu_debugaltlink section with the name of the external dwz file: $ readelf --debug-dump=links testsuite/outputs/gdb.base/index-cache/index-cache * empty * Running dwz by hand, I realized it's because dwz complains that the output .debug_info section is empty and fails: $ gcc ~/src/binutils-gdb/gdb/testsuite/gdb.base/index-cache.c -g3 -O0 -o a && cp a b $ dwz -m foo a b dwz: foo: .debug_info section not present $ echo $? 1 This is because index-cache.c is trivial (just an empty main) and dwz doesn't find anything to factor out to the dwz file. [1] I think that cc-with-tweaks should fail in this scenario: if the user asks for an external dwz file to be generated (the -m flag), then it should be an error if cc-with-tweaks doesn't manage to produce an executable with the proper link to this external dwz file. Otherwise, the test runs with a regular non-dwzified executable, which gives a false sense of security about whether the feature under test works with dwzified executables. So this patch adds checks for that after invoking dwz. It also removes the 2>&1 to allow the error message to be printed like so: Running /home/smarchi/src/binutils-gdb/gdb/testsuite/gdb.base/index-cache.exp ... gdb compile failed, dwz: /home/smarchi/build/binutils-gdb/gdb/testsuite/outputs/gdb.base/index-cache/index-cache.dwz: .debug_info section not present - In the -m case (multi-file compression), we check if the expected output file exists. - In the -z case (single-file compression), we check if the file contents has changed. This should catch cases where dwz doesn't modify the file because it's not worth it. It was chosen not to check for dwz's exit code, as it is not very reliable up to dwz 0.12. With this patch, fewer tests will pass than before with the cc-with-dwz and cc-with-dwz-m boards, but those were false positives anyway, as the test ran with regular executables. [1] Note that dwz has been patched by Tom de Vries to work correctly in this case, so we can use dwz master to run the test: https://sourceware.org/git/?p=dwz.git;a=commit;h=08becc8b33453b6d013a65e7eeae57fc1881e801 gdb/ChangeLog: * contrib/cc-with-tweaks.sh: Validate dwz's work.
2019-05-10Document lazy computation for pretty-printer "children" methodTom Tromey2-0/+11
I found out recently that some users didn't know that the Python pretty-printers "children" method should compute its result lazily. This has been a good idea since the earliest days, but wasn't mentioned in the docs. This patch adds some text to this effect. gdb/doc/ChangeLog 2019-05-10 Tom Tromey <tromey@adacore.com> * python.texi (Pretty Printing API): Mention lazy computation for "children".
2019-05-10Add completion for Ada catch commandsTom Tromey4-2/+31
This patch adds a completion function to the "catch exception" and "catch handlers" commands. Tested on x86-64 Fedora 29; reviewed off-list by Joel. gdb/ChangeLog 2019-05-10 Tom Tromey <tromey@adacore.com> * ada-lang.c (catch_ada_completer): New function. (_initialize_ada_language): Use it. gdb/testsuite/ChangeLog 2019-05-10 Tom Tromey <tromey@adacore.com> * gdb.ada/info_exc.exp: Add "complete" test.
2019-05-10Minor "catch" documentation improvementsTom Tromey2-8/+14
This patch makes a few minor improvements to the catchpoint documentation: * "catch exception" and "catch handlers" now mention the argument in the @item. * "catch exception unhandled" is moved to be closer to "catch exception", rather than after "catch handlers". * "catch load" and "catch unload" now wrap the argument in @var. gdb/doc/ChangeLog 2019-05-10 Tom Tromey <tromey@adacore.com> * gdb.texinfo (Set Catchpoints): Add text for parameter to "catch exception" and "catch handlers". Move "catch exception unhandled" text. Use @var for "catch load" and "catch unload"
2019-05-10Re: Sign-extend start and stop address inputs to objdumpAlan Modra2-8/+21
git commit 2379f9c475 introduced an rx-elf test failure. This fixes it. * testsuite/binutils-all/objdump.exp (test_objdump_disas_limited), (test_objdump_content_limited): Add text arg, use in place of .text. (bintest_signed.o): Call get_standard_section_names for name of text section.
2019-05-10Two minor constificationsTom Tromey5-4/+14
I noticed a couple of spots where a "char *" was used where a "const char *" made more sense. This patch fixes both of them. Tested by rebuilding. gdb/ChangeLog 2019-05-10 Tom Tromey <tromey@adacore.com> * thread.c (print_thread_info): Make "requested_threads" const. * gdbthread.h (print_thread_info): Make "requested_threads" const. * ada-tasks.c (print_ada_task_info): Make "taskno_str" const. * ada-lang.h (print_ada_task_info): Make "taskno_str" const.
2019-05-10Automatic date update in version.inGDB Administrator1-1/+1
2019-05-09Update printing of optional operands during disassembly.Peter Bergner3-13/+12
opcodes/ * ppc-dis.c (skip_optional_operands): Change return type and returns. (print_insn_powerpc) <skip_optional>: Change type. Call skip_optional_operands if we have not skipped any operands. gas/ * testsuite/gas/ppc/476.d: Update expected output. * testsuite/gas/ppc/power6.d: Likewise.
2019-05-09[gas][testsuite] Don't specify arch in testsuite outputMatthew Malcomson2-1/+5
My testcase matched against a file format of elf64-littleaarch64 in the objdump output. This was unnecessarily restrictive and causes testcase failures on aarch64_be. Here we remove that restriction. Committed as obvious. Testing done on aarch64_be-none-elf gas to see the failure goes away. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/sve2.d: Remove file format restriction.
2019-05-09[gdb/testsuite] Fix gdb.arch/amd64-tailcall-self.STom de Vries2-12/+17
The test-case gdb.arch/amd64-tailcall-self.exp fails here: ... if ![runto b] { return -1 } ... like: ... (gdb) file build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\ amd64-tailcall-self Reading symbols from build/gdb/testsuite/outputs/gdb.arch/\ amd64-tailcall-self/amd64-tailcall-self... Dwarf Error: Cannot find DIE at 0x1f5 referenced from DIE at 0x107 [in \ module build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\ amd64-tailcall-self] ... The problem is that in amd64-tailcall-self.S, CU-relative references are assigned .debug_info section relative values. [ This is similar to the problem fixed by "Fix gdb.arch/amd64-entry-value-paramref.S". ] Fix this by assigning CU-relative references instead. Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-05-09 Tom de Vries <tdevries@suse.de> * gdb.arch/amd64-tailcall-self.S: Make DW_FORM_ref4 references CU-relative.
2019-05-09[binutils][aarch64] Add SVE2 testsMatthew Malcomson13-0/+8621
Add tests that SVE2 instructions are encoded as they should be, and tests that invalid instructions have their problems reported. Also check that each sve2 cryptographic extension is required to use the corresponding cryptographic instructions. Finally, test to ensure that sve2 instructions using mnemonics that exist in sve1 still need the sve2 feature to be used. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: New test. * testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.s: Test new instructions. * testsuite/gas/aarch64/sve1-extended-sve2.s: New test. * testsuite/gas/aarch64/sve2.d: Test new instructions. * testsuite/gas/aarch64/sve2.s: Test new instructions.
2019-05-09[binutils][aarch64] Add SVE2 instructions.Matthew Malcomson3-941/+4569
This patch adds all the SVE2 instructions and their associated qualifier sets. Ok for trunk? opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (OP_SVE_BBU): New variant set. (OP_SVE_BBB): New variant set. (OP_SVE_DDDD): New variant set. (OP_SVE_HHH): New variant set. (OP_SVE_HHHU): New variant set. (OP_SVE_SSS): New variant set. (OP_SVE_SSSU): New variant set. (OP_SVE_SHH): New variant set. (OP_SVE_SBBU): New variant set. (OP_SVE_DSS): New variant set. (OP_SVE_DHHU): New variant set. (OP_SVE_VMV_HSD_BHS): New variant set. (OP_SVE_VVU_HSD_BHS): New variant set. (OP_SVE_VVVU_SD_BH): New variant set. (OP_SVE_VVVU_BHSD): New variant set. (OP_SVE_VVV_QHD_DBS): New variant set. (OP_SVE_VVV_HSD_BHS): New variant set. (OP_SVE_VVV_HSD_BHS2): New variant set. (OP_SVE_VVV_BHS_HSD): New variant set. (OP_SVE_VV_BHS_HSD): New variant set. (OP_SVE_VVV_SD): New variant set. (OP_SVE_VVU_BHS_HSD): New variant set. (OP_SVE_VZVV_SD): New variant set. (OP_SVE_VZVV_BH): New variant set. (OP_SVE_VZV_SD): New variant set. (aarch64_opcode_table): Add sve2 instructions.
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson10-22/+53
New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson5-0/+30
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions. This iclass encodes one of three variants by the most significant bit set in a 3-bit value where only one bit may be set. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_tsz_bhs iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_tsz_bhs iclass decode.
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson11-14/+47
This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson5-0/+25
This new iclass encodes the variant by which is the most significant bit used of bits 23-22:20-19, where those bits are usually part of a given constant operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass decode.
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson12-32/+87
Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson5-0/+30
Add sve_size_013 instruction class This new iclass handles instructions such as pmullb whose size specifier can only be encoded as 0, 1, or 3. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_013 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_013 iclass decode.
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson5-0/+14
Add new iclass sve_size_bh to handle instructions that have two variants encoded with the SVE_sz field. This iclass behaves the same as the sve_size_sd iclass, but it has a nicer name for those instructions that choose between variants using the "B" and "H" size qualifiers. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_bh iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_bh iclass decode.
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson7-0/+24
Define new sve_size_sd2 iclass to distinguish between the two variants of ldnt1sb and ldnt1sh. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_sd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_sd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_sz2 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson10-70/+159
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson11-14/+50
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson7-0/+28
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field value to determine the variant of an instruction. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_hsd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_hsd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_size field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson11-38/+69
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2019-05-09[binutils][aarch64] Allow movprfx for SVE2 instructions.Matthew Malcomson2-1/+8
SVE2 introduces a number of new instructions that work with the movprfx instruction. This commit ensures that SVE2 instructions are accounted for. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 instructions.
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson7-0/+90
Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09Use the correct names for the init and fini array start symbols in the ↵Dimitar Dimitrov2-2/+7
default Pru linker script. * scripttempl/pru.sc (__init_array_begin, __init_array_begin): Rename.
2019-05-09Automatic date update in version.inGDB Administrator1-1/+1
2019-05-09[gdb/testsuite] Fix gdb.arch/amd64-entry-value-paramref.STom de Vries2-13/+18
The file gdb.arch/amd64-entry-value-paramref.S contains a DIE for function bar: ... DIE29: .uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram) .ascii "bar\0" # DW_AT_name .byte 0x1 # DW_AT_decl_file (gdb.arch/amd64-entry-value-paramref.cc) .byte 0x15 # DW_AT_decl_line .long DIE45 # DW_AT_type .byte 0x1 # DW_AT_inline ... which refers to DIE45: ... DIE45: .uleb128 0x4 # (DIE (0x45) DW_TAG_base_type) .byte 0x4 # DW_AT_byte_size .byte 0x5 # DW_AT_encoding .ascii "int\0" # DW_AT_name ... using a form DW_FORM_ref4: ... .uleb128 0x2 # (abbrev code) .uleb128 0x2e # (TAG: DW_TAG_subprogram) .byte 0x1 # DW_children_yes ... .uleb128 0x49 # (DW_AT_type) .uleb128 0x13 # (DW_FORM_ref4) ... However, the DW_FORM_ref4 is a CU-relative reference, while using a label for the value will result in a section-relative value. So, if linked in object files contain dwarf info and are placed in the .debug_info section before the compilation units generated from amd64-entry-value-paramref.S, then the referenced type is at 0x108: ... <1><108>: Abbrev Number: 4 (DW_TAG_base_type) <109> DW_AT_byte_size : 4 <10a> DW_AT_encoding : 5 (signed) <10b> DW_AT_name : int ... but the reference will point to a non-existing DIE at 0x1cf: ... <1><f0>: Abbrev Number: 2 (DW_TAG_subprogram) <f1> DW_AT_name : bar <f5> DW_AT_decl_file : 1 <f6> DW_AT_decl_line : 21 <f7> DW_AT_type : <0x1cf> <fb> DW_AT_inline : 1 (inlined) ... which happens to cause a GDB internal error described in PR23270 - "GDB internal error: dwarf2read.c:18656: internal-error: could not find partial DIE 0x1b7 in cache". Fix the invalid DWARF by making the reference value CU-relative: ... - .long DIE45 # DW_AT_type + .long DIE45 - .Ldebug_info0 # DW_AT_type ... Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-05-09 Tom de Vries <tdevries@suse.de> * gdb.arch/amd64-entry-value-paramref.S: Make DW_FORM_ref4 references CU-relative.
2019-05-08Convert gdbtypes.c to type-safe registry APITom Tromey2-5/+10
This changes gdbtypes.c to use the type-safe registry API. gdb/ChangeLog 2019-05-08 Tom Tromey <tom@tromey.com> * gdbtypes.c (objfile_type_data): Change type. (objfile_type, _initialize_gdbtypes): Update.
2019-05-08Convert dwarf2-frame.c to type-safe registry APITom Tromey2-7/+12
This changes dwarf2-frame.c to use the type-safe registry API. gdb/ChangeLog 2019-05-08 Tom Tromey <tom@tromey.com> * dwarf2-frame.c (dwarf2_frame_objfile_data): Change type. (dwarf2_frame_find_fde, dwarf2_build_frame_info) (_initialize_dwarf2_frame): Update.
generated by cgit v1.1 at 2024-12-22 06:13:03 +0000