aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki21-111/+494
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to how the microMIPS opcode table is handled, for both the `match' and `mask' fields, removing special casing for JAL and JALX instructions and their `a' and `i' operand codes throughout, while retaining automatic processing of extendable opcodes in assembly and disassembly. In assembly disallow size enforcement suffixes as appropriate: `.t' for both 32-bit instructions and macros and `.e' for macros only, making macro handling consistent with the microMIPS instruction set. In disassembly fully decode EXTEND prefixes prepended to unsupported instruction encodings (according to the ISA selection) rather than dumping them as hexadecimal data along with the following instruction, removing all special casing for the EXTEND prefix and making its handling rely on its opcode table entry, except where it is considered a part of an extendable instruction. include/ * opcode/mips.h (mips_opcode_32bit_p): New inline function. gas/ * config/tc-mips.c (micromips_insn_length): Use `mips_opcode_32bit_p'. (is_size_valid): Adjust description. (is_size_valid_16): New function. (validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16 operand decoding. (validate_mips16_insn): Remove `a' and `i' operand code special casing, use `mips_opcode_32bit_p' to determine instruction width. (append_insn): Adjust forced MIPS16 instruction size determination. (match_mips16_insn): Likewise. Don't shift the instruction's opcode with the `a' and `i' operand codes. Use `mips_opcode_32bit_p' in operand decoding. (match_mips16_insns): Check for forced instruction size's validity. (mips16_ip): Don't force instruction size in the `noautoextend' mode. * testsuite/gas/mips/mips16-jal-e.d: New test. * testsuite/gas/mips/mips16-jal-t.d: New test. * testsuite/gas/mips/mips16-macro-e.d: New test. * testsuite/gas/mips/mips16-macro-t.d: New test. * testsuite/gas/mips/mips16-jal-t.l: New stderr output. * testsuite/gas/mips/mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16-jal-e.s: New test source. * testsuite/gas/mips/mips16-jal-t.s: New test source. * testsuite/gas/mips/mips16-macro-e.s: New test source. * testsuite/gas/mips/mips16-macro-t.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. opcodes/ * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and `insn' together, with `extend' as the high-order 16 bits. (match_kind): New enum. (print_insn_mips16): Rework for 32-bit instruction matching. Do not dump EXTEND prefixes here. * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. Recode `match' and `mask' fields as 32-bit in absolute "jal" and "jalx" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust test for separate EXTEND prefix disassembly.
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki5-6/+30
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki7-1/+27
Limit the `SD ra, offset(sp)' instruction (I64/SDRASP major/minor opcode) to the MIPS III rather than MIPS I ISA. This is a 64-bit instruction requiring a 64-bit ISA. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). gas/ * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-20MIPS/GAS/testsuite: Correct NewABI test selectionMaciej W. Rozycki2-27/+84
Make sure all tests that require NewABI support are only run with `has_newabi' targets, removing numerous `mips-sgi-irix5' failures. gas/ * testsuite/gas/mips/mips.exp: Limit remaining tests that require NewABI support to `has_newabi' targets.
2016-12-20Update testsuite Makefile with missing dependencies.Cary Coutant3-66/+72
2016-12-20 Cary Coutant <ccoutant@gmail.com> gold/ * testsuite/Makefile.am: Add missing dependencies on gcctestdir/ld or ../ld-new. * testsuite/Makefile.in: Regenerate.
2016-12-19Fix read-beyond-end-of-buffer error in script parsing.Cary Coutant2-14/+26
2016-12-19 Cary Coutant <ccoutant@gmail.com> gold/ PR gold/20949 * script.cc (Lex::get_token): Don't look ahead past NUL characters.
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2-22/+27
sc is a misnomer, because they aren't inherently sc. * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to "*.aqrl".
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2-22/+27
This fixes https://github.com/riscv/riscv-binutils-gdb/issues/36. * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as INSN_ALIAS.
2016-12-20Add canonical JALR for RISC-VAndrew Waterman2-0/+8
jalr rd,offset(rs1) rather than jalr rd,rs1,offset This matches the format of other instructions. * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" format.
2016-12-20Don't define RISC-V .p2alignAndrew Waterman3-42/+82
* config/tc-riscv.c (riscv_pseudo_table): Remove "align", "p2align", and "balign". (s_align): Remove. (riscv_handle_align): New function. (riscv_frag_align_code): Likewise. (riscv_make_nops): Likewise. * config/tc-riscv.h (MAX_MEM_FOR_RS_ALIGN_CODE): Change to 7. (HANDLE_ALIGN): Define. (md_do_align): Define. (riscv_handle_align): Declare. (riscv_frag_align_code): Likewise.
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman13-131/+186
We've decided to standardize on two flags for RISC-V: "-march" sets the target architecture (which determines which instructions can be generated), and "-mabi" sets the target ABI. We needed to rework this because the old flag set didn't support soft-float or single-float ABIs, and didn't support an x32-style ABI on RISC-V. Additionally, we've changed the behavior of the -march flag: it's now a lot stricter and only parses things we can actually understand. Additionally, it's now lowercase-only: the rationale is that while the RISC-V ISA manual specifies that ISA strings are case-insensitive, in Linux-land things are usually case-sensitive. Since this flag can be used to determine library paths, we didn't want to bake some case-insensitivity in there that would case trouble later. This patch implements these two new flags and removes the old flags that could conflict with these. There wasn't a RISC-V release before, so we want to just support a clean flag set. include/ * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define. (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define. (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define. (EF_RISCV_FLOAT_ABI_QUAD): Define. bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT. binutils/ * readelf.c (get_machine_flags): Use EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of EF_RISCV_{SOFT,HARD}_FLOAT. gas/ * config/tc-riscv.h (xlen): Delete. * config/tc-riscv.c (xlen): Make static. (abi_xlen): New variable. (options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC} with OPTION_MABI. (md_longopts): Likewise. (md_parse_option): Likewise. (riscv_elf_final_processing): Likewise. * doc/as.texinfo (Target RISC-V options): Likewise. * doc/c-riscv.texi (OPTIONS): Likewise. * config/tc-riscv.c (float_mode): Removed. (float_abi): New type, specifies the floating-point ABI. (riscv_set_abi): New function. (riscv_add_subset): Only allow lower-case ISA names and require them to start with "rv". (riscv_after_parse_args): Likewise. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's XLEN when none is provided.
2016-12-20Fix an integer overflow in RISC-V relocation handlingAndrew Waterman2-2/+7
* elfnn-riscv.c (bfd_riscv_get_max_alignment): Return bfd_vma instead of unsigned int.
2016-12-20Rework RISC-V relocationsAndrew Waterman11-71/+472
Before this commit we didn't cleanly support CFI directives because the internal offsets used to get relaxed which broke them. This patch significantly reworks how we handle linker relaxations: * DWARF is now properly supported * There is a ".option norelax" to disable relaxations, for when users write assembly that can't be relaxed (if it's to be later patched up, for example). * There is an additional _RELAX relocation that specifies when previous relocations can be relaxed. We're in the process of documenting the RISC-V ELF ABI, which will include documentation of our relocations https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md but we expect that this relocation set will remain ABI compatible in the future (ie, it's safe to release). Thanks to Kuan-Lin Chen for figuring out how to correctly relax the debug info! include/ * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32. bfd/ * reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation. (BFD_RELOC_RISCV_TPREL_S): Likewise. (BFD_RELOC_RISCV_RELAX): Likewise. (BFD_RELOC_RISCV_CFA): Likewise. (BFD_RELOC_RISCV_SUB6): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET16): Likewise. (BFD_RELOC_RISCV_SET32): Likewise. * elfnn-riscv.c (perform_relocation): Handle the new relocations. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Likewise. (howto_table): Likewise. (riscv_reloc_map): Likewise. (relax_func_t): New type. (_bfd_riscv_relax_call): Add reserve_size argument, which controls the maximal offset pessimism. Correct type of max_alignment. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Compute the required reserve size when relocating and use it to when calling relax_func. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ * config/tc-riscv.c (riscv_set_options): Add relax. (riscv_opts): Likewise. (s_riscv_option): Add relax and norelax. (riscv_apply_const_reloc): New function. (append_insn): Move constant relocation handling to riscv_apply_const_reloc. (md_pcrel_from): Likewise. (parse_relocation): Skip BFD_RELOC_UNUSED. (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6, BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA. (md_apply_fix): Likewise. (riscv_pre_output_hook): New function. * config/tc-riscv.h (md_pre_output_hook): Define. (riscv_pre_output_hook): Declare. (DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-20Formatting changes for RISC-VAndrew Waterman7-59/+68
This is a mixed bag of format changes: * Replacing constants with macros (0xffffffff with MINUS_ONE, for example). There's one technically functional change in here (some MINUS_ONEs are changed to 0), but it only changes the behavior of an otherwise-unused field. * Using 0 instead of 0x0 in the relocation table. * There were some missing spaces before parens, the spaces have been added. * A handful of comments are now more descriptive. * A bunch of whitespace-only changes, mostly alignment and brace newlines. bfd/ * elfnn-riscv.c: Formatting and comment fixes throughout. * elfxx-riscv.c: Likewise. (howto_table): Change the src_mask field from MINUS_ONE to 0 for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64. opcodes/ * riscv-opc.c: Formatting fixes. gas/ * config/tc-riscv.c: Formatting and comment fixes throughout.
2016-12-20Improve RISC-V LD error messagePalmer Dabbelt2-2/+8
I recently ran into this error message and found it's not helpful: it just tells me some temporary file can't be linked. This slightly improved one at least tells me it's because of an elf32/elf64 conflict. * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Improve error message when linking elf32 and elf64.
2016-12-20Add opcodes RISC-V dependenciesAlan Modra4-0/+14
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2016-12-19Fix problem where linker does not place .note sections according to script.Cary Coutant5-30/+61
gold/ PR gold/14676 PR gold/20983 * layout.h (Layout::choose_output_section): Add match_input_spec parameter. Adjust all callers. * layout.cc (Layout::choose_output_section): Likewise. Pass match_input_spec to Script_sections::output_section_name(). (Layout::create_note): Pass true for match_input_spec. * script-sections.h (Script_sections::output_section_name): Add match_input_spec parameter. * script-sections.cc (Sections_element::output_section_name): Likewise. (Output_section_definition::output_section_name): Likewise. (Script_sections::output_section_name): Likewise.
2016-12-20Automatic date update in version.inGDB Administrator1-1/+1
2016-12-19Fix an internal error in the constructor of Target_arm.Igor Kudrin6-28/+55
gold/ * arm.cc (Target_arm::Target_arm): Move initialization code ... (Target_arm::do_select_as_default_target): ... to here. * testsuite/Makefile.am (arm_target_lazy_init): New test case. * testsuite/Makefile.in: Regenerate. * testsuite/arm_target_lazy_init.s: New source file. * testsuite/arm_target_lazy_init.t: New linker script.
2016-12-19Fix forced allocation of common (-d) during -r links.Cary Coutant5-4/+81
If the .bss section has other data in it besides common allocations, gold was subtracting the wrong section start address from the symbol value. gold/ PR gold/20976 * symtab.cc (Symbol_table::sized_write_globals): Use address of output section, not input section. * testsuite/Makefile.am (pr20976): New test case. * testsuite/Makefile.in: Regenerate. * testsuite/pr20976.c: New source file.
2016-12-19Clean up gdb.gdb/selftest.expYao Qi2-293/+6
I recently see the test fails like this, (gdb) PASS: gdb.gdb/selftest.exp: step over argv initialization list^M 487 std::vector<struct cmdarg> cmdarg_vec;^M (gdb) FAIL: gdb.gdb/selftest.exp: unknown source line (after step over argv initialization) step^M std::vector<cmdarg, std::allocator<cmdarg> >::vector (this=0x7fffffffdc10) at ../../binutils-gdb/gdb/main.c:487^M 487 std::vector<struct cmdarg> cmdarg_vec;^M (gdb) FAIL: gdb.gdb/selftest.exp: step into xmalloc call These fails are caused by using std::vector in commit f60ee22ea1d62f7004511ec65a3ad76890032d88. selttest.exp should match the source code of GDB. It is a maintenance pain, so this patch removes do_steps_and_nexts. gdb/testsuite: 2016-12-19 Yao Qi <yao.qi@linaro.org> * gdb.gdb/selftest.exp (do_steps_and_nexts): Remove. (test_with_self): Don't call do_steps_and_nexts, and remove code about stepping into xmalloc.
2016-12-19bfd/elf32-arm.c: Rename 'popcount' to 'elf32_arm_popcount'Christian Groessler2-7/+13
bfd/elf32_arm.c contains a function 'popcount' which conflicts with a function of the same name in NetBSD's libc. This change also changes popcount's 'sum' variable to signed since the function returns a signed integer. bfd/ * elf32-arm.c (elf32_arm_popcount): Rename from 'popcount'. Make 'sum' local variable signed.
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki2-1/+6
Correct commit 640c0ccdc980 ("some objdump -M options, better reg dumps"), <https://sourceware.org/ml/binutils/2002-12/msg00706.html>, and only execute code setting up disassembler options based on ELF file structures if SYMTAB_AVAILABLE is set. opcodes/ * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]: Only examine ELF file structures here.
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki2-2/+14
Complement commit 5e7fc731f80e ("MIPS/opcodes: Also set disassembler's ASE flags from ELF structures") and fix an `--enable-targets=all' GDB build regression on 32-bit hosts where the MIPS target is a secondary: ../opcodes/libopcodes.a(mips-dis.o): In function `set_default_mips_dis_options': mips-dis.c:(.text+0x906): undefined reference to `bfd_mips_elf_get_abiflags' collect2: error: ld returned 1 exit status make[2]: *** [gdb] Error 1 by avoiding making a call to the `bfd_mips_elf_get_abiflags' function, which is not available, because there is no MIPS/ELF BFD included in 32-bit BFD builds. This call is only made from a conditional code block guarded by a check against `bfd_target_elf_flavour', which is dead in such a configuration, however cannot be optimized away by the compiler. Also some other MIPS BFDs may be available, such as a.out, ECOFF or PE, so the disassembler has to remain functional. opcodes/ * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call `bfd_mips_elf_get_abiflags' here.
2016-12-19Automatic date update in version.inGDB Administrator1-1/+1
2016-12-18Automatic date update in version.inGDB Administrator1-1/+1
2016-12-17Automatic date update in version.inGDB Administrator1-1/+1
2016-12-16Darwin: Fix gdb compilation.Bernhard Heckel2-3/+6
Due to changes introduced by commit 4d01a485d29732b19743e8b138897f3509e071b0 ('struct expression *' -> gdb::unique_xmalloc_ptr<expression>) compilation is broken on Darwin. ../gdb/darwin-nat-info.c:733:8: error: assigning to 'struct expression *' from incompatible type 'expression_up' (aka 'std::__1::unique_ptr<expression, gdb::xfree_deleter<expression> >') expr = parse_expression (exp); Beside compilation, memory leak was solved as 'make_clean_up' was not called in previous version. 2016-12-16 Bernhard Heckel <bernhard.heckel@intel.com> gdb/Changelog: * darwin-nat-info.c (info_mach_region_command): Use expression_up.
2016-12-16Fix compile time warning building arm-dis.cNick Clifton2-2/+7
2016-12-16Implement and document --gc-keep-exportedfincs8-1/+40
include/ * bfdlink.h (struct bfd_link_info): Add gc_keep_exported. bfd/ * elflink.c (bfd_elf_gc_mark_dynamic_ref_symbol): Add handling for info->gc_keep_exported. (bfd_elf_gc_sections): Likewise. ld/ * ld.texinfo: Document --gc-keep-exported. * ldlex.h (enum option_values): Add OPTION_GC_KEEP_EXPORTED. * lexsup.c (parse_args): Add handling for --gc-keep-exported.
2016-12-16Automatic date update in version.inGDB Administrator1-1/+1
2016-12-15Linking non-ELF file broken by PR20908 fixAlan Modra2-28/+30
PR ld/20968 PR ld/20908 * elflink.c (bfd_elf_final_link): Revert 2016-12-02 change. Move reloc counting code later after ELF flavour test.
2016-12-15Automatic date update in version.inGDB Administrator1-1/+1
2016-12-14MAINTAINERS: Add myself as a MIPS maintainerMaciej W. Rozycki2-0/+6
* MAINTAINERS (Maintainers for particular sims): Add myself as a MIPS maintainer.
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki15-3/+191
Respect any ASE flags recorded in ELF file structures for the purpose of selecting instructions to be disassembled, preventing code from being hex-dumped even though having been clearly indicated as valid at the assembly time. Use date from the MIPS ABI flags structure if present, and otherwise there may be an MDMX ASE flag set in the ELF file header. For backwards compatibility only set extra flags and do not clear any, preserving all previously set by the architecture selected to be disassembled for. include/ * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct typedef as `elf_internal_abiflags_v0'. bfd/ * bfd-in.h (elf_internal_abiflags_v0): New struct declaration. (bfd_mips_elf_get_abiflags): New prototype. * elfxx-mips.c (bfd_mips_elf_get_abiflags): New function. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c (mips_convert_abiflags_ases): New function. (set_default_mips_dis_options): Also infer ASE flags from ELF file structures. binutils/ * testsuite/binutils-all/mips/mips-ase-1.d: New test. * testsuite/binutils-all/mips/mips-ase-2.d: New test. * testsuite/binutils-all/mips/mips-ase-3.d: New test. * testsuite/binutils-all/mips/mips-ase-1.s: New test source. * testsuite/binutils-all/mips/mips-ase-2.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-14MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki2-13/+18
Move ELF file header flag interpretation code, used to set disassembler options, beyond architecture setup. No functional change as the effects of both code sections are disjoint from each other, but this provides for a further expansion of ELF file header flag interpretation. opcodes/ * mips-dis.c (set_default_mips_dis_options): Reorder ELF file header flag interpretation code.
2016-12-14MIPS16/GAS: Fix assertion failures with relocations on 16-bit instructionsMaciej W. Rozycki8-3/+50
Complement commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support)" and report an assembly error when a relocation is required for an instruction, currently a branch only, that has been forced to use its unextended encoding, either with the use of an explicit `.t' mnemonic suffix, or by means of `.set noautoextend' being active, fixing an assertion failure currently caused instead. gas/ * config/tc-mips.c (md_convert_frag): Report an error instead of asserting on `ext'. * testsuite/gas/mips/mips16-branch-unextended-1.d: New test. * testsuite/gas/mips/mips16-branch-unextended-2.d: New test. * testsuite/gas/mips/mips16-branch-unextended-1.s: New test source. * testsuite/gas/mips/mips16-branch-unextended-2.s: New test. * testsuite/gas/mips/mips16-branch-unextended.l: New stderr output. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-14MIPS16: Fix SP-relative SD instruction annotationMaciej W. Rozycki6-2/+58
Fix the annotation of SP-relative SD instructions incorrectly marked as reading from the PC rather than SP, which in turn prevented their 16-bit forms from being scheduled into jump delay slots. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in `pinfo2' with SP-relative "sd" entries. gas/ * testsuite/gas/mips/mips16-sprel-swap.d: New test. * testsuite/gas/mips/mips16-sprel-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2016-12-14MIPS16/opcodes: Fix and clarify MIPS16e commentaryMaciej W. Rozycki2-4/+9
Correct the note about JALRC/JRC being compact jumps rather than branches, and add a reference from where the remaining MIPS16e additions live and the jumps used to be too, complementing commit ceb94aa50d68 ("Update insn_mo when converting to a MIPS16e compact jump"), <https://sourceware.org/ml/binutils/2011-06/msg00369.html>. opcodes/ * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e compact jumps.
2016-12-14ld: aarch64: fix TLS relaxation where TCB_SIZE is usedYury Norov6-5/+56
TCB_SIZE is 2*sizeof(void *), which is 0x10 for lp64, and 0x8 for ilp32. During relaxation, ld goes to do a replace: bl __tls_get_addr => add R0, R0, TCB_SIZE But actual implementation is: bfd_putl32 (0x91004000, contents + rel->r_offset + 4); Which is equivalent of add x0, x0, 0x10. This is wrong for ilp32. The possible fix for it is: bfd_putl32 (0x91000000 | (TCB_SIZE<<10), contents + rel->r_offset + 4); But ilp32 also needs w-registers, so it's simpler to put proper instruction in #if/#else condition. There are 2 such relaxations in elfNN_aarch64_tls_relax(), and so 2 new tests added for ilp32 mode to test it. Yury * bfd/elfnn-aarch64.c: fix TLS relaxations for ilp32 where TCB_SIZE is used. * ld/testsuite/ld-aarch64/aarch64-elf.exp: Add tests for the case. * ld/testsuite/ld-aarch64/tls-relax-ld-le-small-ilp32.d: New file. * ld/testsuite/ld-aarch64/tls-relax-ld-le-tiny-ilp32.d: New file. Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
2016-12-14Revert "bfd: aarch64: fix word and arrdess size declaration in ilp32 mode"Yury Norov1-4/+4
This reverts commit a02c3512655cc2c8ad68e4b656959b7d284acc7d.
2016-12-14Revert "ld: aarch64: fix TLS relaxation where TCB_SIZE is used"Yury Norov4-44/+3
This reverts commit 6650f7bd18f8161b9f666d3e65a6346e23a9d85f.
2016-12-14bfd: aarch64: fix word and arrdess size declaration in ilp32 modeYury Norov1-4/+4
2016-12-14ld: aarch64: fix TLS relaxation where TCB_SIZE is usedYury Norov4-3/+44
TCB_SIZE is 2*sizeof(void *), which is 0x10 for lp64, and 0x8 for ilp32. During relaxation, ld goes to do a replace: bl __tls_get_addr => add R0, R0, TCB_SIZE But actual implementation is: bfd_putl32 (0x91004000, contents + rel->r_offset + 4); Which is equivalent of add x0, x0, 0x10. This is wrong for ilp32. The possible fix for it is: bfd_putl32 (0x91000000 | (TCB_SIZE<<10), contents + rel->r_offset + 4); But ilp32 also needs w-registers, so it's simpler to put proper instruction in #if/#else condition. THere are 2 such relaxations in elfNN_aarch64_tls_relax(), and so 2 new tests added for ilp32 mode to test it. Yury
2016-12-14Automatic date update in version.inGDB Administrator1-1/+1
2016-12-13Add --orphan-handling option.Cary Coutant4-4/+80
gold/ PR gold/20749 * options.h (--orphan-handling): New option. (General_options::Orphan_handling): New enum. (General_options::orphan_handling_enum): New method. (General_options::set_orphan_handling_enum): New method. (General_options::orphan_handling_enum_): New data member. * options.cc (General_options::General_options): Initialize new member. (General_options::finalize): Convert --orphan-handling argument to enum. * script-sections.cc (Script_sections::output_section_name): Check it.
2016-12-13Do not use linker script to place static relocation sections.Cary Coutant3-20/+32
gold/ PR gold/20522 * layout.cc (Layout::choose_output_section): Add is_reloc parameter. Adjust all callers. Do not use linker script for is_reloc sections. (Layout::layout_reloc): Pass is_reloc == true. * layout.h (Layout::choose_output_section): Add is_reloc parameter.
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li12-151/+174
The internal CN register representation for coprocessor fields used in aarch64 sys, sysl instructions are removed in this patch. After the change, those fields are represented as immediate. Related checks are added as well. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range qualifier. (operand_general_constraint_met_p): Remove case for CP_REG. (aarch64_print_operand): Print CRn, CRm operand using imm field. * aarch64-tbl.h (QL_SYS): Use CR qualifier. (QL_SYSL): Likewise. (aarch64_opcode_table): Change CRn, CRm operand class and type. * aarch64-opc-2.c : Regenerate. * aarch64-asm-2.c : Likewise. * aarch64-dis-2.c : Likewise. include/ * opcode/aarch64.h (aarch64_operand_class): Remove AARCH64_OPND_CLASS_CP_REG. (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn, AARCH64_OPND_Cm to AARCH64_OPND_CRm. (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier. gas/ * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register. (get_reg_expected_msg): Remove CN register case. (parse_operands): rewrite parser for CRn, CRm operand. (reg_names): Remove CN register. * testsuite/gas/aarch64/diagnostic.s: Add a new test case. * testsuite/gas/aarch64/diagnostic.l: Adjust error message.
2016-12-13PE linker script improvements.Nick Clifton2-3/+10
PR ld/19254 * scripttempl/pe.sc (.fini): KEEP this section. (.gcc_except_table): Likewise. (.pdata): Also accept .pdata*.
2016-12-13Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson7-45/+309
sim/aarch64 * simulator.c (NEG, POS): Move before set_flags_for_add64. (set_flags_for_add64): Replace with a modified copy of set_flags_for_sub64. sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass to start. (fail): Move .Lfail to start. Return 1 instead of 0. (start): Moved .Lpass and .Lfail to here. * adds.s: New. * fstur.s: New. * tbnz.s: New.
generated by cgit v1.1 at 2024-12-26 08:14:14 +0000