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1996-09-03Fix typpppoJeff Law1-1/+1
1996-09-03 * interp.c: OP should be an array of 32bit operands!Jeff Law4-78/+248
(v850_callback): Declare. (do_format_5): Fix extraction of OP[0]. (sim_size): Remove debugging printf. (sim_set_callbacks): Do something useful. (sim_stop_reason): Gross hacks to get c-torture running. * simops.c: Simplify code for computing targets of bCC insns. Invert 's' bit if 'ov' bit is set for some instructions. Fix 'cy' bit handling for numerous instructions. Make the simulator stop when a halt instruction is encountered. Very crude support for emulated syscalls (trap 0). * v850_sim.h: Include "callback.h" and declare v850_callback. Items in the operand array are 32bits. Fixes & syscall stuff.
1996-09-03 * elf32-v850.c (bfd_elf3_v850_reloc): New function forJeff Law1-2/+27
handling V850 specific relocs. (elf_v850_howto_table): Use the new function for some relocations. Twiddle masks & shifts for some relocs. Set partial_inplace where needed. Fixing more stuff.
1996-09-02Remove reloc.c from v850_files.Mark Alexander1-1/+1
1996-09-02whoops--typoIan Lance Taylor1-0/+27
1996-09-02file was really removed a long time agoIan Lance Taylor2-32/+0
1996-09-01 * .Sanitize: Remove reloc.c from v850_files.Mark Alexander1-0/+6
1996-09-01 * rs6000-core.c (rs6000coff_core_file_matches_executable_p):Ian Lance Taylor1-0/+6
Rewrite to use BFD file read routines and to avoid using a fixed length for the file name.
1996-08-31 * config/tc-v850.c (md_assemble): Compute size of the instrctionJeff Law1-1/+6
from the opcode.
1996-08-31 * v850-dis.c (disassemble): Handle insertion of ',', '[' andJeff Law2-80/+89
']' characters into the output stream. * v850-opc.c (v850_opcodes: Remove size field from all opcodes. Add "memop" field to all opcodes (for the disassembler). Reorder opcodes so that "nop" comes before "mov" and "jr" comes before "jarl". Should give us a functional disassembler.
1996-08-31 * v850-dis.c (print_insn_v850): Properly handle disassemblingJeff Law2-2/+21
a two byte insn at the end of a memory region when the memory region's size is only two byte aligned.
1996-08-31 * v850-dis.c (v850_cc_names): Fix stupid thinkos.Jeff Law2-2/+3
1996-08-31 * v850-dis.c (v850_reg_names): Define.Jeff Law3-3/+62
(v850_sreg_names, v850_cc_names): Likewise. (disassemble): Very rough cut at printing operands (unformatted). One step at a time. * v850-opc.c (BOP_MASK): Fix. (v850_opcodes): Fix mask for jarl and jr. Bugs exposed by disassembler testing.
1996-08-31 * dis-asm.h (print_insn_v850): Declare.Jeff Law1-0/+28
1996-08-31 * v850-dis.c: New file. Skeleton for disassembler support.Jeff Law1-0/+78
* Makefile.in Remove v850 references, they're not needed here and they weren't being sanitized away. * configure.in: Add v850-dis.o when building v850 toolchains. * configure: Rebuilt. * disassemble.c (disassembler): Call v850 disassembler.
1996-08-31 * v850-dis.c: New file. Skeleton for disassembler support.Jeff Law2-2/+9
* Makefile.in Remove v850 references, they're not needed here and they weren't being sanitized away. * configure.in: Add v850-dis.o when building v850 toolchains. * configure: Rebuilt. * disassemble.c (disassembler): Call v850 disassembler. Skeleton support for V850 disassembler.
1996-08-31 * config/tc-v850.c (md_apply_fix3): Do simple byte, short andJeff Law2-0/+14
word fixups too. Fixes "difference between forward references".
1996-08-31 * v850-opc.c (insert_d8_7, extract_d8_7): New functions.Jeff Law2-19/+90
(insert_d8_6, extract_d8_6): New functions. (v850_operands): Rename D7S to D7; operand for D7 is unsigned. Rename D8 to D8_7, use {insert,extract}_d8_7 routines. Add D8_6. (IF4A, IF4B): Use "D7" instead of "D7S". (IF4C, IF4D): Use "D8_7" instead of "D8". (IF4E, IF4F): New. Use "D8_6". (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. So we can assemble sst/sld instructions correctly.
1996-08-31 * v850-opc.c (insert_d16_15, extract_d16_15): New functions.Jeff Law2-11/+52
(v850_operands): Change D16 to D16_15, use special insert/extract routines. New new D16 that uses the generic insert/extract code. (IF7A, IF7B): Use D16_15. (IF7C, IF7D): New. Use D16. (v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
1996-08-31 * v850-opc.c (insert_d9, insert_d22): Slightly improve errorJeff Law2-1/+10
message. Issue an error if the branch offset is odd.
1996-08-31 * elf32-v850.c (enum reloc_type): Add R_V850_{32,16,8}.Jeff Law2-0/+58
(elf_v850_howto_table): Add support for R_V850_{32,16,8}. (v850_reloc_map): Add translation from BFD_RELOC_{32,16,8} to R_V850_{32,16,8}. So we don't get "reloc XXX not supported" messages anymore.
1996-08-31 * v850-opc.c: Add notes about needing special insert/extractJeff Law2-0/+9
for all the load/store insns, except "ld.b" and "st.b". So we don't forget!
1996-08-31 * v850-opc.c (insert_d22, extract_d22): New functions.Jeff Law2-2/+33
(v850_operands): Use insert_d22 and extract_d22 for D22 operands. (insert_d9): Fix range check.
1996-08-31 * gas/v850/basic.exp (do_branch): Check offsets in branch insns.Jeff Law2-32/+37
(do_jumps): Likewise. Now that we can resolve known branch targets.
1996-08-31 * config/tc-v850.c (md_apply_fix3): Use little endian get/putJeff Law2-4/+28
routines to fetch/store the updated instruction from/to memory. (v850_insert_operand): If the operand has a specialized insert routine, call it. Getting fixups closer. At least br <target> works now.
1996-08-31 * emulparms/v850.sh: Entry symbol is "_start", tweakJeff Law2-0/+21
ctor/dtor support.
1996-08-31Opps. Forgot to commit this a few days ago.Jeff Law1-0/+35
1996-08-31* config/tc-v850.c (reg_name_search): Align calling convention toJ.T. Conklin2-133/+195
be like identical function found in tc-ppc.c. (get_reloc): Removed. (v850_reloc_prefix): New function, parse lo(), hi() and hi0(). (md_assemble): emit fixups. (md_pcrel_from): renamed from md_pcrel_from_section, emit proper displacement. (md_apply_fix3): handle fixups/relocs. * config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
1996-08-31* elf32-v850.c (reloc_type): Add R_V850_HI16_S.J.T. Conklin3-1/+209
(elf_v850_howto_table): Add info for HI16_S reloc. (v850_reloc_map): Add HI_16_S reloc. * reloc.c: Define BFD_RELOC_V850_* relocs.
1996-08-31* v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flagJ.T. Conklin2-2/+7
and set bits field to D9 and D22 operands.
1996-08-30 * configure.tgt (sh-*-elf*): New target.Ian Lance Taylor4-0/+62
* emulparams/shelf.sh: New file. * emulparams/shlelf.sh: New file. * Makefile.in (ALL_EMULATIONS): Add eshelf.o and eshlelf.o. (eshelf.c, eshlelf.c): New targets. * scripttempl/elf.sc: If EMBEDDED is defined, then don't add SIZEOF_HEADERS to TEXT_START_ADDR. Expand CTOR_START and CTOR_END around .ctors, and DTOR_START and DTOR_END around .dtors. Expand OTHER_RELOCATING_SECTIONS if RELOCATING.
1996-08-30 Add SH ELF support.Ian Lance Taylor1-0/+48
* configure.in (sh-*-elf*): New target. * config/tc-sh.h (TARGET_ARCH): Define. (WORKING_DOT_WORD): Define. (TC_COFF_FIX2RTYPE): Only define if OBJ_COFF. (BFD_ARCH, COFF_MAGIC, TC_COUNT_RELOC): Likewise. (TC_RELOC_MANGLE, tc_coff_symbol_emit_hook): Likewise. (DO_NOT_STRIP, NEED_FX_R_TYPE, TC_KEEP_FX_OFFSET): Likewise. (TC_COFF_SIZEMACHDEP, tc_frob_file): Likewise. (SUB_SEGMENT_ALIGN): Likewise. (RELOC_32): Don't define. (tc_frob_file_before_adjust): Define if BFD_ASSEMBLER. (target_big_endian): Declare if OBJ_ELF. (TARGET_FORMAT): Define if OBJ_ELF. * config/tc-sh.c: Use BFD reloc codes instead of SH COFF reloc numbers throughout. (tc_crawl_symbol_chain): Only define if OBJ_COFF. (tc_headers_hook, tc_coff_sizemachdep): Likewise. (struct sh_count_relocs): Define. (sh_count_relocs): New static function, broken out of sh_frob_file. Add BFD_ASSEMBLER code. (sh_frob_section): Likewise. (sh_frob_file): Call sh_frob_section. (md_convert_frag): If BFD_ASSEMBLER, change type of headers, and call section_symbol rather than seg_info (seg)->dot. (md_section_align): Add OBJ_ELF version. (SWITCH_TABLE_CONS): Define. (SWITCH_TABLE): Use SWITCH_TABLE_CONS. (md_apply_fix): Change parameter types if BFD_ASSEMBLER. Only handle fx_r_type == 0 if not BFD_ASSEMBLER. Return 0 if BFD_ASSEMBLER. (struct reloc_map): Define if not BFD_ASSEMBLER. (coff_reloc_map): Likewise. (sh_coff_reloc_mangle): Use coff_reloc_map to convert fx_r_type. (tc_gen_reloc): New function if BFD_ASSEMBLER. * write.c (write_relocs): Ifdef out fx_where test which triggers inappropriately for SH ELF. (write_object_file): Call tc_frob_file_before_adjust and obj_frob_file_before_adjust if they are defined. * write.c (write_object_file): Use BFD_RELOC_16, not BFD_RELOC_NONE, when calling fix_new_exp for a broken word.
1996-08-30 Add SH ELF support.Ian Lance Taylor6-27/+188
* elf32-sh.c: New file. * elf.c (prep_headers): Handle bfd_arch_sh. * elfcode.h (write_relocs): Handle absolute symbol. * elf-bfd.h (_bfd_elf32_link_read_relocs): Declare. (_bfd_elf64_link_read_relocs): Declare. * elflink.h (NAME(_bfd_elf,link_read_relocs)): Rename from elf_link_read_relocs. Make globally visible. Change all callers. (elf_link_input_bfd): Get external symbols from cache in symtab_hdr->contents. Get contents from cache in elf_section_data. * elfxx-target.h (bfD_elfNN_bfd_relax_section): Only define if not already defined. * reloc.c: Define BFD_RELOC_SH_* relocs. * libbfd-in.h (_bfd_sh_align_load_span): Declare. * coff-sh.c (sh_insns_conflict): Fix a return value. (_bfd_sh_align_load_span): New globally visible function, broken out of sh_align_load. (sh_align_load): Call _bfd_sh_align_load_span. (sh_swap_insns): Change relocs parameter to PTR. * bfd-in2.h, libbfd.h: Rebuild. * targets.c (bfd_elf32_sh_vec): Declare. (bfd_elf32_shl_vec): Declare. * config.bfd (sh-*-elf*): New target. * configure.in (bfd_elf32_sh_vec): New target vector. (bfd_elf32_shl_vec): New target vector. * configure: Rebuild. * Makefile.in: Rebuild dependencies. (BFD32_BACKENDS): Add elf32-sh.o. (BFD32_BACKENDS_CFILES): Add elf32-sh.c. * elf.c (map_sections_to_segments): Check that LMA does not skip a page before checking D_PAGED.
1996-08-30 * simops.c: Fix "not1" and "set1".Jeff Law2-2/+4
1996-08-30Fri Aug 30 14:47:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-0/+7
* config/tc-d10v.c (find_opcode): Fix problem with calculating branch sizes in across sections.
1996-08-30 * simops.c: Don't forget to initialize temp forJeff Law2-0/+5
"ld.h" and "ld.w"
1996-08-30 * gas/v850/misc.s: Tweak register numbers for better testing.Jeff Law2-2/+5
* gas/v850/basic.exp (misc_tests): Corresponding changes.
1996-08-30 * v850-opc.c (v850_operands): Define SR2 operand.Jeff Law2-1/+9
(v850_opcodes): "ldsr" uses R1,SR2. ldsr is kinda weird.
1996-08-30 * interp.c: Remove various debugging printfs.Jeff Law2-15/+2
1996-08-30 * simops.c: Fix satadd, satsub boundary case handling.Jeff Law2-5/+7
1996-08-30 * interp.c (hash): Fix.Jeff Law3-18/+80
* interp.c (do_format_8): Get operands correctly and call the target function. * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
1996-08-30 * gmon.h: Replace #elif with #else/#endif.Ian Lance Taylor2-1/+7
1996-08-30 * ihex.c (ihex_scan): Removed unnecessary extbase variable.Ian Lance Taylor2-28/+47
(ihex_write_object_contents): Remove extbase; always use segbase instead.
1996-08-30Fri Aug 30 15:07:14 1996 James G. Smith <jsmith@cygnus.co.uk>Jackie Smith Cashion1-18/+104
* remote-mips.c: Provide support for CAIRO target board. (cairo_open, cairo_ops): Added. (mips_monitor_type): MON_CAIRO Added. (mips_enter_debug, mips_exit_debug, mips_initialize, mips_fetch_registers, common_breakpoint, mips_load, _initialize_remote_mips): Updated. Add simple support for NEC CAIRO Vr4300 development board.
1996-08-30 * config/tc-850.c (md_assemble): Handle hi() correctly. HandleJeff Law2-5/+48
hi0() too. Bugfix.
1996-08-30 * gas/v850/hilo.s: New testfile.Jeff Law4-1/+45
* gas/v850/basic.exp: Run hilo tests.
1996-08-30 * interp.c (do_format_4): Get operands correctly andJeff Law3-0/+61
call the target function. * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b", "sst.h", and "sst.w".
1996-08-30 * v850_sim.h: The V850 doesn't have split I&D spaces. ChangeJeff Law3-121/+181
accordingly. Remove many unused definitions. * interp.c: The V850 doesn't have split I&D spaces. Change accordingly. (get_longlong, get_longword, get_word): Deleted. (write_longlong, write_longword, write_word): Deleted. (get_operands): Deleted. (get_byte, get_half, get_word): New functions. (put_byte, put_half, put_word): New functions. * simops.c: Remove unused functions. Rough cut at "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
1996-08-30 * v850_sim.h (struct _state): Remove "psw" field. AddJeff Law3-78/+89
"sregs" field. (PSW): Remove bogus definition. * simops.c: Change condition code handling to use the psw register within the sregs array. Handle "ldsr" and "stsr".
1996-08-30 * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".Jeff Law2-25/+173
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