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2021-04-14PR27631, ubsan: elf32-metag.c:1550:10Alan Modra2-2/+8
PR 27631 * elf32-metag.c (elf_metag_relocate_section): Don't use &hh->elf when hh might be NULL, test for NULL first.
2021-04-14PR27630, ubsan: elf32-arm.c:6587:20Alan Modra2-2/+9
PR 27630 * elf32-arm.c (elf32_arm_size_stubs): Don't use &hash->root when hash might be NULL, cast instead.
2021-04-14PR27716, build failure for msdosdjgpp: PATH_MAX undeclaredAlan Modra11-104/+132
We shouldn't be using arbitrary limits like PATH_MAX in GNU programs. This patch also fixes some memory leaks in readelf when processing separate debug info. PR 27716 binutils/ * objdump.c (show_line): Don't limit paths to PATH_MAX. * readelf.c (struct filedata): Change program_interpreter from a char array to a char pointer. (process_program_headers): Sanity check PT_INTERP p_filesz. Malloc program_interpreter using p_filesz and read directly from file. (process_dynamic_section): Check program_interpreter is non-NULL. (free_filedata): New function, split out from.. (process_object): ..here. (close_debug_file): Call free_filedata. * sysdep.h: Don't include sys/param.h. (PATH_MAX): Don't define. * configure.ac: Don't check for sys/param.h. * configure: Regenerate. gprof/ * gprof.h (PATH_MAX): Don't define. * corefile.c (core_create_line_syms): Don't use PATH_MAX for initial file name size. * source.c (annotate_source): Malloc file name buffer. Always trim off "-ann" when dos 8.3 annotate file matches original. * utils.c (print_name_only): Malloc file name buffer.
2021-04-14Re: PR27723, Internal error in select_cie_for_fdeAlan Modra2-68/+67
Let's make sure what we allow in the CIE initial instructions and what select_cie_for_fde compares for a match is always in sync. Also correct the previous patch that allowed DW_CFA_GNU_window_save to be part of the CIE initial instructions, which was likely a mistake. PR 27723 * dw2gencfi.c (initial_cie_insn): New function, extracted from.. (select_cie_for_fde): ..here. Simplify.
2021-04-14Automatic date update in version.inGDB Administrator1-1/+1
2021-04-14PR27723, Internal error in select_cie_for_fdeAlan Modra2-0/+10
PR 27723 * dw2gencfi.c (select_cie_for_fde): Handle DW_CFA_val_offset, DW_CFA_GNU_window_save and DW_CFA_restore_state.
2021-04-13Remove WinCE code from gdbreplayPedro Alves2-51/+4
gdbserver/ChangeLog: * gdbreplay.c [__MINGW32CE__] (COUNTOF, errno, strerror): Remove.
2021-04-13Remove some unused typedefs from gdbserverTom Tromey2-4/+5
I noticed that gdbserver/win32-low.cc has a few typedefs that are not used. This patch removes them. gdbserver/ChangeLog 2021-04-13 Tom Tromey <tromey@adacore.com> * win32-low.cc (winapi_CreateToolhelp32Snapshot) (winapi_Module32First, winapi_Module32Next): Remove typedefs.
2021-04-13[gdb] Fix regoff_t incompatibilityTom de Vries2-2/+7
I did an experiment with importing the regex module in gnulib, and trying to build gdb. The first problem I ran into was that: - regoff_t was defined as long int, and - the address of a regoff_t variable i in ui_file_style::parse was passed as int * to function extended_color. Fix this by changing the types of some function parameters of functions read_semi_number and extended_color from int * to regoff_t *. Tested on x86_64-linux. gdb/ChangeLog: 2021-04-13 Tom de Vries <tdevries@suse.de> * ui-style.c (read_semi_number, extended_color): Change idx parameter type to regoff_t *.
2021-04-13Fix build failure for 32-bit targets with --enable-targets=allLuis Machado2-2/+9
Replace use of %lx with %s. gdb/ChangeLog: 2021-04-13 Luis Machado <luis.machado@linaro.org> * rs6000-tdep.c (ppc_displaced_step_fixup): Use %s to print hex values.
2021-04-13Document the effect of --as-needed on --rpath on Linux based systems.Nick Clifton2-0/+21
* ld.texi (Options): Add note about the effect of --as-needed on the --rpath and --rpath-link options on Linux based systems.
2021-04-13Remove process_stratum_target::hostio_last_error abstractionPedro Alves10-61/+22
Now that the WinCE port is gone, all ports map host I/O errors from errno, so this abstraction is no longer necessary. Basically undoes: https://sourceware.org/pipermail/gdb-patches/2008-January/055511.html https://sourceware.org/pipermail/gdb-patches/attachments/20080131/f44e7012/attachment.bin gdbserver/ChangeLog: * Makefile.in (SFILES): Remove hostio-errno.cc. * configure: Regenerate. * configure.ac (GDBSERVER_DEPFILES): No longer add $srv_hostio_err_objs. * configure.srv (srv_hostio_err_objs): Delete. * hostio-errno.cc: Delete. * hostio.cc (hostio_error): Inline hostio_last_error_from_errno here. * hostio.h (hostio_last_error_from_errno): Delete. * target.cc (process_stratum_target::hostio_last_error): Delete. * target.h (class process_stratum_target) <hostio_last_error>: Delete.
2021-04-13bfd: avoid infinite loop when static linking XCOFFClément Chigot2-2/+5
git commit b95a0a3177bc changed a "return FALSE" to "continue", and missed updating the while loop iterator. * xcofflink.c (xcoff_link_check_ar_symbols): Update esym earlier.
2021-04-13PR27722, error: array subscript has type charAlan Modra2-3/+9
PR 27722 * libdep_plugin.c (str2vec): Don't pass a potentially signed char to isspace.
2021-04-13Remove now unneeded #ifdef check for NT_NETBSD_PAX.Frederic Cambus2-2/+5
NT_NETBSD_PAX was defined in commit be3b926d8d2dde16a55e9e303fadf95164e13ebf. binutils/ChangeLog: * readelf.c (process_netbsd_elf_note): Remove now unneeded #ifdef check for NT_NETBSD_PAX.
2021-04-13RISC-V: Don't report the mismatched version warning for the implicit extensions.Nelson Chu4-17/+33
bfd/ * elfnn-riscv.c (riscv_version_mismatch): Do not report the warning when the version of input or output is RISCV_UNKNOWN_VERSION, since the extension is added implicitly. * elfxx-riscv.c: Updated the obsolete comments. (RISCV_UNKNOWN_VERSION): Moved to elfxx-riscv.h. * elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Added.
2021-04-13Automatic date update in version.inGDB Administrator1-1/+1
2021-04-12[PATCH,rs6000] Fix vsx-regs.exp testcase failureWill Schmidt2-1/+16
Hi, This test exercise updates to the F* and VS* registers and verifies updates to the same. Note that the registers overlap; the doubleword[1] portion of any VS0-VS31 register contains the F0-F31 register contents, so any updates to one can be measured in the other. Per a brief investigation, we see that dl_main() currently uses some VSX instructions, so the VS* values are not going to be zero when this testcase reaches main, where these tests begin. The test harness does not explicitly initialize the full VS* values, so the first test loop that updates the F* values means our VS* values are uninitalized and will fail the first set of checks. This update explicitly initializes the doubleword[0] portion of the VS* registers, to allow this test to succeed. 2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com> gdb/testsuite/ChangeLog: * gdb.arch/vsx-regs.exp: Initialize vs* doublewords.
2021-04-12[PATCH] gdb-power10-single-stepWill Schmidt5-9/+236
Hi, This is based on a patch originally written by Alan Modra. Powerpc / Power10 ISA 3.1 adds prefixed instructions, which are 8 bytes in length. This is in contrast to powerpc previously always having 4 byte instruction length. This patch implements changes to allow GDB to better detect prefixed instructions, and handle single stepping across the 8 byte instructions. Added #defines to help test for PNOP and prefix instructions. Update ppc_displaced_step_copy_insn() to handle pnop and prefixed instructions whem R=0 (non-pc-relative). Updated ppc_displaced_step_fixup() to properly handle the offset value matching the current instruction size Updated the for-loop within ppc_deal_with_atomic_sequence() to count instructions properly in case we have a mix of 4-byte and 8-byte instructions within the atomic_sequence_length. Added testcase and harness to exercise pc-relative load/store instructions with R=0. 2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com> gdb/ChangeLog: * rs6000-tdep.c: Add support for single-stepping of prefixed instructions. gdb/testsuite/ChangeLog: * gdb.arch/powerpc-plxv-nonrel.s: Testcase using non-relative plxv instructions. * gdb.arch/powerpc-plxv-nonrel.exp: Testcase harness.
2021-04-12[PATCH, rs6000, v3][PR gdb/27525] displaced stepping across addpcis/lnia.Will Schmidt7-1/+319
This addresses PR gdb/27525. The lnia and other variations of the addpcis instruction write the value of the NIA into a target register. If we are single-stepping across a breakpoint, the instruction is executed from a displaced location, and thusly the written value of the PC/NIA will be incorrect. The changes here will measure the displacement offset, and adjust the target register value to compensate. YYYY-MM-DD Will Schmidt <will_schmidt@vnet.ibm.com> gdb/ChangeLog: * rs6000-tdep.c (ppc_displaced_step_fixup): Update to handle the addpcis/lnia instruction. gdb/testsuite/ChangeLog: * gdb.arch/powerpc-addpcis.exp: Testcase harness to exercise single-stepping over subpcis,lnia,addpcis instructions with displacement. * gdb.arch/powerpc-addpcis.s: Testcase with stream of addpcis/lnia/subpcis instructions. * gdb.arch/powerpc-lnia.exp: Testcase harness to exercise single-stepping over lnia instructions with displacement. * gdb.arch/powerpc-lnia.s: Testcase with stream of lnia instructions.
2021-04-12[rs6000] Create a powerpc-power10.exp testWill Schmidt3-0/+1330
Inspired by the existing powerpc-power9.exp test, this is a new test to cover the power10 instruction disassembly. gdb/testsuite/ChangeLog: 2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com> * gdb.arch/powerpc-power10.s: New test for instructions. * gdb.arch/powerpc-power10.exp: Harness to run the test.
2021-04-12Add myself to gdb/MAINTAINERSWill Schmidt2-0/+5
gdb/ChangeLog: * MAINTAINERS (Write After Approval): Add myself.
2021-04-13m68hc11 gas testsuite wartAlan Modra2-13/+15
Writing to a potentially read-only source directory is not good. * testsuite/gas/m68hc11/m68hc11.exp (gas_m68hc11_message): Don't write to $srcdir. Use gas_host_run and read output file rather than gas_start/gas_finish.
2021-04-12RS6000 Add support to print vector register contents as float128Carl Love5-0/+138
This patch adds a floating point 128-bit composite field to the vsx register type. When printing the register with p/f the float128 field will be printed as a 128-bit floating point value. A test case to verify the new vsx register field is visible and correctly prints out the value of a 128-bit floating point value is also added. gdb/ChangeLog: * rs6000-tdep.c (rs6000_builtin_type_vec128): Add t_float128 variable. (rs6000_builtin_type_vec128): Add append_composite_type_field for float128. gdb/testsuite/ChangeLog: * gdb.arch/vsx-vsr-float128.c: New test file. * gdb.arch/vsx-vsr-float128.exp: New expect file.
2021-04-12gdb, gdbserver: remove WinCE support codeSimon Marchi6-191/+15
The support for WinCE was removed with commit 84b300de3666 ("gdbserver: remove support for ARM/WinCE"). There is some leftover code for WinCE support, guarded by the _WIN32_WCE macro, which I didn't know of at the time. I didn't remove the _WIN32_WCE references in the tests, because in theory we still support the WinCE architecture in GDB (when debugging remotely). So someone could run a test with that (although I'd be really surprised). gdb/ChangeLog: * nat/windows-nat.c: Remove all code guarded by _WIN32_WCE. * nat/windows-nat.h: Likewise. gdbserver/ChangeLog: * win32-low.cc: Remove all code guarded by _WIN32_WCE. * win32-low.h: Likewise. Change-Id: I7a871b897e2135dc195b10690bff2a01d9fac05a
2021-04-13ENABLE_CHECKING in bfd, opcodes, binutils, ldAlan Modra17-8/+178
gas already has this. Here it enables checking hash table type passed to elf_link_hash_lookup and elf_link_hash_traverse. bfd/ * elf-bfd.h (ENABLE_CHECKING): Define. (elf_link_hash_lookup): Abort if wrong type of hash table. (elf_link_hash_traverse): Likewise. * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. binutils/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. ld/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. opcodes/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate.
2021-04-12gdbserver: constify the 'pid_to_exec_file' target opTankut Baris Aktemur8-9/+19
gdbserver/ChangeLog: 2021-04-12 Tankut Baris Aktemur <tankut.baris.aktemur@intel.com> * target.h (class process_stratum_target) <pid_to_exec_file>: Constify the return type. Update the definition/references below. * target.cc (process_stratum_target::pid_to_exec_file) * linux-low.h (class linux_process_target) <pid_to_exec_file> * linux-low.cc (linux_process_target::pid_to_exec_file) * netbsd-low.h (class netbsd_process_target) <pid_to_exec_file> * netbsd-low.cc (netbsd_process_target::pid_to_exec_file) * server.cc (handle_qxfer_exec_file)
2021-04-12gdb, testsuite, btrace: relax unneeded stepi expected outputMarkus Metzger2-1/+5
In gdb.btrace/reconnect.exp, we test that we can disconnect and reconnect again to a GDB session that is recording with the btrace recording format. It does not really matter what we are recording. The test assumed that stepping from _start will bring us into an area without debug information. This is not correct on all systems. Relax the expected output to also support systems where we do have debug information for that code.
2021-04-12convert elf_link_hash macros to inline functionsAlan Modra14-56/+101
Involves a bit of editing as we now need to be more precise in pointer types. bfd/ * elf-bfd.h (is_elf_hash_table): Convert macro to inline function. (elf_link_hash_lookup, elf_link_hash_traverse): Likewise. (elf_hash_table, elf_hash_table_id): Likewise. * elf32-arm.c (elf32_arm_setup_section_lists): Delete redundant is_elf_hash_table check. * elf32-csky.c (elf32_csky_setup_section_lists): Likewise. * elf32-hppa.c (clobber_millicode_symbols): Correct param types. * elf64-alpha.c (elf64_alpha_output_extsym): Likewise. * elfnn-ia64.c (elfNN_ia64_global_dyn_info_free: Likewise. (elfNN_ia64_global_dyn_sym_thunk: Likewise. * elf64-ia64-vms.c (elf64_ia64_global_dyn_info_free): Likewise. (elf64_ia64_global_dyn_sym_thunk): Likewise. (elf64_vms_link_add_object_symbols): Pass base type of hash table to is_elf_hash_table. * elflink.c (_bfd_elf_dynamic_symbol_p): Likewise. (_bfd_elf_symbol_refs_local_p, _bfd_elf_add_dynamic_entry): Likewise. (_bfd_elf_strip_zero_sized_dynamic_sections): Likewise. (_bfd_elf_link_check_relocs, elf_link_add_object_symbols): Likewise. (bfd_elf_final_link): Likewise. * elfnn-aarch64.c (elfNN_aarch64_setup_section_lists): Likewise. * elf64-ppc.c (ppc64_elf_set_toc): Likewise. Use bfd_link_hash_lookup. ld/ * emultempl/mipself.em (mips_create_output_section_statements): Pass base type of hash table to is_elf_hash_table. * ldelf.c (ldelf_after_open): Likewise.
2021-04-12elf_backend_archive_symbol_lookupAlan Modra4-20/+33
elf_backend_archive_symbol_lookup might be called when the linker hash table has entries of type generic_link_hash_entry. This happens for instance when running the mmix target linker testsuite where the output is mmo but input is elf64-mmix. * elf-bfd.h (struct elf_backend_data): Return bfd_link_hash_entry* from elf_backend_archive_symbol_lookup. (_bfd_elf_archive_symbol_lookup): Return bfd_link_hash_entry*. * elf64-ppc.c (ppc64_elf_archive_symbol_lookup): Likewise. Check we have a ppc_hash_table before accessing ppc_link_hash_entry fields. * elflink.c (_bfd_elf_archive_symbol_lookup): Return bfd_link_hash_entry*. (elf_link_add_archive_symbols): Adjust to suit.
2021-04-12RISC-V: The version of i-ext should be RISCV_UNKNOWN_VERSION when expanding ↵Nelson Chu2-2/+7
g-ext. Fix the wrong version of i-ext when expanding g-ext. This was changed by the previous patch accidently. bfd/ * elfxx-riscv.c (riscv_parse_std_ext): Fixed the wrong versions of i-ext when expanding g-ext.
2021-04-12RISC-V: Add i-ext as the implicit extension when e-ext is set.Nelson Chu2-37/+27
The linker does not care the default versions of the extensions, since it does not have the default ISA spec setting. Therefore, linker won't insert the implicit extensions for the input objects. But we used to insert the i-ext as the explicit extension, even if the e-ext is set. This causes linker to report "cannot find default versions of the ISA extension `i'" errors when linking the input objects with e-ext. This patch fixes the above linker problem, and also remove the confused riscv_ext_dont_care_version function. Unless these "dont care" extensions are set in the input architecture explicitly, otherwise we always insert them as the implicit ones. Afterwards, let riscv_arch_str1 surpress them not to output to the architecture string if their versions are RISCV_UNKNOWN_VERSION. bfd/ * elfxx-riscv.c (riscv_ext_dont_care_version): Removed. (riscv_parse_add_subset): Always add the implicit extensions, even if their versions are RISCV_UNKNOWN_VERSION. (riscv_parse_std_ext): Delay to add i-ext as the implicit extension in the riscv_parse_add_implicit_subsets. Besides, add g-ext as the implicit extension after it has been expanded. (riscv_parse_add_implicit_subsets): Updated.
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger57-35/+156
Every arch handles this the same way, so move it to the common code. This will also make unifying the sim_cpu structure easier.
2021-04-12Power10 bignum operandsAlan Modra6-70/+124
When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12PR27719, lang_mark_undefineds trashes memoryAlan Modra5-5/+16
It's not enough to test that the output is ELF before casting bfd_link_hash_entry to elf_link_hash_entry. Some ELF targets (d30v, dlx, pj, s12z, xgate) use the generic linker support in bfd/linker.c and thus their symbols are of type generic_link_hash_entry. Not all of the places this patch touches can result in wrong accesses, but I thought it worth ensuring that all occurrences of elf_link_hash_entry in ld/ were obviously correct. PR 27719 * ldlang.c (lang_mark_undefineds, undef_start_stop): Test that the symbol hash table is the correct type before accessing elf_link_hash_entry symbols. * plugin.c (is_visible_from_outside): Likewise. * emultempl/armelf.em (ld${EMULATION_NAME}_finish): Likewise. * emultempl/solaris2.em (elf_solaris2_before_allocation): Likewise.
2021-04-12RISC-V: Support to parse the multi-letter prefix in the architecture string.Nelson Chu26-235/+291
The original discussion is as follows, https://github.com/riscv/riscv-isa-manual/issues/637 I never considered the prefixes may have multiple letters, like zxm. But the ISA spec has been updated for a long time that I haven't noticed. This patch rewrites the part of architecture parser to support parsing the multi-letter prefixes. Besides, I also improve the parser to report errors in details. One of the most obvious improvement is - Do not parse the prefixed extensions according to the orders in the parse_config. If we do so, then we used to get "unexpected ISA string at end" errors, but the message is a little bit hard to know what is happening. I Remove the confused message, and let riscv_parse_prefixed_ext to report the details. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Moved forward. (riscv_std_s_ext_strtab): Likewise. (riscv_std_h_ext_strtab): Likewise. (riscv_std_zxm_ext_strtab): Added for the zxm prefix. (enum riscv_prefix_ext_class): Moved forward and renamed from riscv_isa_ext_class. Reorder them according to the parsing order, since the enum values are used to check the orders in the riscv_compare_subsets. (struct riscv_parse_prefix_config): Moved forward and renamed from riscv_parse_config_t. Also removed the ext_valid_p field, the related functions are replaced by riscv_valid_prefixed_ext. (parse_config): Moved forward and updated. The more letters of the prefix string, the more forward it must be defined. Otherwise, we will get the wrong mapping when using strncmp in riscv_get_prefix_class. (riscv_get_prefix_class): Moved forward. Support to parse the multi-letter prefix, like zxm. (riscv_known_prefixed_ext): New function, check if the prefixed extension is supported according to the right riscv_std_*_ext_strtab. (riscv_valid_prefixed_ext): New function, used to replace the riscv_ext_*_valid_p functions. (riscv_init_ext_order): Do not set the values for prefix keywords since they may have multiple letters for now. (riscv_compare_subsets): Set the order values of prefix keywords to negative numbers according to the riscv_prefix_ext_class. (riscv_parse_std_ext): Call riscv_get_prefix_class to see if we have parsed the prefixed extensions. (riscv_parse_prefixed_ext): Updated and removed the parameter config. Report error when the prefix is unknown. (riscv_parse_subset): Do not parse the prefixed extensions according to the orders in the parse_config. Remove the confused message and let riscv_parse_prefixed_ext to report the details. * elfxx-riscv.h (enum riscv_isa_ext_class): Moved to elfxx-riscv.c. (riscv_get_prefix_class): Removed to static. gas/ * testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from march-fail-porder-x-std.d. * testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from march-fail-porder-z-std.d. * testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from march-fail-porder-x-z.d. * testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace march-fail-porder.l. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Updated. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from march-fail-single-char-h.d. * testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from march-fail-single-char-s.d. * testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from march-fail-single-char-x.d. * testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from march-fail-single-char-z.d. * testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added. * testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace march-fail-single-prefix.l. * testsuite/gas/riscv/march-fail-unknown-zxm.d: Added. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-fail-unknown.l: Likewise.
2021-04-12Automatic date update in version.inGDB Administrator1-1/+1
2021-04-11Improve support for loading DLLs at run time in gdbserver.Eli Zaretskii2-12/+52
This fixes win32-low.cc in the same way as a recent change in windows-nat.c did for GDB: if the lpImageName member of the load-DLL debug event doesn't allow us to find the file name of the DLL, then loop over all the DLLs mapped into the inferior to find the one loaded at the same base address as given by the lpBaseOfDll member of the debug event. gdbserver/ChangeLog: 2021-04-11 Eli Zaretskii <eliz@gnu.org> * win32-low.cc (win32_add_dll): New function, with body almost identical to what win32_add_all_dlls did. Accepts one argument; if that is non-NULL, returns the file name of the DLL that is loaded at the base address equal to that argument, or NULL if not found. If the argument is NULL, add all the DLLs loaded by the inferior to the list of solibs and return NULL. (win32_add_all_dlls): Now a thin wrapper around win32_add_dll. (windows_nat::handle_load_dll) [!_WIN32_WCE]: If get_image_name failed to glean the file name of the DLL, call win32_add_dll to try harder using the lpBaseOfDll member of the load-DLL event.
2021-04-11Automatic date update in version.inGDB Administrator1-1/+1
2021-04-10Fix handling DLL loads at run timeEli Zaretskii2-11/+56
This patch makes handling a DLL load at run time (using LoadLibrary) much more reliable when its file name cannot be obtained using the lpImageName pointer provided by the DLL load debug event. The solution is to enumerate all the DLLs loaded by the inferior, looking for the DLL that's loaded at base address provided by the lpBaseOfDll pointer of the debug event. Correctly resolving the DLL file name is important, because without that GDB doesn't record the DLL in the list of solibs, and then later is unable to show functions in that DLL in the backtraces, which produces corrupted and truncated backtraces. See this thread for the problems that causes: https://sourceware.org/pipermail/gdb-patches/2021-March/177022.html gdb/ChangeLog: 2021-04-10 Eli Zaretskii <eliz@gnu.org> * windows-nat.c (windows_nat::handle_load_dll): Call windows_add_dll if get_image_name failed to glean the name of the DLL by using the lpImageName pointer. (windows_add_all_dlls): Now a thin wrapper around windows_add_dll. (windows_add_dll): Now does what windows_add_all_dlls did before, but also accepts an argument LOAD_ADDR, which, if non-NULL, specifies the address where the DLL was loaded into the inferior, and looks for the single DLL loaded at that address.
2021-04-10Automatic date update in version.inGDB Administrator1-1/+1
2021-04-09Add missing ChangeLog entry for sim/rx change.Luis Machado1-0/+4
2021-04-09[AArch64] Fix include order for MTELuis Machado2-1/+6
Similarly to commit 665af52ec2a52184d39a76d6e724fa4733dbab3c, fix a build failure seen with an updated glibc, due to the enum/constant mismatch. The old include file order eventually makes asm/ptrace.h get included before sys/ptrace.h. This patch fixes it. Seems fairly obvious and I'll push it shortly. gdb/ChangeLog: 2021-04-09 Luis Machado <luis.machado@linaro.org> * nat/aarch64-mte-linux-ptrace.c: Update include file order.
2021-04-09[sim,rx] Silence warning that turns into a build errorLuis Machado1-1/+1
On a 32-bit build, I ran into the following: sim/rx/fpu.c:789:6: error: "*((void *)&a+8)" may be used uninitialized in this function [-Werror=maybe-uninitialized] rv = fp_implode (&a); To silence this, just initialize the struct with 0's. sim/rx/ChangeLog: 2021-04-09 Luis Machado <luis.machado@linaro.org> * fpu.c (rxfp_itof): Initialize structure.
2021-04-09AArch64: Fix Diagnostic messaging for LD/ST Exclusive.Tejas Belagod4-14/+53
A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' gas/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages for LD/ST Exclusive instructions. * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP. * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
2021-04-09AArch64: Fix Atomic LD64/ST64 classification.Tejas Belagod2-4/+9
Patch 1: Fix diagnostics for exclusive load/stores and reclassify Armv8.7-A ST/LD64 Atomics. Following upstream pointing out some inconsistencies in diagnostics, https://sourceware.org/pipermail/binutils/2021-February/115356.html attached is a patch set that fixes the issues. I believe a combination of two patches mainly contributed to these bugs: https://sourceware.org/pipermail/binutils/2020-November/113961.html https://sourceware.org/pipermail/binutils/2018-June/103322.html A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' For instructions: st64bv x0, x2, [x0] st64bv x2, x0, [x0] We incorrectly warn when its not necessary. This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. Patch 2: Reclassify Armv8.7-A ST/LD64 Atomics. This patch reclassifies ST64B{V,V0}, LD64B as lse_atomics rather than ldstexcl according to their encoding class as specified in the architecture. This also has the fortunate side-effect of spurious unpredictable warnings getting eliminated. For eg. For instruction: st64bv x0, x2, [x0] We incorrectly warn when its not necessary: Warning: unpredictable: identical transfer and status registers --`st64bv x0,x2,[x0]' This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. This patch fixes it by reclassifying it and no warnings are issued for this instruction. opcodes/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify LD64/ST64 instructions to lse_atomic instead of ldstexcl.
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra22-147/+311
This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.
2021-04-09Automatic date update in version.inGDB Administrator1-1/+1
2021-04-08Avoid sequence point warning in h8300 simTom Tromey2-1/+6
GCC gives a -Wsequence-point warning for this code in the h8300 sim. The bug is that memory_size is both assigned and used in the same expression. The fix is to assign after the print. sim/h8300/ChangeLog 2021-04-08 Tom Tromey <tom@tromey.com> * compile.c (init_pointers): Fix sequence point warning.
2021-04-08Add system includes in simTom Tromey20-0/+48
This updates various parts of the sim to include missing system headers. I made the includes unconditional, because other parts of the tree are already doing this. 2021-04-08 Tom Tromey <tom@tromey.com> * traps.c: Include stdlib.h. * cris-tmpl.c: Include stdlib.h. sim/erc32/ChangeLog 2021-04-08 Tom Tromey <tom@tromey.com> * func.c: Include sys/time.h. sim/frv/ChangeLog 2021-04-08 Tom Tromey <tom@tromey.com> * traps.c: Include stdlib.h. * registers.c: Include stdlib.h. * profile.c: Include stdlib.h. * memory.c: Include stdlib.h. * interrupts.c: Include stdlib.h. * frv.c: Include stdlib.h. * cache.c: Include stdlib.h. sim/iq2000/ChangeLog 2021-04-08 Tom Tromey <tom@tromey.com> * iq2000.c: Include stdlib.h. sim/m32r/ChangeLog 2021-04-08 Tom Tromey <tom@tromey.com> * traps.c: Include stdlib.h. * m32r.c: Include stdlib.h. sim/ppc/ChangeLog 2021-04-08 Tom Tromey <tom@tromey.com> * emul_unix.c: Include time.h.
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