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2016-03-29PE/COFF regression in base of code and data calculationToni Spets2-0/+8
PR 19878 * coffcode.h (coff_write_object_contents): Revert accidental 2014-11-10 change.
2016-03-28add more const qualifiersTrevor Saunders8-16/+31
gas/ChangeLog: 2016-03-28 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/obj-elf.c (obj_elf_section_name): Return const char *. * config/obj-elf.h (obj_elf_section_name): Adjust. * config/tc-aarch64.c (aarch64_parse_features): Likewise. (aarch64_parse_cpu): Likewise. (aarch64_parse_arch): Likewise. * config/tc-arm.c (arm_parse_extension): Likewise. (arm_parse_cpu): Likewise. (arm_parse_arch): Likewise. * config/tc-nds32.c: Likewise. * config/xtensa-relax.c (parse_special_fn): Likewise. * stabs.c (generate_asm_file): Likewise.
2016-03-29Automatic date update in version.inGDB Administrator1-1/+1
2016-03-28Automatic date update in version.inGDB Administrator1-1/+1
2016-03-27Fix failure to diagnose GOTOFF relocation to undef symbol in shared lib (i386).Cary Coutant2-0/+23
gold/ PR gold/16111 * i386.cc (Target_i386): Add check for fully-resolved symbol for R_386_GOTOFF.
2016-03-27Automatic date update in version.inGDB Administrator1-1/+1
2016-03-25split up cr16s md_assemble ()Trevor Saunders2-25/+42
gas/ChangeLog: 2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-cr16.c (cr16_assemble): New function. (md_assemble): Call cr16_assemble.
2016-03-25rename flag_size_check to flag_allow_nonconst_size and make it a boolTrevor Saunders4-9/+10
This name describes what the variable means slightly better, and the enum with two values that is only used for this one variable is kind of silly. gas/ChangeLog: 2016-03-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * as.c (parse_args): Adjust. * as.h (flag_size_check): Rename to flag_allow_nonconst_size. * config/obj-elf.c (elf_frob_symbol): Adjust.
2016-03-26Automatic date update in version.inGDB Administrator1-1/+1
2016-03-25Automatic date update in version.inGDB Administrator1-1/+1
2016-03-24More -Wstack-usage warnings: opcodes/aarch64-*Jan Kratochvil3-7/+11
opcodes Fix -Wstack-usage warnings. * aarch64-dis.c (print_operands): Substitute size. * aarch64-opc.c (print_register_offset_address): Substitute tblen.
2016-03-24gas: sparc: allow ASR registers in the 0..31 range in V9 and laterJose E. Marchesi2-16/+21
In the SPARC V9 (and later) versions of the SPARC specification, the section C.1.1 "Register Names" specifies that: "asr_reg. An asr_reg is an Ancillary State Register name. It may have one of the following values: %asr16-%asr31" The rationale of having this restriction was that the registers from 16 to 31 are reserved to implementations, and are therefore "non-V9". It also assumes that the existing ASR registers in the range 0..31 will have their own names such as %y, that can be used to access such registers. However, this is problematic. When a new ASR register is introduced, such as %mcdper a.k.a. %asr14, it is useful to be able to use %asr14 in order to not depend on the latest version of the assembler. The Solaris assembler is lax and allows to assembly instructions referring to %asr0 to %asr31. This patch makes the GNU assembler to mimic that behavior. gas/ChangeLog: 2016-03-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_ip): Remove the V9 restriction on ASR registers to be in the 16..31 range.
2016-03-24sparc: reorder wr instructions in sparc_opcodes to fix diagnosticsJose E. Marchesi2-6/+11
This patch changes the location of several variants of the `wr' instruction in sparc_opcodes. This is to get the assembler to emit the right diagnostics when an invalid %asrN register is used in an instruction.
2016-03-24make microblaze build with -Wwrite-stringsTrevor Saunders2-4/+9
frag_var () assigns its last argument to frag::fr_opcode, and it turns out some targets modify the string that points to. However it appears niether the generic code or the microblaze code modifies what fr_opcode points to, so this code should be safe. So we unfortunately need to cast to char * when passing an argument to frag_var () but otherwise microblaze can itself point to these strings with const char *. gas/ChangeLog: 2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-microblaze.c (md_assemble): Cast opc to char * when calling frag_var ().
2016-03-24localize string returned from visium's md_atof ()Trevor Saunders2-1/+6
I'm not sure the string it returns is particularly useful, or better than the string returned by other atof implementations on failure, but given the others return a localized string it seems like this one should too. gas/ChangeLog: 2016-03-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-visium.c (md_atof): Localize the string returned on failure.
2016-03-24Add quotation mark in test messageYao Qi2-1/+6
I happen to see a quotation mark is missing the following test, gdb_test "break $end_location" \ "Breakpoint $decimal at .* line $end_location\." \ set breakpoint at end of main" so the test result is PASS: gdb.reverse/break-reverse.exp: set This patch is to add the missing quotation mark back, and the test result becomes PASS: gdb.reverse/break-reverse.exp: set breakpoint at end of main gdb/testsuite: 2016-03-24 Yao Qi <yao.qi@linaro.org> * gdb.reverse/break-reverse.exp: Add quotation mark in the test message.
2016-03-24Automatic date update in version.inGDB Administrator1-1/+1
2016-03-23More AArch64 simulator improvements.Nick Clifton6-278/+721
* cpustate.c (aarch64_get_FP_half): New function. Read a vector register as a half precision floating point number. (aarch64_set_FP_half): New function. Similar, but for setting a half precision register. (aarch64_get_thread_id): New function. Returns the value of the CPU's TPIDR register. (aarch64_get_FPCR): New function. Returns the value of the CPU's floating point control register. (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR register. * cpustate.h: Add prototypes for new functions. * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. * memory.c: Use unaligned core access functions for all memory reads and writes. * simulator.c (HALT_NYI): Generate an error message if tracing will not tell the user why the simulator is halting. (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. (INSTR): New time-saver macro. (fldrb_abs): New function. Loads an 8-bit value using a scaled offset. (fldrh_abs): New function. Likewise for 16-bit values. (do_vec_SSHL): Allow for negative shift values. (do_vec_USHL): Likewise. (do_vec_SHL): Correct computation of shift amount. (do_vec_SSHR_USHR): Correct decision of signed vs unsigned shifts and computation of shift value. (clz): New function. Counts leading zero bits. (do_vec_CLZ): New function. Implements CLZ (vector). (do_vec_MOV_element): Call do_vec_CLZ. (dexSimpleFPCondCompare): Implement. (do_FCVT_half_to_single): New function. Implements one of the FCVT operations. (do_FCVT_half_to_double): New function. Likewise. (do_FCVT_single_to_half): New function. Likewise. (do_FCVT_double_to_half): New function. Likewise. (dexSimpleFPDataProc1Source): Call new FCVT functions. (do_scalar_SHL): Handle negative shifts. (do_scalar_shift): Handle SSHR. (do_scalar_USHL): New function. (do_double_add): Simplify to just performing a double precision add operation. Move remaining code into... (do_scalar_vec): ... New function. (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs functions. (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR registers. (system_set): New function. (do_MSR_immediate): New function. Stub for now. (do_MSR_reg): New function. Likewise. Partially implements MSR instruction. (do_SYS): New function. Stub for now, (dexSystem): Call new functions.
2016-03-23Remove comments on software_single_step in gdbarch.shYao Qi3-8/+5
This comment is out of date. We've already done that. Patch is to remove it. gdb: 2016-03-23 Yao Qi <yao.qi@linaro.org> * gdbarch.sh (software_single_step): Remove comments. * gdbarch.h: Regenerated.
2016-03-23Automatic date update in version.inGDB Administrator1-1/+1
2016-03-22make more variables constTrevor Saunders15-33/+63
gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-h8300.c (h8300_elf_section): Add const qualifiers. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-m68hc11.c (md_begin): Likewise. (print_opcode_list): Likewise. * config/tc-msp430.c (msp430_section): Likewise. * config/tc-score.c (struct s3_insn_to_dependency): Likewise. (s3_build_dependency_insn_hsh): Likewise. * config/tc-score7.c (struct s7_insn_to_dependency): Likewise. (s7_build_dependency_insn_hsh): Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (subsym_get_arg): Likewise. * config/tc-xtensa.c (struct suffix_reloc_map): Likewise. (get_directive): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c: Likewise. * symbols.c (symbol_create): Likewise. (local_symbol_make): Likewise. (symbol_relc_make_expr): Likewise. include/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/i960.h: Add const qualifiers. * opcode/tic4x.h (struct tic4x_inst): Likewise.
2016-03-22tc-pdp11.c: remove useless codeTrevor Saunders2-2/+5
if the condition is true then we know that str already points to a'\0' in the string passed to the function. Since we know the latter part of the function doesn't modify that string, and str already points to a null byte there's no point in changing str to point to a literal empty string. gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-pdp11.c (md_assemble): Remove useless if and assignment to str.
2016-03-22tc-sparc.c: get rid of wierd usage of strchr ()Trevor Saunders2-6/+18
This lets us avoid assigning a literal to a char *, and perhaps more importantly makes it clearer what is going on here. gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sparc.c (sparc_regname_to_dw2regnum): Replace strchr () call with a switch.
2016-03-22use do_align () directly in tc-ia64.cTrevor Saunders2-19/+17
gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ia64.c (ia64_do_align): Remove. (ia64_cons_align): Call do_align () directly. (dot_proc): Likewise. (stmt_float_cons): Likewise.
2016-03-22replace some raw xmalloc / xrealloc with the XNEW* macrosTrevor Saunders4-20/+33
This increases consistancy of how we allocate memory, and always casting the result to the proper type. It also helps make sure we get any use of sizeof on the result type correct. gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * listing.c (listing_message): Use XNEW style allocation macros. * read.c (read_a_source_file): Likewise. (read_symbol_name): Likewise. (s_mri_common): Likewise. (assign_symbol): Likewise. (s_reloc): Likewise. (emit_expr_with_reloc): Likewise. (s_incbin): Likewise. (s_include): Likewise. * sb.c (sb_build): Likewise. (sb_check): Likewise.
2016-03-22Fix unbounded stack usage warning inside the SAFE_BYTE_GET macro.Nick Clifton2-1/+10
PR 19851 binutils * dwarf.c (SAFE_BYTE_GET): Replace local dynamic array allocation with run time size check.
2016-03-22Improve COFF/PE linker garbage collection by preventing the removal of ↵Nick Clifton6-34/+47
sections containing exported symbols. PR ld/19803 * ldlang.c (lang_add_gc_name): New function. Adds the provided symbol name to the list of gc symbols. (lang_process): Call lang_add_gc_name with entry_symbol_default if entry_symbol.name is NULL. Use lang_add_gc_name to add the init and fini function names. * pe-dll.c (process_def_file_and_drectve): Add exported names to the gc symbol list. * testsuite/ld-pe/pr19803.s: Do not export _testval symbol. * testsuite/ld-pe/pr19803.d: Tweak expected output.
2016-03-22Attribute with DW_FORM_flag_presentAlan Modra2-1/+7
PR 19850 * dwarf2.c (read_attribute_value): Skip info_ptr check for DW_FORM_flag_present.
2016-03-22Fix tic54x regressionAlan Modra2-3/+4
One of the tic54x testcases looks for a section alignment of 1. After 9136aa49 the alignment became 0. While it happens that an alignment of 0 is treated as an alignment of 1, there is no reason to not apply the explicit alignment. * write.c (record_alignment): Revert 2016-02-18 change.
2016-03-22Remove more alloca callsAlan Modra3-5/+16
* config/tc-alpha.c (load_expression): Replace alloca with xmalloc. (emit_jsrjmp, tc_gen_reloc): Likewise. * config/tc-i370.c (i370_macro): Likewise.
2016-03-22Restore v850-rh850 as a recognised v850 architecture name for backwards ↵Nick Clifton2-1/+5
compatibility. bfd * cpu-v850_rh850.c (arch_info_struct): Restore v850-rh850 as an architecture name for backwards compatibility.
2016-03-22Fix possible unbounded stack use in peXXigen.cNick Clifton2-5/+12
* peXXigen.c (_bfd_XXi_write_codeview_record): Fix possible unbounded stack use.
2016-03-22Add -Wstack-usage to the gcc warning flags list, but only if using a ↵Nick Clifton15-8/+171
sufficiently recent version of gcc. bfd * warning.m4 (GCC_WARN_CFLAGS): Only add -Wstack-usage if using a sufficiently recent version of GCC. * configure: Regenerate. others * configure: Regenerate.
2016-03-21Fix problem where gold fails to issue an undefined symbol error during LTO.Cary Coutant7-2/+143
During LTO, if (1) an IR file contains a COMDAT group that is kept, (2) a later non-claimed file contains the same group, which we discard, and (3) the plugin fails to provide a definition of the symbols in that COMDAT group, gold silently resolves any references to those symbols to 0. This patch adds a check for a placeholder symbol when deciding whether to issue an undefined symbol error. It also adds an extra note after any undefined placeholder symbol error that explains that a definition was expected from the plugin. gold/ PR gold/19842 * errors.cc (Errors::undefined_symbol): Add info message when symbol should have been provided by a plugin. * target-reloc.h (issue_undefined_symbol_error): Check for placeholder symbols defined in discarded sections. * testsuite/Makefile.am (plugin_test_9b): New test case. * testsuite/Makefile.in: Regenerate. * testsuite/plugin_test_9b_elf.cc: New test source file. * testsuite/plugin_test_9b_ir.cc: New test source file.
2016-03-22Binutils fails to build with -O0Alan Modra2-2/+6
PR 19851 * plugin.c (try_load_plugin): Avoid -Wstack-usage warning.
2016-03-22Automatic date update in version.inGDB Administrator1-1/+1
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess10-0/+232
Adds the first few nps400 instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-0.d: New file. * testsuite/gas/arc/nps400-0.s: New file. * testsuite/gas/arc/nps400-1.d: New file. * testsuite/gas/arc/nps400-1.s: New file. include/ChangeLog: * opcodes/arc.h (insn_class_t): Add BITOP type. opcodes/ChangeLog: * arc-nps400-tbl.h: New file. * arc-opc.c: Add top level comment. (insert_nps_3bit_dst): New function. (extract_nps_3bit_dst): New function. (insert_nps_3bit_src2): New function. (extract_nps_3bit_src2): New function. (insert_nps_bitop_size): New function. (extract_nps_bitop_size): New function. (arc_flag_operands): Add nps400 entries. (arc_flag_classes): Add nps400 entries. (arc_operands): Add nps400 entries. (arc_opcodes): Add nps400 include.
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess9-40/+81
When parsing the operand instruction flags we don't currently detect the case where multiple flags are provided from the same class set, these will be accepted and the bit values merged together, resulting in the wrong instruction being assembled. For example: adc.n.eq r0,r0,r2 Will assemble without error, yet, upon disassembly, the instruction will actually be: adc.c r0,r0,r2 In a later commit the concept of required flags will be introduced. Required flags are just like normal instruction flags, except that they must be present for the instruction to match. Adding this will allow for simpler instructions in the instruction table, and allow for more sharing of operand extraction and insertion functions. To solve both of the above issues (multiple flags being invalid, and required flags), this commit reworks the flag class mechanism. Currently the flag class is never used. Each instruction can reference multiple flag classes, each flag class has a class type and a set of flags. However, at present, the class type is never used. The current values identify the type of instruction that the flag will be used in, but this is not required information. Instead, this commit discards the old flag classes, and introduces 3 new classes. The first F_CLASS_NONE, is just a NULL marker value, and is only used in the NULL marker flag class. The other two flag classes are F_FLAG_OPTIONAL, and F_FLAG_REQUIRED. The class F_FLAG_OPTIONAL has the property that at most one of the flags in the flag set for that class must be present in the instruction. The "at most" one means that no flags being present is fine. The class F_FLAG_REQUIRED is not currently used, but will be soon. With this class, exactly one of the flags from this class must be present in the instruction. If the flag class contains a single flag, then of course that flag must be present. However, if the flag class contained two or more, then one, and only one of them must be present. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. Handle flag class. * testsuite/gas/arc/asm-errors.d: New file. * testsuite/gas/arc/asm-errors.err: New file. * testsuite/gas/arc/asm-errors.s: New file. include/ChangeLog: * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 new classes instead. opcodes/ChangeLog: * arc-opc.c (arc_flag_classes): Convert all flag classes to use the new class enum values.
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess14-2/+50
This commit introduces the nps400 machine type as a variant of arc. There's a new flag in the assembler to select this machine type. All other changes are just adding handling of the new machine type into the relevant places. The nps400 is an arc700 variant with some vendor specific instructions added into the instruction set. This commit does not add any of the new instructions, this is just laying the groundwork for future commits. However, in preparation for these new instructions a new opcode define for nps400 has been added to include/opcode/arc.h, this new opcode define is used in the assembler and disassembler along with the existing define for arc700 such that when assembling and disassembling for nps400 the user will have access to all arc700 instructions and all the nps400 vendor extension instructions. bfd/ChangeLog: * archures.c (bfd_mach_arc_nps400): Define. * bfd-in2.h: Regenerate. * cpu-arc.c (arch_info_struct): New entry for nps400, renumber some existing entries to make space. * elf32-arc.c (arc_elf_object_p): Add nps400 case. (arc_elf_final_write_processing): Likewise. binutils/ChangeLog: * readelf.c (decode_ARC_machine_flags): Handle nps400. gas/ChangeLog: * config/tc-arc.c (cpu_types): Add nps400 entry. (check_zol): Handle nps400. include/ChangeLog: * elf/arc.h (E_ARC_MACH_NPS400): Define. * opcode/arc.h (ARC_OPCODE_NPS400): Define. opcodes/ChangeLog: * arc-dis.c (print_insn_arc): Handle nps400.
2016-03-21arc: Remove EF_ARC_CPU_GENERIC constant.Andrew Burgess8-92/+97
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h file, and is used in a few places in binutils, however, this constant should never make it into the elf header flags; we always set a valid cpu type in the assembler, which should then be copied over during linking. There are some non-gnu arc compilers that don't write an architecture type into the e_flags field, instead leaving the field as 0, which is the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine type to distinguish between the old and newer arc architectures, setting the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700 architectures, while using EM_ARC_COMPACT2 for newer arcem and archs architectures. Previously when displaying the machine flags for an older EM_ARC_COMPACT machine, if the e_flags had not been filled in, then we relied on the default case statement to display the message "Generic ARCompact", while in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC to print "ARC Generic", leaving the default case to print a message about unrecognised cpu flag. After this commit EF_ARC_CPU_GENERIC has been removed, for both machine types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case statement to handle the situation where the e_flags has not been filled in. The message displayed is now "Unknown ARCompact" (for older arc architectures) and "Unknown ARC" (for the newer architectures). The switch from "Generic" to "Unknown" in the message string is for clarity, calling the file "Generic" can give the impression that the file is compiled for a common sub-set of the architectures, and would therefore run on any type of machine (or at least any type of new or old machine depending on if the machine type is ARC or ARCv2). However, this was not what "Generic" meant, it really meant "Unknown", so that's what we now say. As part of the merging of the readelf flag reading code, I have unified the strings used in displaying the ELF ABI. This means that for older arc machines (arc600, arc601, and arc700) the string used for the original ABI, and ABIv2 have changed, the current ABIv3 remains the same. For the newer architectures (arcem and archs) the abi strings remain unchanged in all cases. bfd/ChangeLog: * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of EF_ARC_CPU_GENERIC. (arc_elf_final_write_processing): Don't bother setting cpu field in e_flags, this will have been set elsewhere. binutils/ChangeLog: * readelf.c (get_machine_flags): Move arc processing into... (decode_ARC_machine_flags): ... new function. Remove use of EF_ARC_CPU_GENERIC, change default case from "generic arc" to "unknown arc". Merged ABI printing between two machine types. gas/ChangeLog: * config/tc-arc.c (arc_select_cpu): Remove use of EF_ARC_CPU_GENERIC. include/ChangeLog: * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-21arc: Remove duplicated constant in include/elf/arc.hAndrew Burgess4-6/+11
In the include/elf/arc.h there are two constants that mask out the machine architecture field. One is used lots (EF_ARC_MACH_MSK), the other is used only once (EF_ARC_MACH). Remove EF_ARC_MACH. bfd/ChangeLog: * elf32-arc.c (arc_elf_final_write_processing): Switch to using EF_ARC_MACH_MSK. include/ChangeLog: * elf/arc.h (EF_ARC_MACH): Delete. (EF_ARC_MACH_MSK): Remove out of date comment.
2016-03-21arc/gas: default mach is arc700, initialised in md_beginAndrew Burgess8-50/+64
This commit restructures the selection of the default cpu/mach so that the choice is made from md_begin (if the user has not provided a command line choice). This will reduce the amount of change needed in a later patch. At the request of Synopsys, the default architecture changes to ARC700 from this commit, previously the default was a non-existent super-architecture that contained all instructions from all arc variants. There's some clean up associated with removing the default merged architecture, and a small test fix now that the default is ARC700. binutils/ChangeLog: * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700 to the architecture list. gas/ChangeLog: * config/tc-arc.c (arc_target): Delay initialisation until arc_select_cpu. (arc_target_name): Likewise. (arc_features): Likewise. (arc_mach_type): Likewise. (cpu_types): Remove "all" entry. (arc_select_cpu): New function, most of the content is from... (md_parse_option): ... here. Call new arc_select_cpu. (md_begin): Call arc_select_cpu if needed, default is now arc700. include/ChangeLog: * opcode/arc.h (ARC_OPCODE_BASE): Delete. opcodes/ChangeLog: * arc-opc.c (BASE): Delete.
2016-03-21gas/arc: Fix test for big-endian arcAndrew Burgess3-0/+15
The inline-data test checks the specific bytes laid down by the assembler, and so relies on the endianness of the target. I could change the expected results to be endian agnostic, however, I worried that a bug in the assembler that gets the endianness wrong would then slip through. Instead I add a new test for big-endian arc, and restrict the existing test to little-endian arc. gas/ChangeLog: * testsuite/gas/arc/inline-data-1.d: Add target restriction. * testsuite/gas/arc/inline-data-2.d: New file.
2016-03-21Remove use of alloca.Nick Clifton52-267/+410
bfd * warning.m4 (GCC_WARN_CFLAGS): Add -Wstack-usage=262144 * configure: Regenerate. * elf32-m68hc1x.c (elf32_m68hc11_relocate_section): Replace use of alloca with call to xmalloc. * elf32-nds32.c: Likewise. * elf64-hppa.c: Likewise. * elfxx-mips.c: Likewise. * pef.c: Likewise. * pei-x86_64.c: Likewise. * som.c: Likewise. * xsym.c: Likewise. binutils * dlltool.c: Replace use of alloca with call to xmalloc. * dllwrap.c: Likewise. * nlmconv.c: Likewise. * objdump.c: Likewise. * resrc.c: Likewise. * winduni.c: Likewise. * configure: Regenerate. gas * atof-generic.c: Replace use of alloca with call to xmalloc. * cgen.c: Likewise. * dwarf2dbg.c: Likewise. * macro.c: Likewise. * remap.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic30.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/te-vms.c: Likewise. * configure: Regenerate. ld * emultempl/msp430.em: Replace use of alloca with call to xmalloc. * plugin.c: Likewise. * pe-dll.c: Likewise.
2016-03-21ARM process record: median instructionsYao Qi2-0/+90
This patch is to support some ARM median instructions in process record. With this patch applied, these fails are fixed: -FAIL: gdb.reverse/break-precsave.exp: run to end of main -FAIL: gdb.reverse/break-precsave.exp: go to end of main forward -FAIL: gdb.reverse/break-precsave.exp: end of record log -FAIL: gdb.reverse/break-reverse.exp: continue to breakpoint: end -FAIL: gdb.reverse/break-reverse.exp: end of record log -FAIL: gdb.reverse/until-precsave.exp: run to end of main -FAIL: gdb.reverse/until-precsave.exp: advance to marker2 -FAIL: gdb.reverse/until-precsave.exp: until func, not called by current frame -FAIL: gdb.reverse/until-precsave.exp: reverse-advance to marker2 -FAIL: gdb.reverse/until-precsave.exp: reverse-finish from marker2 -FAIL: gdb.reverse/until-precsave.exp: reverse-advance to final return of factorial -FAIL: gdb.reverse/until-precsave.exp: reverse-until to entry of factorial -FAIL: gdb.reverse/until-reverse.exp: advance to marker2 -FAIL: gdb.reverse/until-reverse.exp: until func, not called by current frame -FAIL: gdb.reverse/until-reverse.exp: reverse-advance to marker2 -FAIL: gdb.reverse/until-reverse.exp: reverse-finish from marker2 -FAIL: gdb.reverse/until-reverse.exp: reverse-advance to final return of factorial -FAIL: gdb.reverse/until-reverse.exp: reverse-until to entry of factorial gdb: 2016-03-21 Yao Qi <yao.qi@linaro.org> * arm-tdep.c (arm_record_media): New. (arm_record_ld_st_reg_offset): Call arm_record_media.
2016-03-21Canonicalize more arm linux syscallsYao Qi2-10/+370
This patch is to canonicalize more syscalls on arm linux in process record. In this patch, I also comment out some syscalls which isn't handled by GDB now. With this patch applied, two fails are fixed. -FAIL: gdb.reverse/fstatat-reverse.exp: continue to breakpoint: marker2 -FAIL: gdb.reverse/recvmsg-reverse.exp: continue to breakpoint: marker2 gdb: 2016-03-21 Yao Qi <yao.qi@linaro.org> * arm-linux-tdep.c (arm_canonicalize_syscall): Canonicalize more syscalls.
2016-03-20Fix problem where gold cannot build .eh_frame_hdr from ld -r output.Cary Coutant7-12/+145
When running ld -r on objects that have comdat groups, when gold deduplicates a function in a comdat group, it removes the relocations from the EH information that referred to the dropped copy of the function. When running a final link using the result of the -r link, the missing relocation cause it to fail to recognize the FDE for the dropped function. This patch improves gold's FDE scanning to take into account the possibility that an FDE corresponds to a dropped function, and drops that FDE as well. Gnu ld, on the other hand, leaves the relocations in the ld -r output, but makes them R_NONE with an r_sym field of 0. This was sufficient to let both linkers recognize the FDE properly. With this fix, if you do an ld -r with gold, then do the final link with Gnu ld, the .eh_frame_hdr section will not be generated. To make it work with Gnu ld, we would have to leave the R_NONE relocations in, but I think it's better to drop the relocations entirely. I'd hope that if you're doing a -r link with gold, you'll also do the final link with gold. gold/ PR gold/19002 * ehframe.cc (Eh_frame::read_fde): Check for dropped functions. * testsuite/Makefile.am (eh_test_2): New test. * testsuite/Makefile.in: Regenerate. * testsuite/eh_test_2.sh: New test script. * testsuite/eh_test_a.cc (bar): Make it comdat. * testsuite/eh_test_b.cc (bar): Add a duplicate copy.
2016-03-21Automatic date update in version.inGDB Administrator1-1/+1
2016-03-20tc-i386.c: store encoded instructions in unsigned char[]Trevor Saunders2-33/+68
char can be a signed type, and some of the values in these arrays are greater than 0x80 which means they are outside of the range a signed char can store. Fortunately it seems most compilers handle this in the obvious way by storing the same bits as a negative number, but this is wierd and easily fixed. gas/ChangeLog: 2016-03-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * tc-i386.c (f32_1): Change type to unsigned char[]. (f32_2): Likewise. (f32_3): Likewise. (f32_4): Likewise. (f32_5): Likewise. (f32_6): Likewise. (f32_7): Likewise. (f32_8): Likewise. (f32_9): Likewise. (f32_10): Likewise. (f32_11): Likewise. (f32_12): Likewise. (f32_13): Likewise. (f32_14): Likewise. (f16_3): Likewise. (f16_4): Likewise. (f16_5): Likewise. (f16_6): Likewise. (f16_7): Likewise. (f16_8): Likewise. (jump_31): Likewise. (f32_patt): Likewise. (f16_patt): Likewise. (alt_3): Likewise. (alt_4): Likewise. (alt_5): Likewise. (alt_6): Likewise. (alt_7): Likewise. (alt_8): Likewise. (alt_9): Likewise. (alt_10): Likewise. (alt_patt): Likewise.
2016-03-20Automatic date update in version.inGDB Administrator1-1/+1
generated by cgit v1.1 at 2025-03-11 03:56:57 +0000