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2021-05-03PR27755, powerpc-ld infinite loopbinutils-2_34-branchAlan Modra2-1/+6
PR 27755 * elf32-ppc.c (ppc_elf_inline_plt): Do increment rel in loop. (cherry picked from commit 337d0bf887a3ed6b6b2123fecfec0736640edcaf)
2020-11-19gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm modeAndre Vieira3-2/+16
This patch fixes a mistake when enabling MVE instructions that disabled support for single precision vmla and vmul for arm mode. gas/ChangeLog: 2020-11-19 Andre Vieira <andre.simoesdiasvieira@arm.com> Backport from mainline. 2020-11-12 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 26858 * config/tc-arm.c (asm_opcode insns): Fix vmul and vmla's ARM_VARIANT. * testsuite/gas/arm/pr26858.s: New test. * testsuite/gas/arm/pr26858.d: New test.
2020-10-07x86: Update GNU property testsH.J. Lu7-0/+16
Update property tests for glibc compiled by Fedora binary annotation plugin for GCC, which may insert additonal GNU properties: x86 ISA needed: SSE, SSE2 * testsuite/ld-i386/property-3.r: Updated for Fedora binary annotation plugin for GCC. * testsuite/ld-i386/property-4.r: Likewise. * testsuite/ld-i386/property-5.r: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. (cherry picked from commit f95f5adb9a50a27639a811c540c008e776aee46d)
2020-10-07x86: Properly merge -z ibt and -z shstkH.J. Lu15-12/+173
Merge -z ibt and -z shstk only with GNU_PROPERTY_X86_FEATURE_1_AND, not any GNU_PROPERTY_X86_UINT32_AND_XXX properties. bfd/ PR ld/26711 * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Merge -z ibt and -z shstk only with GNU_PROPERTY_X86_FEATURE_1_AND. ld/ PR ld/26711 * testsuite/ld-i386/i386.exp: Run ld/26711 tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr26711-1.d: Likewise. * testsuite/ld-i386/pr26711-2.d: Likewise. * testsuite/ld-i386/pr26711-3.d: Likewise. * testsuite/ld-x86-64/pr26711-1-x32.d: Likewise. * testsuite/ld-x86-64/pr26711-1.d: Likewise. * testsuite/ld-x86-64/pr26711-2-x32.d: Likewise. * testsuite/ld-x86-64/pr26711-2.d: Likewise. * testsuite/ld-x86-64/pr26711-3-x32.d: Likewise. * testsuite/ld-x86-64/pr26711-3.d: Likewise. * testsuite/ld-x86-64/pr26711.s: Likewise. (cherry picked from commit 574df58f5295ef2728526e6a73b5f429b05f2a8c)
2020-09-10PowerPC TPREL_HA/LO optimisationAlan Modra17-200/+442
ppc64 ld optimises sequences like the following addis 3,13,wot@tprel@ha lwz 3,wot@tprel@l(3) to nop lwz 3,wot@tprel(13) when "wot" is located near enough to the thread pointer. However, the ABI doesn't require that R_PPC64_TPREL16_HA always be on an addis rt,13,imm instruction, and while ld checked for that on the high-part instruction it didn't disable the optimisation on the low-part instruction. This patch fixes that problem, disabling the tprel optimisation globally if high-part instructions don't pass sanity checks. The optimisation is also enabled for ppc32, where before ld.bfd had the code in the wrong place and ld.gold had it in a block only enabled for ppc64. bfd/ * elf32-ppc.c (ppc_elf_check_relocs): Set has_tls_reloc for high part tprel16 relocs. (ppc_elf_tls_optimize): Sanity check high part tprel16 relocs. Clear do_tls_opt on odd instructions. (ppc_elf_relocate_section): Move TPREL16_HA/LO optimisation later. Don't sanity check them here. * elf64-ppc.c (ppc64_elf_check_relocs): Set has_tls_reloc for high part tprel16 relocs. (ppc64_elf_tls_optimize): Sanity check high part tprel16 relocs. Clear do_tls_opt on odd instructions. (ppc64_elf_relocate_section): Don't sanity check TPREL16_HA. ld/ * testsuite/ld-powerpc/tls32.d: Update for TPREL_HA/LO optimisation. * testsuite/ld-powerpc/tlsexe32.d: Likewise. * testsuite/ld-powerpc/tlsldopt32.d: Likewise. * testsuite/ld-powerpc/tlsmark32.d: Likewise. * testsuite/ld-powerpc/tlsopt4_32.d: Likewise. * testsuite/ld-powerpc/tprel.s, * testsuite/ld-powerpc/tprel.d, * testsuite/ld-powerpc/tprel32.d: New tests. * testsuite/ld-powerpc/tprelbad.s, * testsuite/ld-powerpc/tprelbad.d: New test. * testsuite/ld-powerpc/powerpc.exp: Run them. gold/ * powerpc.cc (Target_powerpc): Add tprel_opt_ and accessors. (Target_powerpc::Scan::local): Sanity check tprel high relocs. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Control tprel optimisation with tprel_opt_ and enable for 32-bit. (cherry picked from commit 252dcdf432c67f6baafb766ed068c64db1eb2bad)
2020-09-10Date updateAlan Modra1-1/+1
2020-08-11aarch64: set sh_entsize of .plt to 0Szabolcs Nagy2-6/+15
On aarch64 the first PLT entry is 32 bytes, subsequent entries are 16 bytes by default but can be 24 bytes with BTI or with PAC-PLT. sh_entsize of .plt was set to the PLT entry size, so in some cases sh_size % sh_entsize != 0, which breaks some tools. Note that PLT0 (and the TLSDESC stub code which is also in the PLT) were historically not padded up to meet the sh_size requirement, but to ensure that PLT stub code is aligned on cache lines. Similar layout is present on other targets too which just happens to make sh_size a multiple of sh_entsize and it is not expected that sh_entsize of .plt is used for anything. This patch sets sh_entsize of .plt to 0: the section does not hold a table of fixed-size entries so other values are not conforming in principle to the ELF spec. bfd/ChangeLog: Backport from mainline. 2020-07-30 Szabolcs Nagy <szabolcs.nagy@arm.com> PR ld/26312 * elfnn-aarch64.c (elfNN_aarch64_init_small_plt0_entry): Set sh_entsize to 0. (elfNN_aarch64_finish_dynamic_sections): Remove sh_entsize setting. (cherry picked from commit 4d3bb35620e70d543d438bf21be1307f7ea0f5d0)
2020-07-06S/390: z13: Accept vector alignment hintsStefan Schulze Frielinghaus5-20/+42
Accept vector alignment hints on z13 although they are ignored there. The advantage is that any binary compiled for architecture level z13 may run on z14 or later and benefit from vector alignment hints. Backport from mainline. gas/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector load/store instruction variants with alignment hints. * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store instruction variants with alignment hints. opcodes/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * s390-opc.txt: Relocate vector load/store instructions with additional alignment parameter and change architecture level constraint from z14 to z13.
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2020-06-10gas: Fix checking for backwards .org with negative offsetAlex Coplan8-2/+29
This patch fixes internal errors in (at least) arm and aarch64 GAS when assembling code that attempts a negative .org. The bug appears to be a regression introduced in binutils-2.29 by commit 9875b36538d. * write.c (relax_segment): Fix handling of negative offset when relaxing an rs_org frag. * testsuite/gas/aarch64/org-neg.d: New test. * testsuite/gas/aarch64/org-neg.l: Error output for test. * testsuite/gas/aarch64/org-neg.s: Input for test. * testsuite/gas/arm/org-neg.d: New test. * testsuite/gas/arm/org-neg.l: Error output for test. * testsuite/gas/arm/org-neg.s: Input for test. (cherry picked from commit c39c821c1da3e8a64eff5984a39e104eb798e8b8)
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2020-06-03Prevent a potential use-after-fee memory corruption bug in the linker (for ↵Nick Clifton3-12/+48
PE format files). PR 25993 * emultempl/pe.em (_after_open): Check for duplicate filename pointers before renaming the dll. * emultempl/pep.em (_after_open): Likewise.
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