diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/sparc/.Sanitize | 4 | ||||
| -rw-r--r-- | sim/sparc/ChangeLog | 32 | ||||
| -rw-r--r-- | sim/sparc/Makefile.in | 45 | ||||
| -rw-r--r-- | sim/sparc/acconfig.h | 3 | ||||
| -rw-r--r-- | sim/sparc/arch.c | 2428 | ||||
| -rw-r--r-- | sim/sparc/arch.h | 149 | ||||
| -rw-r--r-- | sim/sparc/cpu32.h | 618 | ||||
| -rw-r--r-- | sim/sparc/decode32.c | 1278 | ||||
| -rw-r--r-- | sim/sparc/decode32.h | 285 | ||||
| -rw-r--r-- | sim/sparc/dev64.c | 9 | ||||
| -rw-r--r-- | sim/sparc/dev64.h | 21 | ||||
| -rw-r--r-- | sim/sparc/model32.c | 3516 | ||||
| -rw-r--r-- | sim/sparc/sem32.c | 5444 | ||||
| -rw-r--r-- | sim/sparc/sparc64.c | 264 | ||||
| -rw-r--r-- | sim/sparc/trap64.h | 86 |
15 files changed, 14168 insertions, 14 deletions
diff --git a/sim/sparc/.Sanitize b/sim/sparc/.Sanitize index e60cadc..e1076ad 100644 --- a/sim/sparc/.Sanitize +++ b/sim/sparc/.Sanitize @@ -38,6 +38,8 @@ decode32.c decode32.h dev32.c dev32.h +dev64.c +dev64.h mloop32.in model32.c regs32.h @@ -47,9 +49,11 @@ sim-main.h sparc-sim.h sparc.c sparc32.c +sparc64.c tconfig.in trap32.c trap32.h +trap64.h Things-to-lose: diff --git a/sim/sparc/ChangeLog b/sim/sparc/ChangeLog new file mode 100644 index 0000000..b686496 --- /dev/null +++ b/sim/sparc/ChangeLog @@ -0,0 +1,32 @@ +1999-02-09 Doug Evans <devans@casey.cygnus.com> + + * Makefile.in (SPARC64_OBJS): Add dev64.o. + (CPU_OBJS): New variable. + (SIM_OBJS): Add sparc-desc.o. + (SIM_EXTRA_DEPS): Replace cpu-opc.h with sparc-desc.h. + (sim-core.o): Add dev64.h dependency. + (dev64.o): Add rule. + (stamp-arch,stamp-cpu32): Update FLAGS variable, option syntax changed. + (stamp-cpu64): Ditto. + (stamp-desc): New rule. + * configure.in (sim_link_files,sim_link_links): Delete. + Set cpu_objs to one of SPARC32_OBJS,SPARC64_OBJS. + * configure: Rebuild. + * acconfig.h: Rebuild. + * config.in: Rebuild. + * dev64.c: New file. + * dev64.h: New file. + * sparc64.c: New file. + * trap64.h: New file. + * arch.c,arch.h,cpuall.h: Rebuild. + * cpu32.c,decode32.c,decode32.h,model32.c,sem32.c: Rebuild. + * sim-if.c (sparc_disassemble_insn): New function. + (sim_open): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. + Set disassembler. + (sim_close): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. + * sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include + sparc-desc.h,sparc-opc.h,sparc-sim.h. + +1999-02-02 Doug Evans <devans@casey.cygnus.com> + + * Directory created. diff --git a/sim/sparc/Makefile.in b/sim/sparc/Makefile.in index e708a0c..5c33f89 100644 --- a/sim/sparc/Makefile.in +++ b/sim/sparc/Makefile.in @@ -4,7 +4,10 @@ ## COMMON_PRE_CONFIG_FRAG SPARC32_OBJS = sparc32.o trap32.o dev32.o cpu32.o decode32.o model32.o mloop32.o sem32.o -SPARC64_OBJS = sparc64.o trap64.o cpu64.o decode64.o model64.o mloop64.o sem64.o +SPARC64_OBJS = sparc64.o trap64.o dev64.o cpu64.o decode64.o model64.o mloop64.o sem64.o + +# Set to one of SPARC32_OBJS/SPARC64_OBJS. +CPU_OBJS = @cpu_objs@ SIM_OBJS = \ $(SIM_NEW_COMMON_OBJS) \ @@ -15,14 +18,14 @@ SIM_OBJS = \ sim-reg.o \ cgen-utils.o cgen-trace.o cgen-scache.o \ cgen-run.o sim-reason.o sim-engine.o sim-stop.o \ - sim-if.o sparc.o arch.o \ - $(SPARC32_OBJS) + sim-if.o sparc.o arch.o sparc-desc.o \ + $(CPU_OBJS) # Extra headers included by sim-main.h. # This plus sim_main_headers is used by Make-common.in for files in common. SIM_EXTRA_DEPS = \ $(CGEN_INCLUDE_DEPS) \ - arch.h cpuall.h cpu-opc.h + arch.h cpuall.h sparc-desc.h # sparc-sim.h kept out for now (too much unnecessary recompilation) SIM_EXTRA_CFLAGS = @@ -37,7 +40,8 @@ NL_TARGET = -DNL_TARGET_sparc arch = sparc -sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h dev32.h +sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h \ + dev32.h dev64.h sparc.o: sparc.c $(SIM_MAIN_DEPS) \ $(srcdir)/../common/cgen-mem.h \ $(srcdir)/../common/cgen-ops.h @@ -81,6 +85,7 @@ SPARC64_INCLUDE_DEPS = \ sparc64.o: sparc64.c $(SPARC64_INCLUDE_DEPS) trap64.o: trap64.c $(SPARC64_INCLUDE_DEPS) +dev64.o: dev64.c $(SPARC32_INCLUDE_DEPS) dev64.h # FIXME: Use of `mono' is wip. mloop64.c eng64.h: stamp-mloop64 @@ -98,38 +103,50 @@ decode64.o: decode64.c $(SPARC64_INCLUDE_DEPS) model64.o: model64.c $(SPARC64_INCLUDE_DEPS) sparc-clean: - rm -f mloop32.c eng32.h mloop64.c eng64.h stamp-mloop32 stamp-mloop64 - rm -f stamp-arch stamp-cpu32 stamp-cpu64 + rm -f mloop32.c eng32.h stamp-mloop32 + rm -f mloop64.c eng64.h stamp-mloop64 + rm -f stamp-arch stamp-cpu32 stamp-cpu64 stamp-desc rm -f tmp-* # cgen support -stamp-arch: $(CGEN_MAIN_SCM) $(CGEN_ARCH_SCM) \ +stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) \ $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu \ $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu - $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=sparc-v8,sparclite + $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \ + mach=sparc-v8,sparclite,sparc-v9 \ + FLAGS="copyright=cygnus package=cygsim" touch stamp-arch arch.h arch.c cpuall.h: $(CGEN_MAIN) stamp-arch @true # Add with-scache to FLAGS when switching to -pbb. -stamp-cpu32: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \ +stamp-cpu32: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \ $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ cpu=sparc32 mach=sparc-v8,sparclite SUFFIX=32 \ - FLAGS="with-profile fn" \ + FLAGS="with-profile=fn copyright=cygnus package=cygsim" \ EXTRAFILES="$(CGEN_CPU_SEM)" touch stamp-cpu32 cpu32.h decode32.h decode32.c model32.c sem32.c sem32-switch.c: $(CGEN_MAINT) stamp-cpu32 @true # Add with-scache to FLAGS when switching to -pbb. -stamp-cpu64: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \ +stamp-cpu64: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \ $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc64.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=sparc64 mach=sparc-v9,sparc-v9a SUFFIX=64 \ - FLAGS="with-profile fn" \ + cpu=sparc64 mach=sparc-v9 SUFFIX=64 \ + FLAGS="with-profile=fn copyright=cygnus package=cygsim" \ EXTRAFILES="$(CGEN_CPU_SEM)" touch stamp-cpu64 cpu64.h decode64.h decode64.c model64.c sem64.c sem64-switch.c: $(CGEN_MAINT) stamp-cpu64 @true + +stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \ + $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu + $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \ + cpu=sparc mach=all \ + FLAGS="copyright=cygnus package=cygsim" + touch stamp-desc +sparc-desc.c sparc-desc.h sparc-opc: $(CGEN_MAINT) stamp-desc + @true diff --git a/sim/sparc/acconfig.h b/sim/sparc/acconfig.h index f9b87a1..27a2a2f 100644 --- a/sim/sparc/acconfig.h +++ b/sim/sparc/acconfig.h @@ -13,3 +13,6 @@ /* Define if your locale.h file contains LC_MESSAGES. */ #undef HAVE_LC_MESSAGES + +/* Define if sparc64 target. */ +#undef SPARC64_P diff --git a/sim/sparc/arch.c b/sim/sparc/arch.c new file mode 100644 index 0000000..5970e8c --- /dev/null +++ b/sim/sparc/arch.c @@ -0,0 +1,2428 @@ +/* Simulator support for sparc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#include "sim-main.h" +#include "bfd.h" + +const MACH *sim_machs[] = +{ +#ifdef HAVE_CPU_SPARC32 + & sparc_v8_mach, +#endif +#ifdef HAVE_CPU_SPARC32 + & sparclite_mach, +#endif +#ifdef HAVE_CPU_SPARC64 + & sparc_v9_mach, +#endif + 0 +}; + +/* Get the value of h-pc. */ + +USI +a_sparc_h_pc_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_pc_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_pc_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_pc_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-pc. */ + +void +a_sparc_h_pc_set (SIM_CPU *current_cpu, USI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_pc_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_pc_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_pc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-npc. */ + +SI +a_sparc_h_npc_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_npc_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_npc_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_npc_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-npc. */ + +void +a_sparc_h_npc_set (SIM_CPU *current_cpu, SI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_npc_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_npc_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_npc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-gr. */ + +SI +a_sparc_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_gr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_gr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_gr_get (current_cpu, regno); +#endif + default : + abort (); + } +} + +/* Set a value for h-gr. */ + +void +a_sparc_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_gr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_gr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_gr_set (current_cpu, regno, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-icc-c. */ + +BI +a_sparc_h_icc_c_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_icc_c_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_icc_c_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_icc_c_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-icc-c. */ + +void +a_sparc_h_icc_c_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_icc_c_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_icc_c_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_icc_c_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-icc-n. */ + +BI +a_sparc_h_icc_n_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_icc_n_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_icc_n_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_icc_n_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-icc-n. */ + +void +a_sparc_h_icc_n_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_icc_n_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_icc_n_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_icc_n_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-icc-v. */ + +BI +a_sparc_h_icc_v_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_icc_v_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_icc_v_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_icc_v_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-icc-v. */ + +void +a_sparc_h_icc_v_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_icc_v_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_icc_v_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_icc_v_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-icc-z. */ + +BI +a_sparc_h_icc_z_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_icc_z_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_icc_z_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_icc_z_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-icc-z. */ + +void +a_sparc_h_icc_z_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_icc_z_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_icc_z_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_icc_z_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-xcc-c. */ + +BI +a_sparc_h_xcc_c_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_xcc_c_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_xcc_c_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_xcc_c_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-xcc-c. */ + +void +a_sparc_h_xcc_c_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_xcc_c_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_xcc_c_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_xcc_c_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-xcc-n. */ + +BI +a_sparc_h_xcc_n_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_xcc_n_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_xcc_n_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_xcc_n_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-xcc-n. */ + +void +a_sparc_h_xcc_n_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_xcc_n_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_xcc_n_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_xcc_n_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-xcc-v. */ + +BI +a_sparc_h_xcc_v_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_xcc_v_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_xcc_v_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_xcc_v_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-xcc-v. */ + +void +a_sparc_h_xcc_v_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_xcc_v_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_xcc_v_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_xcc_v_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-xcc-z. */ + +BI +a_sparc_h_xcc_z_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_xcc_z_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_xcc_z_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_xcc_z_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-xcc-z. */ + +void +a_sparc_h_xcc_z_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_xcc_z_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_xcc_z_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_xcc_z_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-y. */ + +SI +a_sparc_h_y_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_y_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_y_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_y_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-y. */ + +void +a_sparc_h_y_set (SIM_CPU *current_cpu, SI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_y_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_y_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_y_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-asr. */ + +SI +a_sparc_h_asr_get (SIM_CPU *current_cpu, UINT regno) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_asr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_asr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_asr_get (current_cpu, regno); +#endif + default : + abort (); + } +} + +/* Set a value for h-asr. */ + +void +a_sparc_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_asr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_asr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_asr_set (current_cpu, regno, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-annul-p. */ + +BI +a_sparc_h_annul_p_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_annul_p_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_annul_p_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_annul_p_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-annul-p. */ + +void +a_sparc_h_annul_p_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_annul_p_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_annul_p_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_annul_p_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fr. */ + +SF +a_sparc_h_fr_get (SIM_CPU *current_cpu, UINT regno) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_fr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_fr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fr_get (current_cpu, regno); +#endif + default : + abort (); + } +} + +/* Set a value for h-fr. */ + +void +a_sparc_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_fr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_fr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fr_set (current_cpu, regno, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-psr. */ + +USI +a_sparc_h_psr_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_psr_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_psr_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_psr_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-psr. */ + +void +a_sparc_h_psr_set (SIM_CPU *current_cpu, USI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_psr_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_psr_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_psr_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-s. */ + +BI +a_sparc_h_s_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_s_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_s_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_s_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-s. */ + +void +a_sparc_h_s_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_s_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_s_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_s_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-ps. */ + +BI +a_sparc_h_ps_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_ps_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_ps_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_ps_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-ps. */ + +void +a_sparc_h_ps_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_ps_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_ps_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_ps_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-pil. */ + +UQI +a_sparc_h_pil_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_pil_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_pil_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_pil_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-pil. */ + +void +a_sparc_h_pil_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_pil_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_pil_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_pil_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-et. */ + +BI +a_sparc_h_et_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_et_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_et_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_et_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-et. */ + +void +a_sparc_h_et_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_et_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_et_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_et_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tbr. */ + +SI +a_sparc_h_tbr_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_tbr_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_tbr_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tbr_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tbr. */ + +void +a_sparc_h_tbr_set (SIM_CPU *current_cpu, SI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_tbr_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_tbr_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tbr_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-cwp. */ + +UQI +a_sparc_h_cwp_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_cwp_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_cwp_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_cwp_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-cwp. */ + +void +a_sparc_h_cwp_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_cwp_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_cwp_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_cwp_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-wim. */ + +USI +a_sparc_h_wim_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_wim_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_wim_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_wim_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-wim. */ + +void +a_sparc_h_wim_set (SIM_CPU *current_cpu, USI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_wim_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_wim_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_wim_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-ag. */ + +QI +a_sparc_h_ag_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_ag_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_ag_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_ag_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-ag. */ + +void +a_sparc_h_ag_set (SIM_CPU *current_cpu, QI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_ag_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_ag_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_ag_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-ec. */ + +BI +a_sparc_h_ec_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_ec_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_ec_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_ec_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-ec. */ + +void +a_sparc_h_ec_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_ec_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_ec_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_ec_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-ef. */ + +BI +a_sparc_h_ef_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_ef_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_ef_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_ef_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-ef. */ + +void +a_sparc_h_ef_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_ef_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_ef_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_ef_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr. */ + +USI +a_sparc_h_fsr_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + return sparc32_h_fsr_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + return sparc32_h_fsr_get (current_cpu); +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr. */ + +void +a_sparc_h_fsr_set (SIM_CPU *current_cpu, USI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc : + sparc32_h_fsr_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC32 + case bfd_mach_sparc_sparclite : + sparc32_h_fsr_set (current_cpu, newval); + break; +#endif +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-ver. */ + +UDI +a_sparc_h_ver_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_ver_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-ver. */ + +void +a_sparc_h_ver_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_ver_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-pstate. */ + +UDI +a_sparc_h_pstate_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_pstate_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-pstate. */ + +void +a_sparc_h_pstate_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_pstate_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tba. */ + +UDI +a_sparc_h_tba_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tba_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tba. */ + +void +a_sparc_h_tba_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tba_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tt. */ + +UDI +a_sparc_h_tt_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tt_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tt. */ + +void +a_sparc_h_tt_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tt_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-asi. */ + +UQI +a_sparc_h_asi_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_asi_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-asi. */ + +void +a_sparc_h_asi_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_asi_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tl. */ + +UQI +a_sparc_h_tl_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tl_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tl. */ + +void +a_sparc_h_tl_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tl_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tpc. */ + +UDI +a_sparc_h_tpc_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tpc_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tpc. */ + +void +a_sparc_h_tpc_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tpc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tnpc. */ + +UDI +a_sparc_h_tnpc_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tnpc_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tnpc. */ + +void +a_sparc_h_tnpc_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tnpc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tstate. */ + +UDI +a_sparc_h_tstate_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tstate_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tstate. */ + +void +a_sparc_h_tstate_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tstate_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-tick. */ + +UDI +a_sparc_h_tick_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_tick_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-tick. */ + +void +a_sparc_h_tick_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_tick_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-cansave. */ + +UDI +a_sparc_h_cansave_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_cansave_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-cansave. */ + +void +a_sparc_h_cansave_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_cansave_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-canrestore. */ + +UDI +a_sparc_h_canrestore_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_canrestore_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-canrestore. */ + +void +a_sparc_h_canrestore_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_canrestore_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-otherwin. */ + +UDI +a_sparc_h_otherwin_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_otherwin_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-otherwin. */ + +void +a_sparc_h_otherwin_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_otherwin_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-cleanwin. */ + +UDI +a_sparc_h_cleanwin_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_cleanwin_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-cleanwin. */ + +void +a_sparc_h_cleanwin_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_cleanwin_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-wstate. */ + +UDI +a_sparc_h_wstate_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_wstate_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-wstate. */ + +void +a_sparc_h_wstate_set (SIM_CPU *current_cpu, UDI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_wstate_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fcc0. */ + +UQI +a_sparc_h_fcc0_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fcc0_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fcc0. */ + +void +a_sparc_h_fcc0_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fcc0_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fcc1. */ + +UQI +a_sparc_h_fcc1_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fcc1_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fcc1. */ + +void +a_sparc_h_fcc1_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fcc1_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fcc2. */ + +UQI +a_sparc_h_fcc2_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fcc2_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fcc2. */ + +void +a_sparc_h_fcc2_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fcc2_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fcc3. */ + +UQI +a_sparc_h_fcc3_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fcc3_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fcc3. */ + +void +a_sparc_h_fcc3_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fcc3_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-rd. */ + +UQI +a_sparc_h_fsr_rd_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_rd_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-rd. */ + +void +a_sparc_h_fsr_rd_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_rd_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-tem. */ + +UQI +a_sparc_h_fsr_tem_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_tem_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-tem. */ + +void +a_sparc_h_fsr_tem_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_tem_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-ns. */ + +BI +a_sparc_h_fsr_ns_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_ns_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-ns. */ + +void +a_sparc_h_fsr_ns_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_ns_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-ver. */ + +UQI +a_sparc_h_fsr_ver_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_ver_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-ver. */ + +void +a_sparc_h_fsr_ver_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_ver_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-ftt. */ + +UQI +a_sparc_h_fsr_ftt_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_ftt_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-ftt. */ + +void +a_sparc_h_fsr_ftt_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_ftt_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-qne. */ + +BI +a_sparc_h_fsr_qne_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_qne_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-qne. */ + +void +a_sparc_h_fsr_qne_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_qne_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-aexc. */ + +UQI +a_sparc_h_fsr_aexc_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_aexc_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-aexc. */ + +void +a_sparc_h_fsr_aexc_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_aexc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fsr-cexc. */ + +UQI +a_sparc_h_fsr_cexc_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fsr_cexc_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fsr-cexc. */ + +void +a_sparc_h_fsr_cexc_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fsr_cexc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fpsr-fef. */ + +BI +a_sparc_h_fpsr_fef_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fpsr_fef_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fpsr-fef. */ + +void +a_sparc_h_fpsr_fef_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fpsr_fef_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fpsr-du. */ + +BI +a_sparc_h_fpsr_du_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fpsr_du_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fpsr-du. */ + +void +a_sparc_h_fpsr_du_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fpsr_du_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fpsr-dl. */ + +BI +a_sparc_h_fpsr_dl_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fpsr_dl_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fpsr-dl. */ + +void +a_sparc_h_fpsr_dl_set (SIM_CPU *current_cpu, BI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fpsr_dl_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + +/* Get the value of h-fpsr. */ + +UQI +a_sparc_h_fpsr_get (SIM_CPU *current_cpu) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + return sparc64_h_fpsr_get (current_cpu); +#endif + default : + abort (); + } +} + +/* Set a value for h-fpsr. */ + +void +a_sparc_h_fpsr_set (SIM_CPU *current_cpu, UQI newval) +{ + switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) + { +#ifdef HAVE_CPU_SPARC64 + case bfd_mach_sparc_v9 : + sparc64_h_fpsr_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + diff --git a/sim/sparc/arch.h b/sim/sparc/arch.h new file mode 100644 index 0000000..704f9b3 --- /dev/null +++ b/sim/sparc/arch.h @@ -0,0 +1,149 @@ +/* Simulator header for sparc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#ifndef SPARC_ARCH_H +#define SPARC_ARCH_H + +#define TARGET_BIG_ENDIAN 1 + +/* Cover fns for register access. */ +USI a_sparc_h_pc_get (SIM_CPU *); +void a_sparc_h_pc_set (SIM_CPU *, USI); +SI a_sparc_h_npc_get (SIM_CPU *); +void a_sparc_h_npc_set (SIM_CPU *, SI); +SI a_sparc_h_gr_get (SIM_CPU *, UINT); +void a_sparc_h_gr_set (SIM_CPU *, UINT, SI); +BI a_sparc_h_icc_c_get (SIM_CPU *); +void a_sparc_h_icc_c_set (SIM_CPU *, BI); +BI a_sparc_h_icc_n_get (SIM_CPU *); +void a_sparc_h_icc_n_set (SIM_CPU *, BI); +BI a_sparc_h_icc_v_get (SIM_CPU *); +void a_sparc_h_icc_v_set (SIM_CPU *, BI); +BI a_sparc_h_icc_z_get (SIM_CPU *); +void a_sparc_h_icc_z_set (SIM_CPU *, BI); +BI a_sparc_h_xcc_c_get (SIM_CPU *); +void a_sparc_h_xcc_c_set (SIM_CPU *, BI); +BI a_sparc_h_xcc_n_get (SIM_CPU *); +void a_sparc_h_xcc_n_set (SIM_CPU *, BI); +BI a_sparc_h_xcc_v_get (SIM_CPU *); +void a_sparc_h_xcc_v_set (SIM_CPU *, BI); +BI a_sparc_h_xcc_z_get (SIM_CPU *); +void a_sparc_h_xcc_z_set (SIM_CPU *, BI); +SI a_sparc_h_y_get (SIM_CPU *); +void a_sparc_h_y_set (SIM_CPU *, SI); +SI a_sparc_h_asr_get (SIM_CPU *, UINT); +void a_sparc_h_asr_set (SIM_CPU *, UINT, SI); +BI a_sparc_h_annul_p_get (SIM_CPU *); +void a_sparc_h_annul_p_set (SIM_CPU *, BI); +SF a_sparc_h_fr_get (SIM_CPU *, UINT); +void a_sparc_h_fr_set (SIM_CPU *, UINT, SF); +USI a_sparc_h_psr_get (SIM_CPU *); +void a_sparc_h_psr_set (SIM_CPU *, USI); +BI a_sparc_h_s_get (SIM_CPU *); +void a_sparc_h_s_set (SIM_CPU *, BI); +BI a_sparc_h_ps_get (SIM_CPU *); +void a_sparc_h_ps_set (SIM_CPU *, BI); +UQI a_sparc_h_pil_get (SIM_CPU *); +void a_sparc_h_pil_set (SIM_CPU *, UQI); +BI a_sparc_h_et_get (SIM_CPU *); +void a_sparc_h_et_set (SIM_CPU *, BI); +SI a_sparc_h_tbr_get (SIM_CPU *); +void a_sparc_h_tbr_set (SIM_CPU *, SI); +UQI a_sparc_h_cwp_get (SIM_CPU *); +void a_sparc_h_cwp_set (SIM_CPU *, UQI); +USI a_sparc_h_wim_get (SIM_CPU *); +void a_sparc_h_wim_set (SIM_CPU *, USI); +QI a_sparc_h_ag_get (SIM_CPU *); +void a_sparc_h_ag_set (SIM_CPU *, QI); +BI a_sparc_h_ec_get (SIM_CPU *); +void a_sparc_h_ec_set (SIM_CPU *, BI); +BI a_sparc_h_ef_get (SIM_CPU *); +void a_sparc_h_ef_set (SIM_CPU *, BI); +USI a_sparc_h_fsr_get (SIM_CPU *); +void a_sparc_h_fsr_set (SIM_CPU *, USI); +UDI a_sparc_h_ver_get (SIM_CPU *); +void a_sparc_h_ver_set (SIM_CPU *, UDI); +UDI a_sparc_h_pstate_get (SIM_CPU *); +void a_sparc_h_pstate_set (SIM_CPU *, UDI); +UDI a_sparc_h_tba_get (SIM_CPU *); +void a_sparc_h_tba_set (SIM_CPU *, UDI); +UDI a_sparc_h_tt_get (SIM_CPU *); +void a_sparc_h_tt_set (SIM_CPU *, UDI); +UQI a_sparc_h_asi_get (SIM_CPU *); +void a_sparc_h_asi_set (SIM_CPU *, UQI); +UQI a_sparc_h_tl_get (SIM_CPU *); +void a_sparc_h_tl_set (SIM_CPU *, UQI); +UDI a_sparc_h_tpc_get (SIM_CPU *); +void a_sparc_h_tpc_set (SIM_CPU *, UDI); +UDI a_sparc_h_tnpc_get (SIM_CPU *); +void a_sparc_h_tnpc_set (SIM_CPU *, UDI); +UDI a_sparc_h_tstate_get (SIM_CPU *); +void a_sparc_h_tstate_set (SIM_CPU *, UDI); +UDI a_sparc_h_tick_get (SIM_CPU *); +void a_sparc_h_tick_set (SIM_CPU *, UDI); +UDI a_sparc_h_cansave_get (SIM_CPU *); +void a_sparc_h_cansave_set (SIM_CPU *, UDI); +UDI a_sparc_h_canrestore_get (SIM_CPU *); +void a_sparc_h_canrestore_set (SIM_CPU *, UDI); +UDI a_sparc_h_otherwin_get (SIM_CPU *); +void a_sparc_h_otherwin_set (SIM_CPU *, UDI); +UDI a_sparc_h_cleanwin_get (SIM_CPU *); +void a_sparc_h_cleanwin_set (SIM_CPU *, UDI); +UDI a_sparc_h_wstate_get (SIM_CPU *); +void a_sparc_h_wstate_set (SIM_CPU *, UDI); +UQI a_sparc_h_fcc0_get (SIM_CPU *); +void a_sparc_h_fcc0_set (SIM_CPU *, UQI); +UQI a_sparc_h_fcc1_get (SIM_CPU *); +void a_sparc_h_fcc1_set (SIM_CPU *, UQI); +UQI a_sparc_h_fcc2_get (SIM_CPU *); +void a_sparc_h_fcc2_set (SIM_CPU *, UQI); +UQI a_sparc_h_fcc3_get (SIM_CPU *); +void a_sparc_h_fcc3_set (SIM_CPU *, UQI); +UQI a_sparc_h_fsr_rd_get (SIM_CPU *); +void a_sparc_h_fsr_rd_set (SIM_CPU *, UQI); +UQI a_sparc_h_fsr_tem_get (SIM_CPU *); +void a_sparc_h_fsr_tem_set (SIM_CPU *, UQI); +BI a_sparc_h_fsr_ns_get (SIM_CPU *); +void a_sparc_h_fsr_ns_set (SIM_CPU *, BI); +UQI a_sparc_h_fsr_ver_get (SIM_CPU *); +void a_sparc_h_fsr_ver_set (SIM_CPU *, UQI); +UQI a_sparc_h_fsr_ftt_get (SIM_CPU *); +void a_sparc_h_fsr_ftt_set (SIM_CPU *, UQI); +BI a_sparc_h_fsr_qne_get (SIM_CPU *); +void a_sparc_h_fsr_qne_set (SIM_CPU *, BI); +UQI a_sparc_h_fsr_aexc_get (SIM_CPU *); +void a_sparc_h_fsr_aexc_set (SIM_CPU *, UQI); +UQI a_sparc_h_fsr_cexc_get (SIM_CPU *); +void a_sparc_h_fsr_cexc_set (SIM_CPU *, UQI); +BI a_sparc_h_fpsr_fef_get (SIM_CPU *); +void a_sparc_h_fpsr_fef_set (SIM_CPU *, BI); +BI a_sparc_h_fpsr_du_get (SIM_CPU *); +void a_sparc_h_fpsr_du_set (SIM_CPU *, BI); +BI a_sparc_h_fpsr_dl_get (SIM_CPU *); +void a_sparc_h_fpsr_dl_set (SIM_CPU *, BI); +UQI a_sparc_h_fpsr_get (SIM_CPU *); +void a_sparc_h_fpsr_set (SIM_CPU *, UQI); + +/* Enum declaration for model types. */ +typedef enum model_type { + MODEL_SPARC32_DEF, MODEL_SPARC64_DEF, MODEL_MAX +} MODEL_TYPE; + +#define MAX_MODELS ((int) MODEL_MAX) + +/* Enum declaration for unit types. */ +typedef enum unit_type { + UNIT_NONE, UNIT_SPARC32_DEF_U_EXEC, UNIT_SPARC64_DEF_U_EXEC, UNIT_MAX +} UNIT_TYPE; + +#define MAX_UNITS (1) + +#endif /* SPARC_ARCH_H */ diff --git a/sim/sparc/cpu32.h b/sim/sparc/cpu32.h new file mode 100644 index 0000000..c822a3d --- /dev/null +++ b/sim/sparc/cpu32.h @@ -0,0 +1,618 @@ +/* CPU family header for sparc32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#ifndef CPU_SPARC32_H +#define CPU_SPARC32_H + +/* Maximum number of instructions that are fetched at a time. + This is for LIW type instructions sets (e.g. m32r). */ +#define MAX_LIW_INSNS 1 + +/* Maximum number of instructions that can be executed in parallel. */ +#define MAX_PARALLEL_INSNS 1 + +/* CPU state information. */ +typedef struct { + /* Hardware elements. */ + struct { + /* program counter */ + USI h_pc; +#define GET_H_PC() CPU (h_pc) +#define SET_H_PC(x) (CPU (h_pc) = (x)) + /* next pc */ + SI h_npc; +#define GET_H_NPC() CPU (h_npc) +#define SET_H_NPC(x) (CPU (h_npc) = (x)) +/* GET_H_GR macro user-written */ +/* SET_H_GR macro user-written */ + /* icc carry bit */ + BI h_icc_c; +#define GET_H_ICC_C() CPU (h_icc_c) +#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x)) + /* icc negative bit */ + BI h_icc_n; +#define GET_H_ICC_N() CPU (h_icc_n) +#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x)) + /* icc overflow bit */ + BI h_icc_v; +#define GET_H_ICC_V() CPU (h_icc_v) +#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x)) + /* icc zero bit */ + BI h_icc_z; +#define GET_H_ICC_Z() CPU (h_icc_z) +#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x)) + /* xcc carry bit */ + BI h_xcc_c; +#define GET_H_XCC_C() CPU (h_xcc_c) +#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x)) + /* xcc negative bit */ + BI h_xcc_n; +#define GET_H_XCC_N() CPU (h_xcc_n) +#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x)) + /* xcc overflow bit */ + BI h_xcc_v; +#define GET_H_XCC_V() CPU (h_xcc_v) +#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x)) + /* xcc zero bit */ + BI h_xcc_z; +#define GET_H_XCC_Z() CPU (h_xcc_z) +#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x)) +/* GET_H_Y macro user-written */ +/* SET_H_Y macro user-written */ + /* ancilliary state registers */ + SI h_asr[32]; +#define GET_H_ASR(a1) CPU (h_asr)[a1] +#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x)) + /* annul next insn? - assists execution */ + BI h_annul_p; +#define GET_H_ANNUL_P() CPU (h_annul_p) +#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x)) + /* floating point regs */ + SF h_fr[32]; +#define GET_H_FR(a1) CPU (h_fr)[a1] +#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) + /* psr register */ + USI h_psr; +/* GET_H_PSR macro user-written */ +/* SET_H_PSR macro user-written */ + /* supervisor bit */ + BI h_s; +#define GET_H_S() CPU (h_s) +#define SET_H_S(x) (CPU (h_s) = (x)) + /* previous supervisor bit */ + BI h_ps; +#define GET_H_PS() CPU (h_ps) +#define SET_H_PS(x) (CPU (h_ps) = (x)) + /* processor interrupt level */ + UQI h_pil; +#define GET_H_PIL() CPU (h_pil) +#define SET_H_PIL(x) (CPU (h_pil) = (x)) + /* enable traps bit */ + BI h_et; +#define GET_H_ET() CPU (h_et) +#define SET_H_ET(x) (CPU (h_et) = (x)) + /* tbr register */ + SI h_tbr; +/* GET_H_TBR macro user-written */ +/* SET_H_TBR macro user-written */ + /* current window pointer */ + UQI h_cwp; +/* GET_H_CWP macro user-written */ +/* SET_H_CWP macro user-written */ + /* window invalid mask */ + USI h_wim; +/* GET_H_WIM macro user-written */ +/* SET_H_WIM macro user-written */ + /* alternate global indicator */ + QI h_ag; +#define GET_H_AG() CPU (h_ag) +#define SET_H_AG(x) (CPU (h_ag) = (x)) + /* enable coprocessor bit */ + BI h_ec; +#define GET_H_EC() CPU (h_ec) +#define SET_H_EC(x) (CPU (h_ec) = (x)) + /* enable fpu bit */ + BI h_ef; +#define GET_H_EF() CPU (h_ef) +#define SET_H_EF(x) (CPU (h_ef) = (x)) + /* floating point status register */ + USI h_fsr; +#define GET_H_FSR() CPU (h_fsr) +#define SET_H_FSR(x) (CPU (h_fsr) = (x)) + } hardware; +#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +} SPARC32_CPU_DATA; + +/* Cover fns for register access. */ +USI sparc32_h_pc_get (SIM_CPU *); +void sparc32_h_pc_set (SIM_CPU *, USI); +SI sparc32_h_npc_get (SIM_CPU *); +void sparc32_h_npc_set (SIM_CPU *, SI); +SI sparc32_h_gr_get (SIM_CPU *, UINT); +void sparc32_h_gr_set (SIM_CPU *, UINT, SI); +BI sparc32_h_icc_c_get (SIM_CPU *); +void sparc32_h_icc_c_set (SIM_CPU *, BI); +BI sparc32_h_icc_n_get (SIM_CPU *); +void sparc32_h_icc_n_set (SIM_CPU *, BI); +BI sparc32_h_icc_v_get (SIM_CPU *); +void sparc32_h_icc_v_set (SIM_CPU *, BI); +BI sparc32_h_icc_z_get (SIM_CPU *); +void sparc32_h_icc_z_set (SIM_CPU *, BI); +BI sparc32_h_xcc_c_get (SIM_CPU *); +void sparc32_h_xcc_c_set (SIM_CPU *, BI); +BI sparc32_h_xcc_n_get (SIM_CPU *); +void sparc32_h_xcc_n_set (SIM_CPU *, BI); +BI sparc32_h_xcc_v_get (SIM_CPU *); +void sparc32_h_xcc_v_set (SIM_CPU *, BI); +BI sparc32_h_xcc_z_get (SIM_CPU *); +void sparc32_h_xcc_z_set (SIM_CPU *, BI); +SI sparc32_h_y_get (SIM_CPU *); +void sparc32_h_y_set (SIM_CPU *, SI); +SI sparc32_h_asr_get (SIM_CPU *, UINT); +void sparc32_h_asr_set (SIM_CPU *, UINT, SI); +BI sparc32_h_annul_p_get (SIM_CPU *); +void sparc32_h_annul_p_set (SIM_CPU *, BI); +SF sparc32_h_fr_get (SIM_CPU *, UINT); +void sparc32_h_fr_set (SIM_CPU *, UINT, SF); +USI sparc32_h_psr_get (SIM_CPU *); +void sparc32_h_psr_set (SIM_CPU *, USI); +BI sparc32_h_s_get (SIM_CPU *); +void sparc32_h_s_set (SIM_CPU *, BI); +BI sparc32_h_ps_get (SIM_CPU *); +void sparc32_h_ps_set (SIM_CPU *, BI); +UQI sparc32_h_pil_get (SIM_CPU *); +void sparc32_h_pil_set (SIM_CPU *, UQI); +BI sparc32_h_et_get (SIM_CPU *); +void sparc32_h_et_set (SIM_CPU *, BI); +SI sparc32_h_tbr_get (SIM_CPU *); +void sparc32_h_tbr_set (SIM_CPU *, SI); +UQI sparc32_h_cwp_get (SIM_CPU *); +void sparc32_h_cwp_set (SIM_CPU *, UQI); +USI sparc32_h_wim_get (SIM_CPU *); +void sparc32_h_wim_set (SIM_CPU *, USI); +QI sparc32_h_ag_get (SIM_CPU *); +void sparc32_h_ag_set (SIM_CPU *, QI); +BI sparc32_h_ec_get (SIM_CPU *); +void sparc32_h_ec_set (SIM_CPU *, BI); +BI sparc32_h_ef_get (SIM_CPU *); +void sparc32_h_ef_set (SIM_CPU *, BI); +USI sparc32_h_fsr_get (SIM_CPU *); +void sparc32_h_fsr_set (SIM_CPU *, USI); + +/* These must be hand-written. */ +extern CPUREG_FETCH_FN sparc32_fetch_register; +extern CPUREG_STORE_FN sparc32_store_register; + +typedef struct { + int empty; +} MODEL_SPARC32_DEF_DATA; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* cpu specific data follows */ + CGEN_INSN_INT insn; + int written; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + /* Instruction fields. */ \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_RD_ASR_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_RD_ASR_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_WR_ASR_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_WR_ASR_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_WR_ASR_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_WR_ASR_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_RD_PSR_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_RD_PSR_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_WR_PSR_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_WR_PSR_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_WR_PSR_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_WR_PSR_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDSTUB_REG_REG_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDSTUB_REG_REG_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDSTUB_REG_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDSTUB_REG_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + UINT f_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDD_REG_REG_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_REG_REG_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDD_REG_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_REG_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + UINT f_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + UINT f_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_SETHI_VARS \ + /* Instruction fields. */ \ + INT f_hi22; \ + UINT f_op2; \ + UINT f_rd; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_SETHI_CODE \ + length = 4; \ + f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_UNIMP_VARS \ + /* Instruction fields. */ \ + INT f_imm22; \ + UINT f_op2; \ + UINT f_rd_res; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_UNIMP_CODE \ + length = 4; \ + f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_CALL_VARS \ + /* Instruction fields. */ \ + SI f_disp30; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_CALL_CODE \ + length = 4; \ + f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_BA_VARS \ + /* Instruction fields. */ \ + SI f_disp22; \ + UINT f_op2; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_BA_CODE \ + length = 4; \ + f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \ + f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_TA_VARS \ + /* Instruction fields. */ \ + UINT f_rs2; \ + INT f_res_asi; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_TA_CODE \ + length = 4; \ + f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ + f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +#define EXTRACT_IFMT_TA_IMM_VARS \ + /* Instruction fields. */ \ + INT f_simm13; \ + UINT f_i; \ + UINT f_rs1; \ + UINT f_op3; \ + UINT f_fmt2_cond; \ + UINT f_a; \ + UINT f_op; \ + unsigned int length; +#define EXTRACT_IFMT_TA_IMM_CODE \ + length = 4; \ + f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ + f_i = EXTRACT_UINT (insn, 32, 13, 1); \ + f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ + f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ + f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ + f_a = EXTRACT_UINT (insn, 32, 29, 1); \ + f_op = EXTRACT_UINT (insn, 32, 31, 2); \ + +/* Collection of various things for the trace handler to use. */ + +typedef struct trace_record { + IADDR pc; + /* FIXME:wip */ +} TRACE_RECORD; + +#endif /* CPU_SPARC32_H */ diff --git a/sim/sparc/decode32.c b/sim/sparc/decode32.c new file mode 100644 index 0000000..9d85b99 --- /dev/null +++ b/sim/sparc/decode32.c @@ -0,0 +1,1278 @@ +/* Simulator instruction decoder for sparc32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc32 +#define WANT_CPU_SPARC32 + +#include "sim-main.h" +#include "sim-assert.h" + +/* FIXME: Need to review choices for the following. */ + +#if WITH_SEM_SWITCH_FULL +#define FULL(fn) +#else +#define FULL(fn) CONCAT3 (sparc32,_sem_,fn) , +#endif + +#if WITH_FAST +#if WITH_SEM_SWITCH_FAST +#define FAST(fn) +#else +#define FAST(fn) CONCAT3 (sparc32,_semf_,fn) , /* f for fast */ +#endif +#else +#define FAST(fn) +#endif + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC sparc32_insn_data[SPARC32_INSN_MAX]; + +/* The INSN_ prefix is not here and is instead part of the `insn' argument + to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ +#define IDX(insn) CONCAT2 (SPARC32_,insn) +#define TYPE(insn) CONCAT2 (SPARC_,insn) + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem sparc32_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, + { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, + { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, + { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, + { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, + { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, + { TYPE (INSN_RD_ASR), IDX (INSN_RD_ASR), FULL (rd_asr) FAST (rd_asr) }, + { TYPE (INSN_WR_ASR), IDX (INSN_WR_ASR), FULL (wr_asr) FAST (wr_asr) }, + { TYPE (INSN_WR_ASR_IMM), IDX (INSN_WR_ASR_IMM), FULL (wr_asr_imm) FAST (wr_asr_imm) }, + { TYPE (INSN_RD_PSR), IDX (INSN_RD_PSR), FULL (rd_psr) FAST (rd_psr) }, + { TYPE (INSN_WR_PSR), IDX (INSN_WR_PSR), FULL (wr_psr) FAST (wr_psr) }, + { TYPE (INSN_WR_PSR_IMM), IDX (INSN_WR_PSR_IMM), FULL (wr_psr_imm) FAST (wr_psr_imm) }, + { TYPE (INSN_RD_WIM), IDX (INSN_RD_WIM), FULL (rd_wim) FAST (rd_wim) }, + { TYPE (INSN_WR_WIM), IDX (INSN_WR_WIM), FULL (wr_wim) FAST (wr_wim) }, + { TYPE (INSN_WR_WIM_IMM), IDX (INSN_WR_WIM_IMM), FULL (wr_wim_imm) FAST (wr_wim_imm) }, + { TYPE (INSN_RD_TBR), IDX (INSN_RD_TBR), FULL (rd_tbr) FAST (rd_tbr) }, + { TYPE (INSN_WR_TBR), IDX (INSN_WR_TBR), FULL (wr_tbr) FAST (wr_tbr) }, + { TYPE (INSN_WR_TBR_IMM), IDX (INSN_WR_TBR_IMM), FULL (wr_tbr_imm) FAST (wr_tbr_imm) }, + { TYPE (INSN_LDSTUB_REG_REG), IDX (INSN_LDSTUB_REG_REG), FULL (ldstub_reg_reg) FAST (ldstub_reg_reg) }, + { TYPE (INSN_LDSTUB_REG_IMM), IDX (INSN_LDSTUB_REG_IMM), FULL (ldstub_reg_imm) FAST (ldstub_reg_imm) }, + { TYPE (INSN_LDSTUB_REG_REG_ASI), IDX (INSN_LDSTUB_REG_REG_ASI), FULL (ldstub_reg_reg_asi) FAST (ldstub_reg_reg_asi) }, + { TYPE (INSN_SWAP_REG_REG), IDX (INSN_SWAP_REG_REG), FULL (swap_reg_reg) FAST (swap_reg_reg) }, + { TYPE (INSN_SWAP_REG_IMM), IDX (INSN_SWAP_REG_IMM), FULL (swap_reg_imm) FAST (swap_reg_imm) }, + { TYPE (INSN_SWAP_REG_REG_ASI), IDX (INSN_SWAP_REG_REG_ASI), FULL (swap_reg_reg_asi) FAST (swap_reg_reg_asi) }, + { TYPE (INSN_LDSB_REG_REG), IDX (INSN_LDSB_REG_REG), FULL (ldsb_reg_reg) FAST (ldsb_reg_reg) }, + { TYPE (INSN_LDSB_REG_IMM), IDX (INSN_LDSB_REG_IMM), FULL (ldsb_reg_imm) FAST (ldsb_reg_imm) }, + { TYPE (INSN_LDSB_REG_REG_ASI), IDX (INSN_LDSB_REG_REG_ASI), FULL (ldsb_reg_reg_asi) FAST (ldsb_reg_reg_asi) }, + { TYPE (INSN_LDUB_REG_REG), IDX (INSN_LDUB_REG_REG), FULL (ldub_reg_reg) FAST (ldub_reg_reg) }, + { TYPE (INSN_LDUB_REG_IMM), IDX (INSN_LDUB_REG_IMM), FULL (ldub_reg_imm) FAST (ldub_reg_imm) }, + { TYPE (INSN_LDUB_REG_REG_ASI), IDX (INSN_LDUB_REG_REG_ASI), FULL (ldub_reg_reg_asi) FAST (ldub_reg_reg_asi) }, + { TYPE (INSN_LDSH_REG_REG), IDX (INSN_LDSH_REG_REG), FULL (ldsh_reg_reg) FAST (ldsh_reg_reg) }, + { TYPE (INSN_LDSH_REG_IMM), IDX (INSN_LDSH_REG_IMM), FULL (ldsh_reg_imm) FAST (ldsh_reg_imm) }, + { TYPE (INSN_LDSH_REG_REG_ASI), IDX (INSN_LDSH_REG_REG_ASI), FULL (ldsh_reg_reg_asi) FAST (ldsh_reg_reg_asi) }, + { TYPE (INSN_LDUH_REG_REG), IDX (INSN_LDUH_REG_REG), FULL (lduh_reg_reg) FAST (lduh_reg_reg) }, + { TYPE (INSN_LDUH_REG_IMM), IDX (INSN_LDUH_REG_IMM), FULL (lduh_reg_imm) FAST (lduh_reg_imm) }, + { TYPE (INSN_LDUH_REG_REG_ASI), IDX (INSN_LDUH_REG_REG_ASI), FULL (lduh_reg_reg_asi) FAST (lduh_reg_reg_asi) }, + { TYPE (INSN_LDSW_REG_REG), IDX (INSN_LDSW_REG_REG), FULL (ldsw_reg_reg) FAST (ldsw_reg_reg) }, + { TYPE (INSN_LDSW_REG_IMM), IDX (INSN_LDSW_REG_IMM), FULL (ldsw_reg_imm) FAST (ldsw_reg_imm) }, + { TYPE (INSN_LDSW_REG_REG_ASI), IDX (INSN_LDSW_REG_REG_ASI), FULL (ldsw_reg_reg_asi) FAST (ldsw_reg_reg_asi) }, + { TYPE (INSN_LDUW_REG_REG), IDX (INSN_LDUW_REG_REG), FULL (lduw_reg_reg) FAST (lduw_reg_reg) }, + { TYPE (INSN_LDUW_REG_IMM), IDX (INSN_LDUW_REG_IMM), FULL (lduw_reg_imm) FAST (lduw_reg_imm) }, + { TYPE (INSN_LDUW_REG_REG_ASI), IDX (INSN_LDUW_REG_REG_ASI), FULL (lduw_reg_reg_asi) FAST (lduw_reg_reg_asi) }, + { TYPE (INSN_LDD_REG_REG), IDX (INSN_LDD_REG_REG), FULL (ldd_reg_reg) FAST (ldd_reg_reg) }, + { TYPE (INSN_LDD_REG_IMM), IDX (INSN_LDD_REG_IMM), FULL (ldd_reg_imm) FAST (ldd_reg_imm) }, + { TYPE (INSN_LDD_REG_REG_ASI), IDX (INSN_LDD_REG_REG_ASI), FULL (ldd_reg_reg_asi) FAST (ldd_reg_reg_asi) }, + { TYPE (INSN_STB_REG_REG), IDX (INSN_STB_REG_REG), FULL (stb_reg_reg) FAST (stb_reg_reg) }, + { TYPE (INSN_STB_REG_IMM), IDX (INSN_STB_REG_IMM), FULL (stb_reg_imm) FAST (stb_reg_imm) }, + { TYPE (INSN_STB_REG_REG_ASI), IDX (INSN_STB_REG_REG_ASI), FULL (stb_reg_reg_asi) FAST (stb_reg_reg_asi) }, + { TYPE (INSN_STH_REG_REG), IDX (INSN_STH_REG_REG), FULL (sth_reg_reg) FAST (sth_reg_reg) }, + { TYPE (INSN_STH_REG_IMM), IDX (INSN_STH_REG_IMM), FULL (sth_reg_imm) FAST (sth_reg_imm) }, + { TYPE (INSN_STH_REG_REG_ASI), IDX (INSN_STH_REG_REG_ASI), FULL (sth_reg_reg_asi) FAST (sth_reg_reg_asi) }, + { TYPE (INSN_ST_REG_REG), IDX (INSN_ST_REG_REG), FULL (st_reg_reg) FAST (st_reg_reg) }, + { TYPE (INSN_ST_REG_IMM), IDX (INSN_ST_REG_IMM), FULL (st_reg_imm) FAST (st_reg_imm) }, + { TYPE (INSN_ST_REG_REG_ASI), IDX (INSN_ST_REG_REG_ASI), FULL (st_reg_reg_asi) FAST (st_reg_reg_asi) }, + { TYPE (INSN_STD_REG_REG), IDX (INSN_STD_REG_REG), FULL (std_reg_reg) FAST (std_reg_reg) }, + { TYPE (INSN_STD_REG_IMM), IDX (INSN_STD_REG_IMM), FULL (std_reg_imm) FAST (std_reg_imm) }, + { TYPE (INSN_STD_REG_REG_ASI), IDX (INSN_STD_REG_REG_ASI), FULL (std_reg_reg_asi) FAST (std_reg_reg_asi) }, + { TYPE (INSN_FP_LD_REG_REG), IDX (INSN_FP_LD_REG_REG), FULL (fp_ld_reg_reg) FAST (fp_ld_reg_reg) }, + { TYPE (INSN_FP_LD_REG_IMM), IDX (INSN_FP_LD_REG_IMM), FULL (fp_ld_reg_imm) FAST (fp_ld_reg_imm) }, + { TYPE (INSN_FP_LD_REG_REG_ASI), IDX (INSN_FP_LD_REG_REG_ASI), FULL (fp_ld_reg_reg_asi) FAST (fp_ld_reg_reg_asi) }, + { TYPE (INSN_SETHI), IDX (INSN_SETHI), FULL (sethi) FAST (sethi) }, + { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) }, + { TYPE (INSN_ADD_IMM), IDX (INSN_ADD_IMM), FULL (add_imm) FAST (add_imm) }, + { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) }, + { TYPE (INSN_SUB_IMM), IDX (INSN_SUB_IMM), FULL (sub_imm) FAST (sub_imm) }, + { TYPE (INSN_ADDCC), IDX (INSN_ADDCC), FULL (addcc) FAST (addcc) }, + { TYPE (INSN_ADDCC_IMM), IDX (INSN_ADDCC_IMM), FULL (addcc_imm) FAST (addcc_imm) }, + { TYPE (INSN_SUBCC), IDX (INSN_SUBCC), FULL (subcc) FAST (subcc) }, + { TYPE (INSN_SUBCC_IMM), IDX (INSN_SUBCC_IMM), FULL (subcc_imm) FAST (subcc_imm) }, + { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) }, + { TYPE (INSN_ADDX_IMM), IDX (INSN_ADDX_IMM), FULL (addx_imm) FAST (addx_imm) }, + { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) }, + { TYPE (INSN_SUBX_IMM), IDX (INSN_SUBX_IMM), FULL (subx_imm) FAST (subx_imm) }, + { TYPE (INSN_ADDXCC), IDX (INSN_ADDXCC), FULL (addxcc) FAST (addxcc) }, + { TYPE (INSN_ADDXCC_IMM), IDX (INSN_ADDXCC_IMM), FULL (addxcc_imm) FAST (addxcc_imm) }, + { TYPE (INSN_SUBXCC), IDX (INSN_SUBXCC), FULL (subxcc) FAST (subxcc) }, + { TYPE (INSN_SUBXCC_IMM), IDX (INSN_SUBXCC_IMM), FULL (subxcc_imm) FAST (subxcc_imm) }, + { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, + { TYPE (INSN_AND_IMM), IDX (INSN_AND_IMM), FULL (and_imm) FAST (and_imm) }, + { TYPE (INSN_ANDCC), IDX (INSN_ANDCC), FULL (andcc) FAST (andcc) }, + { TYPE (INSN_ANDCC_IMM), IDX (INSN_ANDCC_IMM), FULL (andcc_imm) FAST (andcc_imm) }, + { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, + { TYPE (INSN_OR_IMM), IDX (INSN_OR_IMM), FULL (or_imm) FAST (or_imm) }, + { TYPE (INSN_ORCC), IDX (INSN_ORCC), FULL (orcc) FAST (orcc) }, + { TYPE (INSN_ORCC_IMM), IDX (INSN_ORCC_IMM), FULL (orcc_imm) FAST (orcc_imm) }, + { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, + { TYPE (INSN_XOR_IMM), IDX (INSN_XOR_IMM), FULL (xor_imm) FAST (xor_imm) }, + { TYPE (INSN_XORCC), IDX (INSN_XORCC), FULL (xorcc) FAST (xorcc) }, + { TYPE (INSN_XORCC_IMM), IDX (INSN_XORCC_IMM), FULL (xorcc_imm) FAST (xorcc_imm) }, + { TYPE (INSN_ANDN), IDX (INSN_ANDN), FULL (andn) FAST (andn) }, + { TYPE (INSN_ANDN_IMM), IDX (INSN_ANDN_IMM), FULL (andn_imm) FAST (andn_imm) }, + { TYPE (INSN_ANDNCC), IDX (INSN_ANDNCC), FULL (andncc) FAST (andncc) }, + { TYPE (INSN_ANDNCC_IMM), IDX (INSN_ANDNCC_IMM), FULL (andncc_imm) FAST (andncc_imm) }, + { TYPE (INSN_ORN), IDX (INSN_ORN), FULL (orn) FAST (orn) }, + { TYPE (INSN_ORN_IMM), IDX (INSN_ORN_IMM), FULL (orn_imm) FAST (orn_imm) }, + { TYPE (INSN_ORNCC), IDX (INSN_ORNCC), FULL (orncc) FAST (orncc) }, + { TYPE (INSN_ORNCC_IMM), IDX (INSN_ORNCC_IMM), FULL (orncc_imm) FAST (orncc_imm) }, + { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) }, + { TYPE (INSN_XNOR_IMM), IDX (INSN_XNOR_IMM), FULL (xnor_imm) FAST (xnor_imm) }, + { TYPE (INSN_XNORCC), IDX (INSN_XNORCC), FULL (xnorcc) FAST (xnorcc) }, + { TYPE (INSN_XNORCC_IMM), IDX (INSN_XNORCC_IMM), FULL (xnorcc_imm) FAST (xnorcc_imm) }, + { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) }, + { TYPE (INSN_SLL_IMM), IDX (INSN_SLL_IMM), FULL (sll_imm) FAST (sll_imm) }, + { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) }, + { TYPE (INSN_SRL_IMM), IDX (INSN_SRL_IMM), FULL (srl_imm) FAST (srl_imm) }, + { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) }, + { TYPE (INSN_SRA_IMM), IDX (INSN_SRA_IMM), FULL (sra_imm) FAST (sra_imm) }, + { TYPE (INSN_SMUL), IDX (INSN_SMUL), FULL (smul) FAST (smul) }, + { TYPE (INSN_SMUL_IMM), IDX (INSN_SMUL_IMM), FULL (smul_imm) FAST (smul_imm) }, + { TYPE (INSN_SMUL_CC), IDX (INSN_SMUL_CC), FULL (smul_cc) FAST (smul_cc) }, + { TYPE (INSN_SMUL_CC_IMM), IDX (INSN_SMUL_CC_IMM), FULL (smul_cc_imm) FAST (smul_cc_imm) }, + { TYPE (INSN_UMUL), IDX (INSN_UMUL), FULL (umul) FAST (umul) }, + { TYPE (INSN_UMUL_IMM), IDX (INSN_UMUL_IMM), FULL (umul_imm) FAST (umul_imm) }, + { TYPE (INSN_UMUL_CC), IDX (INSN_UMUL_CC), FULL (umul_cc) FAST (umul_cc) }, + { TYPE (INSN_UMUL_CC_IMM), IDX (INSN_UMUL_CC_IMM), FULL (umul_cc_imm) FAST (umul_cc_imm) }, + { TYPE (INSN_SDIV), IDX (INSN_SDIV), FULL (sdiv) FAST (sdiv) }, + { TYPE (INSN_SDIV_IMM), IDX (INSN_SDIV_IMM), FULL (sdiv_imm) FAST (sdiv_imm) }, + { TYPE (INSN_SDIV_CC), IDX (INSN_SDIV_CC), FULL (sdiv_cc) FAST (sdiv_cc) }, + { TYPE (INSN_SDIV_CC_IMM), IDX (INSN_SDIV_CC_IMM), FULL (sdiv_cc_imm) FAST (sdiv_cc_imm) }, + { TYPE (INSN_UDIV), IDX (INSN_UDIV), FULL (udiv) FAST (udiv) }, + { TYPE (INSN_UDIV_IMM), IDX (INSN_UDIV_IMM), FULL (udiv_imm) FAST (udiv_imm) }, + { TYPE (INSN_UDIV_CC), IDX (INSN_UDIV_CC), FULL (udiv_cc) FAST (udiv_cc) }, + { TYPE (INSN_UDIV_CC_IMM), IDX (INSN_UDIV_CC_IMM), FULL (udiv_cc_imm) FAST (udiv_cc_imm) }, + { TYPE (INSN_MULSCC), IDX (INSN_MULSCC), FULL (mulscc) FAST (mulscc) }, + { TYPE (INSN_SAVE), IDX (INSN_SAVE), FULL (save) FAST (save) }, + { TYPE (INSN_SAVE_IMM), IDX (INSN_SAVE_IMM), FULL (save_imm) FAST (save_imm) }, + { TYPE (INSN_RESTORE), IDX (INSN_RESTORE), FULL (restore) FAST (restore) }, + { TYPE (INSN_RESTORE_IMM), IDX (INSN_RESTORE_IMM), FULL (restore_imm) FAST (restore_imm) }, + { TYPE (INSN_RETT), IDX (INSN_RETT), FULL (rett) FAST (rett) }, + { TYPE (INSN_RETT_IMM), IDX (INSN_RETT_IMM), FULL (rett_imm) FAST (rett_imm) }, + { TYPE (INSN_UNIMP), IDX (INSN_UNIMP), FULL (unimp) FAST (unimp) }, + { TYPE (INSN_CALL), IDX (INSN_CALL), FULL (call) FAST (call) }, + { TYPE (INSN_JMPL), IDX (INSN_JMPL), FULL (jmpl) FAST (jmpl) }, + { TYPE (INSN_JMPL_IMM), IDX (INSN_JMPL_IMM), FULL (jmpl_imm) FAST (jmpl_imm) }, + { TYPE (INSN_BA), IDX (INSN_BA), FULL (ba) FAST (ba) }, + { TYPE (INSN_TA), IDX (INSN_TA), FULL (ta) FAST (ta) }, + { TYPE (INSN_TA_IMM), IDX (INSN_TA_IMM), FULL (ta_imm) FAST (ta_imm) }, + { TYPE (INSN_BN), IDX (INSN_BN), FULL (bn) FAST (bn) }, + { TYPE (INSN_TN), IDX (INSN_TN), FULL (tn) FAST (tn) }, + { TYPE (INSN_TN_IMM), IDX (INSN_TN_IMM), FULL (tn_imm) FAST (tn_imm) }, + { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, + { TYPE (INSN_TNE), IDX (INSN_TNE), FULL (tne) FAST (tne) }, + { TYPE (INSN_TNE_IMM), IDX (INSN_TNE_IMM), FULL (tne_imm) FAST (tne_imm) }, + { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) }, + { TYPE (INSN_TE), IDX (INSN_TE), FULL (te) FAST (te) }, + { TYPE (INSN_TE_IMM), IDX (INSN_TE_IMM), FULL (te_imm) FAST (te_imm) }, + { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) }, + { TYPE (INSN_TG), IDX (INSN_TG), FULL (tg) FAST (tg) }, + { TYPE (INSN_TG_IMM), IDX (INSN_TG_IMM), FULL (tg_imm) FAST (tg_imm) }, + { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, + { TYPE (INSN_TLE), IDX (INSN_TLE), FULL (tle) FAST (tle) }, + { TYPE (INSN_TLE_IMM), IDX (INSN_TLE_IMM), FULL (tle_imm) FAST (tle_imm) }, + { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, + { TYPE (INSN_TGE), IDX (INSN_TGE), FULL (tge) FAST (tge) }, + { TYPE (INSN_TGE_IMM), IDX (INSN_TGE_IMM), FULL (tge_imm) FAST (tge_imm) }, + { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) }, + { TYPE (INSN_TL), IDX (INSN_TL), FULL (tl) FAST (tl) }, + { TYPE (INSN_TL_IMM), IDX (INSN_TL_IMM), FULL (tl_imm) FAST (tl_imm) }, + { TYPE (INSN_BGU), IDX (INSN_BGU), FULL (bgu) FAST (bgu) }, + { TYPE (INSN_TGU), IDX (INSN_TGU), FULL (tgu) FAST (tgu) }, + { TYPE (INSN_TGU_IMM), IDX (INSN_TGU_IMM), FULL (tgu_imm) FAST (tgu_imm) }, + { TYPE (INSN_BLEU), IDX (INSN_BLEU), FULL (bleu) FAST (bleu) }, + { TYPE (INSN_TLEU), IDX (INSN_TLEU), FULL (tleu) FAST (tleu) }, + { TYPE (INSN_TLEU_IMM), IDX (INSN_TLEU_IMM), FULL (tleu_imm) FAST (tleu_imm) }, + { TYPE (INSN_BCC), IDX (INSN_BCC), FULL (bcc) FAST (bcc) }, + { TYPE (INSN_TCC), IDX (INSN_TCC), FULL (tcc) FAST (tcc) }, + { TYPE (INSN_TCC_IMM), IDX (INSN_TCC_IMM), FULL (tcc_imm) FAST (tcc_imm) }, + { TYPE (INSN_BCS), IDX (INSN_BCS), FULL (bcs) FAST (bcs) }, + { TYPE (INSN_TCS), IDX (INSN_TCS), FULL (tcs) FAST (tcs) }, + { TYPE (INSN_TCS_IMM), IDX (INSN_TCS_IMM), FULL (tcs_imm) FAST (tcs_imm) }, + { TYPE (INSN_BPOS), IDX (INSN_BPOS), FULL (bpos) FAST (bpos) }, + { TYPE (INSN_TPOS), IDX (INSN_TPOS), FULL (tpos) FAST (tpos) }, + { TYPE (INSN_TPOS_IMM), IDX (INSN_TPOS_IMM), FULL (tpos_imm) FAST (tpos_imm) }, + { TYPE (INSN_BNEG), IDX (INSN_BNEG), FULL (bneg) FAST (bneg) }, + { TYPE (INSN_TNEG), IDX (INSN_TNEG), FULL (tneg) FAST (tneg) }, + { TYPE (INSN_TNEG_IMM), IDX (INSN_TNEG_IMM), FULL (tneg_imm) FAST (tneg_imm) }, + { TYPE (INSN_BVC), IDX (INSN_BVC), FULL (bvc) FAST (bvc) }, + { TYPE (INSN_TVC), IDX (INSN_TVC), FULL (tvc) FAST (tvc) }, + { TYPE (INSN_TVC_IMM), IDX (INSN_TVC_IMM), FULL (tvc_imm) FAST (tvc_imm) }, + { TYPE (INSN_BVS), IDX (INSN_BVS), FULL (bvs) FAST (bvs) }, + { TYPE (INSN_TVS), IDX (INSN_TVS), FULL (tvs) FAST (tvs) }, + { TYPE (INSN_TVS_IMM), IDX (INSN_TVS_IMM), FULL (tvs_imm) FAST (tvs_imm) }, +}; + +static const struct insn_sem sparc32_insn_sem_invalid = +{ + VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) +}; + +#undef IDX +#undef TYPE + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; +#if ! WITH_SEM_SWITCH_FULL + id->sem_full = t->sem_full; +#endif +#if WITH_FAST && ! WITH_SEM_SWITCH_FAST + id->sem_fast = t->sem_fast; +#endif +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif +} + +/* Initialize the instruction descriptor table. */ + +void +sparc32_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = SPARC32_INSN_MAX; + IDESC *table = sparc32_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & sparc32_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = sparc32_insn_sem, tend = t + sizeof (sparc32_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +#define GOTO_EXTRACT(id) goto extract + +/* The decoder needs a slightly different computed goto switch control. */ +#ifdef __GNUC__ +#define DECODE_SWITCH(N, X) goto *labels_##N[X]; +#else +#define DECODE_SWITCH(N, X) switch (X) +#endif + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +sparc32_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + ARGBUF *abuf) +{ + /* Result. */ + const IDESC *idecode; + + { +#define I(insn) & sparc32_insn_data[CONCAT2 (SPARC32_,insn)] + CGEN_INSN_INT insn = base_insn; + static const IDESC *idecode_invalid = I (INSN_X_INVALID); + + { +#ifdef __GNUC__ + static const void *labels_0[256] = { + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_16, && case_0_17, && case_0_18, && case_0_19, + && case_0_20, && case_0_21, && case_0_22, && case_0_23, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_128, && case_0_129, && case_0_130, && case_0_131, + && case_0_132, && case_0_133, && case_0_134, && case_0_135, + && case_0_136, && default_0, && case_0_138, && case_0_139, + && case_0_140, && default_0, && case_0_142, && case_0_143, + && case_0_144, && case_0_145, && case_0_146, && case_0_147, + && case_0_148, && case_0_149, && case_0_150, && case_0_151, + && case_0_152, && default_0, && case_0_154, && case_0_155, + && case_0_156, && default_0, && case_0_158, && case_0_159, + && default_0, && default_0, && default_0, && default_0, + && default_0, && case_0_165, && case_0_166, && case_0_167, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_176, && case_0_177, && case_0_178, && case_0_179, + && default_0, && default_0, && default_0, && default_0, + && case_0_184, && case_0_185, && case_0_186, && default_0, + && case_0_188, && case_0_189, && default_0, && default_0, + && case_0_192, && case_0_193, && case_0_194, && case_0_195, + && case_0_196, && case_0_197, && case_0_198, && case_0_199, + && case_0_200, && case_0_201, && case_0_202, && default_0, + && default_0, && case_0_205, && default_0, && case_0_207, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && case_0_224, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + && default_0, && default_0, && default_0, && default_0, + }; +#endif + static const IDESC * insns[256] = { + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_UNIMP), I (INSN_UNIMP), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_SETHI), I (INSN_SETHI), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + I (INSN_CALL), I (INSN_CALL), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_MULSCC), 0, + 0, 0, + I (INSN_RD_ASR), I (INSN_RD_PSR), + I (INSN_RD_WIM), I (INSN_RD_TBR), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + 0, I (INSN_X_INVALID), + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), 0, + I (INSN_X_INVALID), 0, + I (INSN_LDUW_REG_REG_ASI), I (INSN_LDUB_REG_REG_ASI), + I (INSN_LDUH_REG_REG_ASI), I (INSN_LDD_REG_REG_ASI), + I (INSN_ST_REG_REG_ASI), I (INSN_STB_REG_REG_ASI), + I (INSN_STH_REG_REG_ASI), I (INSN_STD_REG_REG_ASI), + I (INSN_LDSW_REG_REG_ASI), I (INSN_LDSB_REG_REG_ASI), + I (INSN_LDSH_REG_REG_ASI), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_LDSTUB_REG_REG_ASI), + I (INSN_X_INVALID), I (INSN_SWAP_REG_REG_ASI), + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_FP_LD_REG_REG_ASI), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 24) & (3 << 6)) | ((insn >> 19) & (63 << 0))); + DECODE_SWITCH (0, val) + { + CASE (0, 16) : /* fall through */ + CASE (0, 17) : /* fall through */ + CASE (0, 18) : /* fall through */ + CASE (0, 19) : /* fall through */ + CASE (0, 20) : /* fall through */ + CASE (0, 21) : /* fall through */ + CASE (0, 22) : /* fall through */ + CASE (0, 23) : + { + static const IDESC * insns[16] = { + I (INSN_BN), I (INSN_BE), + I (INSN_BLE), I (INSN_BL), + I (INSN_BLEU), I (INSN_BCS), + I (INSN_BNEG), I (INSN_BVS), + I (INSN_BA), I (INSN_BNE), + I (INSN_BG), I (INSN_BGE), + I (INSN_BGU), I (INSN_BCC), + I (INSN_BPOS), I (INSN_BVC), + }; + unsigned int val = (((insn >> 25) & (15 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 128) : + { + static const IDESC * insns[2] = { + I (INSN_ADD), I (INSN_ADD_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 129) : + { + static const IDESC * insns[2] = { + I (INSN_AND), I (INSN_AND_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 130) : + { + static const IDESC * insns[2] = { + I (INSN_OR), I (INSN_OR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 131) : + { + static const IDESC * insns[2] = { + I (INSN_XOR), I (INSN_XOR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 132) : + { + static const IDESC * insns[2] = { + I (INSN_SUB), I (INSN_SUB_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 133) : + { + static const IDESC * insns[2] = { + I (INSN_ANDN), I (INSN_ANDN_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 134) : + { + static const IDESC * insns[2] = { + I (INSN_ORN), I (INSN_ORN_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 135) : + { + static const IDESC * insns[2] = { + I (INSN_XNOR), I (INSN_XNOR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 136) : + { + static const IDESC * insns[2] = { + I (INSN_ADDX), I (INSN_ADDX_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 138) : + { + static const IDESC * insns[2] = { + I (INSN_UMUL), I (INSN_UMUL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 139) : + { + static const IDESC * insns[2] = { + I (INSN_SMUL), I (INSN_SMUL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 140) : + { + static const IDESC * insns[2] = { + I (INSN_SUBX), I (INSN_SUBX_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 142) : + { + static const IDESC * insns[2] = { + I (INSN_UDIV), I (INSN_UDIV_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 143) : + { + static const IDESC * insns[2] = { + I (INSN_SDIV), I (INSN_SDIV_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 144) : + { + static const IDESC * insns[2] = { + I (INSN_ADDCC), I (INSN_ADDCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 145) : + { + static const IDESC * insns[2] = { + I (INSN_ANDCC), I (INSN_ANDCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 146) : + { + static const IDESC * insns[2] = { + I (INSN_ORCC), I (INSN_ORCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 147) : + { + static const IDESC * insns[2] = { + I (INSN_XORCC), I (INSN_XORCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 148) : + { + static const IDESC * insns[2] = { + I (INSN_SUBCC), I (INSN_SUBCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 149) : + { + static const IDESC * insns[2] = { + I (INSN_ANDNCC), I (INSN_ANDNCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 150) : + { + static const IDESC * insns[2] = { + I (INSN_ORNCC), I (INSN_ORNCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 151) : + { + static const IDESC * insns[2] = { + I (INSN_XNORCC), I (INSN_XNORCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 152) : + { + static const IDESC * insns[2] = { + I (INSN_ADDXCC), I (INSN_ADDXCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 154) : + { + static const IDESC * insns[2] = { + I (INSN_UMUL_CC), I (INSN_UMUL_CC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 155) : + { + static const IDESC * insns[2] = { + I (INSN_SMUL_CC), I (INSN_SMUL_CC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 156) : + { + static const IDESC * insns[2] = { + I (INSN_SUBXCC), I (INSN_SUBXCC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 158) : + { + static const IDESC * insns[2] = { + I (INSN_UDIV_CC), I (INSN_UDIV_CC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 159) : + { + static const IDESC * insns[2] = { + I (INSN_SDIV_CC), I (INSN_SDIV_CC_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 165) : + { + static const IDESC * insns[2] = { + I (INSN_SLL), I (INSN_SLL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 166) : + { + static const IDESC * insns[2] = { + I (INSN_SRL), I (INSN_SRL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 167) : + { + static const IDESC * insns[2] = { + I (INSN_SRA), I (INSN_SRA_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 176) : + { + static const IDESC * insns[2] = { + I (INSN_WR_ASR), I (INSN_WR_ASR_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 177) : + { +#ifdef __GNUC__ + static const void *labels_0_177[16] = { + && case_0_177_0, && default_0_177, && default_0_177, && default_0_177, + && default_0_177, && default_0_177, && default_0_177, && default_0_177, + && default_0_177, && default_0_177, && default_0_177, && default_0_177, + && default_0_177, && default_0_177, && default_0_177, && default_0_177, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_177, val) + { + CASE (0_177, 0) : + { + static const IDESC * insns[4] = { + I (INSN_WR_PSR), I (INSN_WR_PSR_IMM), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_177) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_177) + } + CASE (0, 178) : + { +#ifdef __GNUC__ + static const void *labels_0_178[16] = { + && case_0_178_0, && default_0_178, && default_0_178, && default_0_178, + && default_0_178, && default_0_178, && default_0_178, && default_0_178, + && default_0_178, && default_0_178, && default_0_178, && default_0_178, + && default_0_178, && default_0_178, && default_0_178, && default_0_178, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_178, val) + { + CASE (0_178, 0) : + { + static const IDESC * insns[4] = { + I (INSN_WR_WIM), I (INSN_WR_WIM_IMM), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_178) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_178) + } + CASE (0, 179) : + { +#ifdef __GNUC__ + static const void *labels_0_179[16] = { + && case_0_179_0, && default_0_179, && default_0_179, && default_0_179, + && default_0_179, && default_0_179, && default_0_179, && default_0_179, + && default_0_179, && default_0_179, && default_0_179, && default_0_179, + && default_0_179, && default_0_179, && default_0_179, && default_0_179, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_179, val) + { + CASE (0_179, 0) : + { + static const IDESC * insns[4] = { + I (INSN_WR_TBR), I (INSN_WR_TBR_IMM), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_179) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_179) + } + CASE (0, 184) : + { + static const IDESC * insns[2] = { + I (INSN_JMPL), I (INSN_JMPL_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 185) : + { +#ifdef __GNUC__ + static const void *labels_0_185[16] = { + && case_0_185_0, && default_0_185, && default_0_185, && default_0_185, + && default_0_185, && default_0_185, && default_0_185, && default_0_185, + && default_0_185, && default_0_185, && default_0_185, && default_0_185, + && default_0_185, && default_0_185, && default_0_185, && default_0_185, + }; +#endif + static const IDESC * insns[16] = { + 0, I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_185, val) + { + CASE (0_185, 0) : + { + static const IDESC * insns[4] = { + I (INSN_RETT), I (INSN_RETT_IMM), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_185) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_185) + } + CASE (0, 186) : + { +#ifdef __GNUC__ + static const void *labels_0_186[16] = { + && case_0_186_0, && case_0_186_1, && case_0_186_2, && case_0_186_3, + && case_0_186_4, && case_0_186_5, && case_0_186_6, && case_0_186_7, + && default_0_186, && default_0_186, && default_0_186, && default_0_186, + && default_0_186, && default_0_186, && default_0_186, && default_0_186, + }; +#endif + static const IDESC * insns[16] = { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + I (INSN_X_INVALID), I (INSN_X_INVALID), + }; + unsigned int val; + val = (((insn >> 26) & (15 << 0))); + DECODE_SWITCH (0_186, val) + { + CASE (0_186, 0) : + { + static const IDESC * insns[4] = { + I (INSN_TN), I (INSN_TN_IMM), + I (INSN_TE), I (INSN_TE_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 1) : + { + static const IDESC * insns[4] = { + I (INSN_TLE), I (INSN_TLE_IMM), + I (INSN_TL), I (INSN_TL_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 2) : + { + static const IDESC * insns[4] = { + I (INSN_TLEU), I (INSN_TLEU_IMM), + I (INSN_TCS), I (INSN_TCS_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 3) : + { + static const IDESC * insns[4] = { + I (INSN_TNEG), I (INSN_TNEG_IMM), + I (INSN_TVS), I (INSN_TVS_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 4) : + { + static const IDESC * insns[4] = { + I (INSN_TA), I (INSN_TA_IMM), + I (INSN_TNE), I (INSN_TNE_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 5) : + { + static const IDESC * insns[4] = { + I (INSN_TG), I (INSN_TG_IMM), + I (INSN_TGE), I (INSN_TGE_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 6) : + { + static const IDESC * insns[4] = { + I (INSN_TGU), I (INSN_TGU_IMM), + I (INSN_TCC), I (INSN_TCC_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0_186, 7) : + { + static const IDESC * insns[4] = { + I (INSN_TPOS), I (INSN_TPOS_IMM), + I (INSN_TVC), I (INSN_TVC_IMM), + }; + unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0_186) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0_186) + } + CASE (0, 188) : + { + static const IDESC * insns[2] = { + I (INSN_SAVE), I (INSN_SAVE_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 189) : + { + static const IDESC * insns[2] = { + I (INSN_RESTORE), I (INSN_RESTORE_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 192) : + { + static const IDESC * insns[2] = { + I (INSN_LDUW_REG_REG), I (INSN_LDUW_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 193) : + { + static const IDESC * insns[2] = { + I (INSN_LDUB_REG_REG), I (INSN_LDUB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 194) : + { + static const IDESC * insns[2] = { + I (INSN_LDUH_REG_REG), I (INSN_LDUH_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 195) : + { + static const IDESC * insns[2] = { + I (INSN_LDD_REG_REG), I (INSN_LDD_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 196) : + { + static const IDESC * insns[2] = { + I (INSN_ST_REG_REG), I (INSN_ST_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 197) : + { + static const IDESC * insns[2] = { + I (INSN_STB_REG_REG), I (INSN_STB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 198) : + { + static const IDESC * insns[2] = { + I (INSN_STH_REG_REG), I (INSN_STH_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 199) : + { + static const IDESC * insns[2] = { + I (INSN_STD_REG_REG), I (INSN_STD_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 200) : + { + static const IDESC * insns[2] = { + I (INSN_LDSW_REG_REG), I (INSN_LDSW_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 201) : + { + static const IDESC * insns[2] = { + I (INSN_LDSB_REG_REG), I (INSN_LDSB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 202) : + { + static const IDESC * insns[2] = { + I (INSN_LDSH_REG_REG), I (INSN_LDSH_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 205) : + { + static const IDESC * insns[2] = { + I (INSN_LDSTUB_REG_REG), I (INSN_LDSTUB_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 207) : + { + static const IDESC * insns[2] = { + I (INSN_SWAP_REG_REG), I (INSN_SWAP_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + CASE (0, 224) : + { + static const IDESC * insns[2] = { + I (INSN_FP_LD_REG_REG), I (INSN_FP_LD_REG_IMM), + }; + unsigned int val = (((insn >> 13) & (1 << 0))); + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + DEFAULT (0) : + idecode = insns[val]; + GOTO_EXTRACT (idecode); + } + ENDSWITCH (0) + } +#undef I +#undef E + } + + /* Extraction is defered until the semantic code. */ + + extract: + return idecode; +} diff --git a/sim/sparc/decode32.h b/sim/sparc/decode32.h new file mode 100644 index 0000000..2d9873e --- /dev/null +++ b/sim/sparc/decode32.h @@ -0,0 +1,285 @@ +/* Decode header for sparc32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#ifndef SPARC32_DECODE_H +#define SPARC32_DECODE_H + +extern const IDESC *sparc32_decode (SIM_CPU *, IADDR, + CGEN_INSN_INT, CGEN_INSN_INT, + ARGBUF *); +extern void sparc32_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family sparc32. */ +typedef enum sparc32_insn_type { + SPARC32_INSN_X_INVALID, SPARC32_INSN_X_AFTER, SPARC32_INSN_X_BEFORE, SPARC32_INSN_X_CTI_CHAIN + , SPARC32_INSN_X_CHAIN, SPARC32_INSN_X_BEGIN, SPARC32_INSN_RD_ASR, SPARC32_INSN_WR_ASR + , SPARC32_INSN_WR_ASR_IMM, SPARC32_INSN_RD_PSR, SPARC32_INSN_WR_PSR, SPARC32_INSN_WR_PSR_IMM + , SPARC32_INSN_RD_WIM, SPARC32_INSN_WR_WIM, SPARC32_INSN_WR_WIM_IMM, SPARC32_INSN_RD_TBR + , SPARC32_INSN_WR_TBR, SPARC32_INSN_WR_TBR_IMM, SPARC32_INSN_LDSTUB_REG_REG, SPARC32_INSN_LDSTUB_REG_IMM + , SPARC32_INSN_LDSTUB_REG_REG_ASI, SPARC32_INSN_SWAP_REG_REG, SPARC32_INSN_SWAP_REG_IMM, SPARC32_INSN_SWAP_REG_REG_ASI + , SPARC32_INSN_LDSB_REG_REG, SPARC32_INSN_LDSB_REG_IMM, SPARC32_INSN_LDSB_REG_REG_ASI, SPARC32_INSN_LDUB_REG_REG + , SPARC32_INSN_LDUB_REG_IMM, SPARC32_INSN_LDUB_REG_REG_ASI, SPARC32_INSN_LDSH_REG_REG, SPARC32_INSN_LDSH_REG_IMM + , SPARC32_INSN_LDSH_REG_REG_ASI, SPARC32_INSN_LDUH_REG_REG, SPARC32_INSN_LDUH_REG_IMM, SPARC32_INSN_LDUH_REG_REG_ASI + , SPARC32_INSN_LDSW_REG_REG, SPARC32_INSN_LDSW_REG_IMM, SPARC32_INSN_LDSW_REG_REG_ASI, SPARC32_INSN_LDUW_REG_REG + , SPARC32_INSN_LDUW_REG_IMM, SPARC32_INSN_LDUW_REG_REG_ASI, SPARC32_INSN_LDD_REG_REG, SPARC32_INSN_LDD_REG_IMM + , SPARC32_INSN_LDD_REG_REG_ASI, SPARC32_INSN_STB_REG_REG, SPARC32_INSN_STB_REG_IMM, SPARC32_INSN_STB_REG_REG_ASI + , SPARC32_INSN_STH_REG_REG, SPARC32_INSN_STH_REG_IMM, SPARC32_INSN_STH_REG_REG_ASI, SPARC32_INSN_ST_REG_REG + , SPARC32_INSN_ST_REG_IMM, SPARC32_INSN_ST_REG_REG_ASI, SPARC32_INSN_STD_REG_REG, SPARC32_INSN_STD_REG_IMM + , SPARC32_INSN_STD_REG_REG_ASI, SPARC32_INSN_FP_LD_REG_REG, SPARC32_INSN_FP_LD_REG_IMM, SPARC32_INSN_FP_LD_REG_REG_ASI + , SPARC32_INSN_SETHI, SPARC32_INSN_ADD, SPARC32_INSN_ADD_IMM, SPARC32_INSN_SUB + , SPARC32_INSN_SUB_IMM, SPARC32_INSN_ADDCC, SPARC32_INSN_ADDCC_IMM, SPARC32_INSN_SUBCC + , SPARC32_INSN_SUBCC_IMM, SPARC32_INSN_ADDX, SPARC32_INSN_ADDX_IMM, SPARC32_INSN_SUBX + , SPARC32_INSN_SUBX_IMM, SPARC32_INSN_ADDXCC, SPARC32_INSN_ADDXCC_IMM, SPARC32_INSN_SUBXCC + , SPARC32_INSN_SUBXCC_IMM, SPARC32_INSN_AND, SPARC32_INSN_AND_IMM, SPARC32_INSN_ANDCC + , SPARC32_INSN_ANDCC_IMM, SPARC32_INSN_OR, SPARC32_INSN_OR_IMM, SPARC32_INSN_ORCC + , SPARC32_INSN_ORCC_IMM, SPARC32_INSN_XOR, SPARC32_INSN_XOR_IMM, SPARC32_INSN_XORCC + , SPARC32_INSN_XORCC_IMM, SPARC32_INSN_ANDN, SPARC32_INSN_ANDN_IMM, SPARC32_INSN_ANDNCC + , SPARC32_INSN_ANDNCC_IMM, SPARC32_INSN_ORN, SPARC32_INSN_ORN_IMM, SPARC32_INSN_ORNCC + , SPARC32_INSN_ORNCC_IMM, SPARC32_INSN_XNOR, SPARC32_INSN_XNOR_IMM, SPARC32_INSN_XNORCC + , SPARC32_INSN_XNORCC_IMM, SPARC32_INSN_SLL, SPARC32_INSN_SLL_IMM, SPARC32_INSN_SRL + , SPARC32_INSN_SRL_IMM, SPARC32_INSN_SRA, SPARC32_INSN_SRA_IMM, SPARC32_INSN_SMUL + , SPARC32_INSN_SMUL_IMM, SPARC32_INSN_SMUL_CC, SPARC32_INSN_SMUL_CC_IMM, SPARC32_INSN_UMUL + , SPARC32_INSN_UMUL_IMM, SPARC32_INSN_UMUL_CC, SPARC32_INSN_UMUL_CC_IMM, SPARC32_INSN_SDIV + , SPARC32_INSN_SDIV_IMM, SPARC32_INSN_SDIV_CC, SPARC32_INSN_SDIV_CC_IMM, SPARC32_INSN_UDIV + , SPARC32_INSN_UDIV_IMM, SPARC32_INSN_UDIV_CC, SPARC32_INSN_UDIV_CC_IMM, SPARC32_INSN_MULSCC + , SPARC32_INSN_SAVE, SPARC32_INSN_SAVE_IMM, SPARC32_INSN_RESTORE, SPARC32_INSN_RESTORE_IMM + , SPARC32_INSN_RETT, SPARC32_INSN_RETT_IMM, SPARC32_INSN_UNIMP, SPARC32_INSN_CALL + , SPARC32_INSN_JMPL, SPARC32_INSN_JMPL_IMM, SPARC32_INSN_BA, SPARC32_INSN_TA + , SPARC32_INSN_TA_IMM, SPARC32_INSN_BN, SPARC32_INSN_TN, SPARC32_INSN_TN_IMM + , SPARC32_INSN_BNE, SPARC32_INSN_TNE, SPARC32_INSN_TNE_IMM, SPARC32_INSN_BE + , SPARC32_INSN_TE, SPARC32_INSN_TE_IMM, SPARC32_INSN_BG, SPARC32_INSN_TG + , SPARC32_INSN_TG_IMM, SPARC32_INSN_BLE, SPARC32_INSN_TLE, SPARC32_INSN_TLE_IMM + , SPARC32_INSN_BGE, SPARC32_INSN_TGE, SPARC32_INSN_TGE_IMM, SPARC32_INSN_BL + , SPARC32_INSN_TL, SPARC32_INSN_TL_IMM, SPARC32_INSN_BGU, SPARC32_INSN_TGU + , SPARC32_INSN_TGU_IMM, SPARC32_INSN_BLEU, SPARC32_INSN_TLEU, SPARC32_INSN_TLEU_IMM + , SPARC32_INSN_BCC, SPARC32_INSN_TCC, SPARC32_INSN_TCC_IMM, SPARC32_INSN_BCS + , SPARC32_INSN_TCS, SPARC32_INSN_TCS_IMM, SPARC32_INSN_BPOS, SPARC32_INSN_TPOS + , SPARC32_INSN_TPOS_IMM, SPARC32_INSN_BNEG, SPARC32_INSN_TNEG, SPARC32_INSN_TNEG_IMM + , SPARC32_INSN_BVC, SPARC32_INSN_TVC, SPARC32_INSN_TVC_IMM, SPARC32_INSN_BVS + , SPARC32_INSN_TVS, SPARC32_INSN_TVS_IMM, SPARC32_INSN_MAX +} SPARC32_INSN_TYPE; + +#if ! WITH_SEM_SWITCH_FULL +#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,fn); +#else +#define SEMFULL(fn) +#endif + +#if ! WITH_SEM_SWITCH_FAST +#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc32,_semf_,fn); +#else +#define SEMFAST(fn) +#endif + +#define SEM(fn) SEMFULL (fn) SEMFAST (fn) + +/* The function version of the before/after handlers is always needed, + so we always want the SEMFULL declaration of them. */ +extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,x_before); +extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,x_after); + +SEM (x_invalid) +SEM (x_after) +SEM (x_before) +SEM (x_cti_chain) +SEM (x_chain) +SEM (x_begin) +SEM (rd_asr) +SEM (wr_asr) +SEM (wr_asr_imm) +SEM (rd_psr) +SEM (wr_psr) +SEM (wr_psr_imm) +SEM (rd_wim) +SEM (wr_wim) +SEM (wr_wim_imm) +SEM (rd_tbr) +SEM (wr_tbr) +SEM (wr_tbr_imm) +SEM (ldstub_reg_reg) +SEM (ldstub_reg_imm) +SEM (ldstub_reg_reg_asi) +SEM (swap_reg_reg) +SEM (swap_reg_imm) +SEM (swap_reg_reg_asi) +SEM (ldsb_reg_reg) +SEM (ldsb_reg_imm) +SEM (ldsb_reg_reg_asi) +SEM (ldub_reg_reg) +SEM (ldub_reg_imm) +SEM (ldub_reg_reg_asi) +SEM (ldsh_reg_reg) +SEM (ldsh_reg_imm) +SEM (ldsh_reg_reg_asi) +SEM (lduh_reg_reg) +SEM (lduh_reg_imm) +SEM (lduh_reg_reg_asi) +SEM (ldsw_reg_reg) +SEM (ldsw_reg_imm) +SEM (ldsw_reg_reg_asi) +SEM (lduw_reg_reg) +SEM (lduw_reg_imm) +SEM (lduw_reg_reg_asi) +SEM (ldd_reg_reg) +SEM (ldd_reg_imm) +SEM (ldd_reg_reg_asi) +SEM (stb_reg_reg) +SEM (stb_reg_imm) +SEM (stb_reg_reg_asi) +SEM (sth_reg_reg) +SEM (sth_reg_imm) +SEM (sth_reg_reg_asi) +SEM (st_reg_reg) +SEM (st_reg_imm) +SEM (st_reg_reg_asi) +SEM (std_reg_reg) +SEM (std_reg_imm) +SEM (std_reg_reg_asi) +SEM (fp_ld_reg_reg) +SEM (fp_ld_reg_imm) +SEM (fp_ld_reg_reg_asi) +SEM (sethi) +SEM (add) +SEM (add_imm) +SEM (sub) +SEM (sub_imm) +SEM (addcc) +SEM (addcc_imm) +SEM (subcc) +SEM (subcc_imm) +SEM (addx) +SEM (addx_imm) +SEM (subx) +SEM (subx_imm) +SEM (addxcc) +SEM (addxcc_imm) +SEM (subxcc) +SEM (subxcc_imm) +SEM (and) +SEM (and_imm) +SEM (andcc) +SEM (andcc_imm) +SEM (or) +SEM (or_imm) +SEM (orcc) +SEM (orcc_imm) +SEM (xor) +SEM (xor_imm) +SEM (xorcc) +SEM (xorcc_imm) +SEM (andn) +SEM (andn_imm) +SEM (andncc) +SEM (andncc_imm) +SEM (orn) +SEM (orn_imm) +SEM (orncc) +SEM (orncc_imm) +SEM (xnor) +SEM (xnor_imm) +SEM (xnorcc) +SEM (xnorcc_imm) +SEM (sll) +SEM (sll_imm) +SEM (srl) +SEM (srl_imm) +SEM (sra) +SEM (sra_imm) +SEM (smul) +SEM (smul_imm) +SEM (smul_cc) +SEM (smul_cc_imm) +SEM (umul) +SEM (umul_imm) +SEM (umul_cc) +SEM (umul_cc_imm) +SEM (sdiv) +SEM (sdiv_imm) +SEM (sdiv_cc) +SEM (sdiv_cc_imm) +SEM (udiv) +SEM (udiv_imm) +SEM (udiv_cc) +SEM (udiv_cc_imm) +SEM (mulscc) +SEM (save) +SEM (save_imm) +SEM (restore) +SEM (restore_imm) +SEM (rett) +SEM (rett_imm) +SEM (unimp) +SEM (call) +SEM (jmpl) +SEM (jmpl_imm) +SEM (ba) +SEM (ta) +SEM (ta_imm) +SEM (bn) +SEM (tn) +SEM (tn_imm) +SEM (bne) +SEM (tne) +SEM (tne_imm) +SEM (be) +SEM (te) +SEM (te_imm) +SEM (bg) +SEM (tg) +SEM (tg_imm) +SEM (ble) +SEM (tle) +SEM (tle_imm) +SEM (bge) +SEM (tge) +SEM (tge_imm) +SEM (bl) +SEM (tl) +SEM (tl_imm) +SEM (bgu) +SEM (tgu) +SEM (tgu_imm) +SEM (bleu) +SEM (tleu) +SEM (tleu_imm) +SEM (bcc) +SEM (tcc) +SEM (tcc_imm) +SEM (bcs) +SEM (tcs) +SEM (tcs_imm) +SEM (bpos) +SEM (tpos) +SEM (tpos_imm) +SEM (bneg) +SEM (tneg) +SEM (tneg_imm) +SEM (bvc) +SEM (tvc) +SEM (tvc_imm) +SEM (bvs) +SEM (tvs) +SEM (tvs_imm) + +#undef SEMFULL +#undef SEMFAST +#undef SEM + +/* Function unit handlers (user written). */ + +extern int sparc32_model_sparc32_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); + +/* Profiling before/after handlers (user written) */ + +extern void sparc32_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void sparc32_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* SPARC32_DECODE_H */ diff --git a/sim/sparc/dev64.c b/sim/sparc/dev64.c new file mode 100644 index 0000000..73236a4 --- /dev/null +++ b/sim/sparc/dev64.c @@ -0,0 +1,9 @@ +/* sparc64 device support + Copyright (C) 1999 Cygnus Solutions. */ + +#include "sim-main.h" +#include "dev64.h" + +#ifdef HAVE_DV_SOCKSER +#include "dv-sockser.h" +#endif diff --git a/sim/sparc/dev64.h b/sim/sparc/dev64.h new file mode 100644 index 0000000..689e0e7 --- /dev/null +++ b/sim/sparc/dev64.h @@ -0,0 +1,21 @@ +/* sparc64 device support + Copyright (C) 1999 Cygnus Solutions. */ + +#ifndef DEV64_H +#define DEV64_H + +/* From libgloss/sparc/erc32-io.c. */ + +#define ERC32_DEVICE_ADDR 0x1f80000 +#define ERC32_DEVICE_LEN (0x2000000 - 0x1f80000) + +#define RXADATA 0x01F800E0 +#define RXBDATA 0x01F800E4 +#define RXSTAT 0x01F800E8 + +extern device sparc_devices; + +/* FIXME: Temporary, until device support ready. */ +struct _device { int foo; }; + +#endif /* DEV64_H */ diff --git a/sim/sparc/model32.c b/sim/sparc/model32.c new file mode 100644 index 0000000..ba2e8d5 --- /dev/null +++ b/sim/sparc/model32.c @@ -0,0 +1,3516 @@ +/* Simulator model support for sparc32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc32 +#define WANT_CPU_SPARC32 + +#include "sim-main.h" + +/* The profiling data is recorded here, but is accessed via the profiling + mechanism. After all, this is information for profiling. */ + +#if WITH_PROFILE_MODEL_P + +/* Model handlers for each insn. */ + +static int +model_sparc32_def_rd_asr (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_RD_ASR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_ASR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_asr (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_ASR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_ASR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_asr_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_ASR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_ASR_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_rd_psr (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_psr (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_psr_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_rd_wim (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_wim (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_wim_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_rd_tbr (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_tbr (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_wr_tbr_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldstub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldstub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldstub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_swap_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_swap_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_swap_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_lduh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_lduh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_lduh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldsw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_lduw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_lduw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_lduw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldd_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldd_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ldd_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_stb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_stb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_stb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sth_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sth_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sth_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_st_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_st_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_st_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_std_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_std_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_std_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_fp_ld_reg_reg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_fp_ld_reg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_fp_ld_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ + EXTRACT_IFMT_SETHI_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_add (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_add_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sub (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sub_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_addcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_subcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_addx (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_addx_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_subx (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_subx_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_addxcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_subxcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_and (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_and_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_andcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_or (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_or_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_orcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xor (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xor_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xorcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_andn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_andn_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_andncc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_andncc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_orn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_orn_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_orncc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_orncc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xnor (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xnor_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xnorcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_xnorcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sll (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sll_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_srl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_srl_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sra (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sra_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_smul (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_smul_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_smul_cc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_smul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_umul (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_umul_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_umul_cc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_umul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sdiv_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sdiv_cc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_sdiv_cc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_udiv_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_udiv_cc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_udiv_cc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_mulscc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_save (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_save_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_restore (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_restore_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_rett (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_rett_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_unimp (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ + EXTRACT_IFMT_UNIMP_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_call (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ + IADDR i_disp30; + EXTRACT_IFMT_CALL_CODE + i_disp30 = f_disp30; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_jmpl_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ba (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ta (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ta_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_BA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tn (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tn_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bne (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tne (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tne_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_be (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_te (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_te_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_ble (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tle (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tle_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bge (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tge (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tge_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tl (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tl_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bgu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tgu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tgu_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bleu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tleu (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tleu_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tcc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tcc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bcs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tcs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tcs_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bpos (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tpos (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tpos_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bneg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tneg (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tneg_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bvc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tvc (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tvc_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_bvs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tvs (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +static int +model_sparc32_def_tvs_imm (SIM_CPU *current_cpu, void *sem_arg) +{ + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + IADDR UNUSED pc = GET_H_PC (); + CGEN_INSN_INT insn = abuf->insn; + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +} + +/* We assume UNIT_NONE == 0 because the tables don't always terminate + entries with it. */ + +/* Model timing data for `sparc32-def'. */ + +static const INSN_TIMING sparc32_def_timing[] = { + { SPARC32_INSN_X_INVALID, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_X_AFTER, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_X_BEFORE, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_X_CHAIN, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_X_BEGIN, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RD_ASR, model_sparc32_def_rd_asr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_ASR, model_sparc32_def_wr_asr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_ASR_IMM, model_sparc32_def_wr_asr_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RD_PSR, model_sparc32_def_rd_psr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_PSR, model_sparc32_def_wr_psr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_PSR_IMM, model_sparc32_def_wr_psr_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RD_WIM, model_sparc32_def_rd_wim, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_WIM, model_sparc32_def_wr_wim, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_WIM_IMM, model_sparc32_def_wr_wim_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RD_TBR, model_sparc32_def_rd_tbr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_TBR, model_sparc32_def_wr_tbr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_WR_TBR_IMM, model_sparc32_def_wr_tbr_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSTUB_REG_REG, model_sparc32_def_ldstub_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSTUB_REG_IMM, model_sparc32_def_ldstub_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSTUB_REG_REG_ASI, model_sparc32_def_ldstub_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SWAP_REG_REG, model_sparc32_def_swap_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SWAP_REG_IMM, model_sparc32_def_swap_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SWAP_REG_REG_ASI, model_sparc32_def_swap_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSB_REG_REG, model_sparc32_def_ldsb_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSB_REG_IMM, model_sparc32_def_ldsb_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSB_REG_REG_ASI, model_sparc32_def_ldsb_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUB_REG_REG, model_sparc32_def_ldub_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUB_REG_IMM, model_sparc32_def_ldub_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUB_REG_REG_ASI, model_sparc32_def_ldub_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSH_REG_REG, model_sparc32_def_ldsh_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSH_REG_IMM, model_sparc32_def_ldsh_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSH_REG_REG_ASI, model_sparc32_def_ldsh_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUH_REG_REG, model_sparc32_def_lduh_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUH_REG_IMM, model_sparc32_def_lduh_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUH_REG_REG_ASI, model_sparc32_def_lduh_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSW_REG_REG, model_sparc32_def_ldsw_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSW_REG_IMM, model_sparc32_def_ldsw_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDSW_REG_REG_ASI, model_sparc32_def_ldsw_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUW_REG_REG, model_sparc32_def_lduw_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUW_REG_IMM, model_sparc32_def_lduw_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDUW_REG_REG_ASI, model_sparc32_def_lduw_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDD_REG_REG, model_sparc32_def_ldd_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDD_REG_IMM, model_sparc32_def_ldd_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_LDD_REG_REG_ASI, model_sparc32_def_ldd_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STB_REG_REG, model_sparc32_def_stb_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STB_REG_IMM, model_sparc32_def_stb_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STB_REG_REG_ASI, model_sparc32_def_stb_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STH_REG_REG, model_sparc32_def_sth_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STH_REG_IMM, model_sparc32_def_sth_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STH_REG_REG_ASI, model_sparc32_def_sth_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ST_REG_REG, model_sparc32_def_st_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ST_REG_IMM, model_sparc32_def_st_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ST_REG_REG_ASI, model_sparc32_def_st_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STD_REG_REG, model_sparc32_def_std_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STD_REG_IMM, model_sparc32_def_std_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_STD_REG_REG_ASI, model_sparc32_def_std_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_FP_LD_REG_REG, model_sparc32_def_fp_ld_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_FP_LD_REG_IMM, model_sparc32_def_fp_ld_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_FP_LD_REG_REG_ASI, model_sparc32_def_fp_ld_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SETHI, model_sparc32_def_sethi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADD, model_sparc32_def_add, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADD_IMM, model_sparc32_def_add_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUB, model_sparc32_def_sub, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUB_IMM, model_sparc32_def_sub_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADDCC, model_sparc32_def_addcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADDCC_IMM, model_sparc32_def_addcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUBCC, model_sparc32_def_subcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUBCC_IMM, model_sparc32_def_subcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADDX, model_sparc32_def_addx, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADDX_IMM, model_sparc32_def_addx_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUBX, model_sparc32_def_subx, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUBX_IMM, model_sparc32_def_subx_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADDXCC, model_sparc32_def_addxcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ADDXCC_IMM, model_sparc32_def_addxcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUBXCC, model_sparc32_def_subxcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SUBXCC_IMM, model_sparc32_def_subxcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_AND, model_sparc32_def_and, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_AND_IMM, model_sparc32_def_and_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ANDCC, model_sparc32_def_andcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ANDCC_IMM, model_sparc32_def_andcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_OR, model_sparc32_def_or, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_OR_IMM, model_sparc32_def_or_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ORCC, model_sparc32_def_orcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ORCC_IMM, model_sparc32_def_orcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XOR, model_sparc32_def_xor, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XOR_IMM, model_sparc32_def_xor_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XORCC, model_sparc32_def_xorcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XORCC_IMM, model_sparc32_def_xorcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ANDN, model_sparc32_def_andn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ANDN_IMM, model_sparc32_def_andn_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ANDNCC, model_sparc32_def_andncc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ANDNCC_IMM, model_sparc32_def_andncc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ORN, model_sparc32_def_orn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ORN_IMM, model_sparc32_def_orn_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ORNCC, model_sparc32_def_orncc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_ORNCC_IMM, model_sparc32_def_orncc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XNOR, model_sparc32_def_xnor, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XNOR_IMM, model_sparc32_def_xnor_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XNORCC, model_sparc32_def_xnorcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_XNORCC_IMM, model_sparc32_def_xnorcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SLL, model_sparc32_def_sll, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SLL_IMM, model_sparc32_def_sll_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SRL, model_sparc32_def_srl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SRL_IMM, model_sparc32_def_srl_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SRA, model_sparc32_def_sra, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SRA_IMM, model_sparc32_def_sra_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SMUL, model_sparc32_def_smul, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SMUL_IMM, model_sparc32_def_smul_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SMUL_CC, model_sparc32_def_smul_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SMUL_CC_IMM, model_sparc32_def_smul_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UMUL, model_sparc32_def_umul, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UMUL_IMM, model_sparc32_def_umul_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UMUL_CC, model_sparc32_def_umul_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UMUL_CC_IMM, model_sparc32_def_umul_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SDIV, model_sparc32_def_sdiv, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SDIV_IMM, model_sparc32_def_sdiv_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SDIV_CC, model_sparc32_def_sdiv_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SDIV_CC_IMM, model_sparc32_def_sdiv_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UDIV, model_sparc32_def_udiv, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UDIV_IMM, model_sparc32_def_udiv_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UDIV_CC, model_sparc32_def_udiv_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UDIV_CC_IMM, model_sparc32_def_udiv_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_MULSCC, model_sparc32_def_mulscc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SAVE, model_sparc32_def_save, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_SAVE_IMM, model_sparc32_def_save_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RESTORE, model_sparc32_def_restore, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RESTORE_IMM, model_sparc32_def_restore_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RETT, model_sparc32_def_rett, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_RETT_IMM, model_sparc32_def_rett_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_UNIMP, model_sparc32_def_unimp, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_CALL, model_sparc32_def_call, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_JMPL, model_sparc32_def_jmpl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_JMPL_IMM, model_sparc32_def_jmpl_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BA, model_sparc32_def_ba, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TA, model_sparc32_def_ta, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TA_IMM, model_sparc32_def_ta_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BN, model_sparc32_def_bn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TN, model_sparc32_def_tn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TN_IMM, model_sparc32_def_tn_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BNE, model_sparc32_def_bne, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TNE, model_sparc32_def_tne, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TNE_IMM, model_sparc32_def_tne_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BE, model_sparc32_def_be, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TE, model_sparc32_def_te, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TE_IMM, model_sparc32_def_te_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BG, model_sparc32_def_bg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TG, model_sparc32_def_tg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TG_IMM, model_sparc32_def_tg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BLE, model_sparc32_def_ble, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TLE, model_sparc32_def_tle, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TLE_IMM, model_sparc32_def_tle_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BGE, model_sparc32_def_bge, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TGE, model_sparc32_def_tge, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TGE_IMM, model_sparc32_def_tge_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BL, model_sparc32_def_bl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TL, model_sparc32_def_tl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TL_IMM, model_sparc32_def_tl_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BGU, model_sparc32_def_bgu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TGU, model_sparc32_def_tgu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TGU_IMM, model_sparc32_def_tgu_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BLEU, model_sparc32_def_bleu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TLEU, model_sparc32_def_tleu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TLEU_IMM, model_sparc32_def_tleu_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BCC, model_sparc32_def_bcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TCC, model_sparc32_def_tcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TCC_IMM, model_sparc32_def_tcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BCS, model_sparc32_def_bcs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TCS, model_sparc32_def_tcs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TCS_IMM, model_sparc32_def_tcs_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BPOS, model_sparc32_def_bpos, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TPOS, model_sparc32_def_tpos, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TPOS_IMM, model_sparc32_def_tpos_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BNEG, model_sparc32_def_bneg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TNEG, model_sparc32_def_tneg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TNEG_IMM, model_sparc32_def_tneg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BVC, model_sparc32_def_bvc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TVC, model_sparc32_def_tvc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TVC_IMM, model_sparc32_def_tvc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_BVS, model_sparc32_def_bvs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TVS, model_sparc32_def_tvs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, + { SPARC32_INSN_TVS_IMM, model_sparc32_def_tvs_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, +}; + +#endif /* WITH_PROFILE_MODEL_P */ + +static void +sparc32_def_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SPARC32_DEF_DATA)); +} + +#if WITH_PROFILE_MODEL_P +#define TIMING_DATA(td) td +#else +#define TIMING_DATA(td) 0 +#endif + +static const MODEL sparc_v8_models[] = +{ + { "sparc32-def", & sparc_v8_mach, MODEL_SPARC32_DEF, TIMING_DATA (& sparc32_def_timing[0]), sparc32_def_model_init }, + { 0 } +}; + +static const MODEL sparclite_models[] = +{ + { 0 } +}; + +/* The properties of this cpu's implementation. */ + +static const MACH_IMP_PROPERTIES sparc32_imp_properties = +{ + sizeof (SIM_CPU), +#if WITH_SCACHE + sizeof (SCACHE) +#else + 0 +#endif +}; + + +static void +sparc32_prepare_run (SIM_CPU *cpu) +{ + if (CPU_IDESC (cpu) == NULL) + sparc32_init_idesc_table (cpu); +} + +static const CGEN_INSN * +sparc32_get_idata (SIM_CPU *cpu, int inum) +{ + return CPU_IDESC (cpu) [inum].idata; +} + +static void +sparc_v8_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = sparc32_fetch_register; + CPU_REG_STORE (cpu) = sparc32_store_register; + CPU_PC_FETCH (cpu) = sparc32_h_pc_get; + CPU_PC_STORE (cpu) = sparc32_h_pc_set; + CPU_GET_IDATA (cpu) = sparc32_get_idata; + CPU_MAX_INSNS (cpu) = SPARC32_INSN_MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = sparc32_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_full; +#endif +} + +const MACH sparc_v8_mach = +{ + "sparc-v8", "sparc", + 32, 32, & sparc_v8_models[0], & sparc32_imp_properties, + sparc_v8_init_cpu, + sparc32_prepare_run +}; + +static void +sparclite_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = sparc32_fetch_register; + CPU_REG_STORE (cpu) = sparc32_store_register; + CPU_PC_FETCH (cpu) = sparc32_h_pc_get; + CPU_PC_STORE (cpu) = sparc32_h_pc_set; + CPU_GET_IDATA (cpu) = sparc32_get_idata; + CPU_MAX_INSNS (cpu) = SPARC32_INSN_MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = sparc32_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_full; +#endif +} + +const MACH sparclite_mach = +{ + "sparclite", "sparc_sparclite", + 32, 32, & sparclite_models[0], & sparc32_imp_properties, + sparclite_init_cpu, + sparc32_prepare_run +}; + diff --git a/sim/sparc/sem32.c b/sim/sparc/sem32.c new file mode 100644 index 0000000..cb8a377 --- /dev/null +++ b/sim/sparc/sem32.c @@ -0,0 +1,5444 @@ +/* Simulator instruction semantics for sparc32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1999 Cygnus Solutions, Inc. + +This file is part of the Cygnus Simulators. + + +*/ + +#define WANT_CPU sparc32 +#define WANT_CPU_SPARC32 + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +#undef GET_ATTR +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) + +/* x-invalid: --invalid-- */ + +SEM_STATUS +SEM_FN_NAME (sparc32,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE + /* Update the recorded pc in the cpu state struct. */ + SET_H_PC (pc); +#endif + sim_engine_invalid_insn (current_cpu, pc); + sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n"); + /* NOTREACHED */ + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-after: --after-- */ + +SEM_STATUS +SEM_FN_NAME (sparc32,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC32 + sparc32_pbb_after (current_cpu, sem_arg); +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-before: --before-- */ + +SEM_STATUS +SEM_FN_NAME (sparc32,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC32 + sparc32_pbb_before (current_cpu, sem_arg); +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-cti-chain: --cti-chain-- */ + +SEM_STATUS +SEM_FN_NAME (sparc32,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC32 +#ifdef DEFINE_SWITCH + vpc = sparc32_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_npc_ptr, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = sparc32_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-chain: --chain-- */ + +SEM_STATUS +SEM_FN_NAME (sparc32,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC32 + vpc = sparc32_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* x-begin: --begin-- */ + +SEM_STATUS +SEM_FN_NAME (sparc32,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + EXTRACT_IFMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_CODE + + { +#if WITH_SCACHE_PBB_SPARC32 +#ifdef DEFINE_SWITCH + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = sparc32_pbb_begin (current_cpu, FAST_P); +#else + vpc = sparc32_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#endif +#endif + } + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* rd-asr: rd $rdasr,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,rd_asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_RD_ASR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_ASR_CODE + + { + SI opval = CPU (h_asr[f_rs1]); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-asr: wr $rs1,$rs2,$wrasr */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_ASR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_ASR_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + CPU (h_asr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "wrasr", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-asr-imm: wr $rs1,$simm13,$wrasr */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_asr_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_ASR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_ASR_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + CPU (h_asr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "wrasr", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* rd-psr: rd %psr,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,rd_psr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_PSR_CODE + + { + SI opval = GET_H_PSR (); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-psr: wr $rs1,$rs2,%psr */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_psr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_PSR (opval); + TRACE_RESULT (current_cpu, abuf, "psr-0", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-psr-imm: wr $rs1,$simm13,%psr */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_psr_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_PSR (opval); + TRACE_RESULT (current_cpu, abuf, "psr-0", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* rd-wim: rd %wim,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,rd_wim) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_PSR_CODE + + { + SI opval = GET_H_WIM (); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-wim: wr $rs1,$rs2,%wim */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_wim) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_WIM (opval); + TRACE_RESULT (current_cpu, abuf, "wim-0", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-wim-imm: wr $rs1,$simm13,%wim */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_wim_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_WIM (opval); + TRACE_RESULT (current_cpu, abuf, "wim-0", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* rd-tbr: rd %tbr,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,rd_tbr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_RD_PSR_CODE + + { + SI opval = GET_H_TBR (); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-tbr: wr $rs1,$rs2,%tbr */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_tbr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_TBR (opval); + TRACE_RESULT (current_cpu, abuf, "tbr-0", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* wr-tbr-imm: wr $rs1,$simm13,%tbr */ + +SEM_STATUS +SEM_FN_NAME (sparc32,wr_tbr_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_TBR (opval); + TRACE_RESULT (current_cpu, abuf, "tbr-0", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldstub-reg+reg: ldstub [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldstub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +sparc32_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldstub-reg+imm: ldstub [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldstub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +sparc32_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldstub-reg+reg/asi: ldstub [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldstub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + +sparc32_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* swap-reg+reg: swap [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,swap_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +sparc32_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* swap-reg+imm: swap [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,swap_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +sparc32_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* swap-reg+reg/asi: swap [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,swap_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + +sparc32_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsb-reg+reg: ldsb [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsb-reg+imm: ldsb [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsb-reg+reg/asi: ldsb [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldub-reg+reg: ldub [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldub-reg+imm: ldub [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldub-reg+reg/asi: ldub [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsh-reg+reg: ldsh [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsh-reg+imm: ldsh [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsh-reg+reg/asi: ldsh [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduh-reg+reg: lduh [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,lduh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduh-reg+imm: lduh [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,lduh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduh-reg+reg/asi: lduh [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,lduh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsw-reg+reg: ldsw [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsw-reg+imm: ldsw [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldsw-reg+reg/asi: ldsw [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldsw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduw-reg+reg: lduw [$rs1+$rs2],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,lduw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduw-reg+imm: lduw [$rs1+$simm13],$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,lduw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* lduw-reg+reg/asi: lduw [$rs1+$rs2]$asi,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,lduw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldd-reg+reg: ldd [$rs1+$rs2],$rdd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldd_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + +do { + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); + SET_H_GR (((f_rd) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldd-reg+imm: ldd [$rs1+$simm13],$rdd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldd_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + +do { + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4))); + SET_H_GR (((f_rd) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* ldd-reg+reg/asi: ldd [$rs1+$rs2]$asi,$rdd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ldd_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + +do { + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); + } + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); + SET_H_GR (((f_rd) + (1)), opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stb-reg+reg: stb $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,stb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + QI opval = GET_H_GR (f_rd); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stb-reg+imm: stb $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,stb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + QI opval = GET_H_GR (f_rd); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* stb-reg+reg/asi: stb $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc32,stb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + QI opval = GET_H_GR (f_rd); + SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sth-reg+reg: sth $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sth_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + HI opval = GET_H_GR (f_rd); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sth-reg+imm: sth $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sth_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + HI opval = GET_H_GR (f_rd); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sth-reg+reg/asi: sth $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sth_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + HI opval = GET_H_GR (f_rd); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* st-reg+reg: st $rd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,st_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* st-reg+imm: st $rd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,st_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* st-reg+reg/asi: st $rd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc32,st_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE + + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* std-reg+reg: std $rdd,[$rs1+$rs2] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,std_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_CODE + +do { + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (((f_rd) + (1))); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* std-reg+imm: std $rdd,[$rs1+$simm13] */ + +SEM_STATUS +SEM_FN_NAME (sparc32,std_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_IMM_CODE + +do { + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (((f_rd) + (1))); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* std-reg+reg/asi: std $rdd,[$rs1+$rs2]$asi */ + +SEM_STATUS +SEM_FN_NAME (sparc32,std_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDD_REG_REG_ASI_CODE + +do { + { + SI opval = GET_H_GR (f_rd); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = GET_H_GR (((f_rd) + (1))); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* fp-ld-reg+reg: ld [$rs1+$rs2],$frd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,fp_ld_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_CODE + +do { +sparc32_hw_trap (current_cpu, pc, TRAP32_FP_DIS); + { + SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + CPU (h_fr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* fp-ld-reg+imm: ld [$rs1+$simm13],$frd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,fp_ld_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_IMM_CODE + +do { +sparc32_hw_trap (current_cpu, pc, TRAP32_FP_DIS); + { + SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); + CPU (h_fr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* fp-ld-reg+reg/asi: ld [$rs1+$rs2]$asi,$frd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,fp_ld_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE + +do { +sparc32_hw_trap (current_cpu, pc, TRAP32_FP_DIS); + { + SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); + CPU (h_fr[f_rd]) = opval; + TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sethi: sethi $hi22,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sethi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ + EXTRACT_IFMT_SETHI_CODE + + { + SI opval = SLLSI (f_hi22, 10); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* add: add $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* add-imm: add $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,add_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sub: sub $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sub-imm: sub $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sub_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addcc: addcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,addcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addcc-imm: addcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,addcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, 0); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subcc: subcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,subcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subcc-imm: subcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,subcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, 0); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addx: addx $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addx-imm: addx $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,addx_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subx: subx $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subx-imm: subx $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,subx_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addxcc: addxcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,addxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* addxcc-imm: addxcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,addxcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + { + BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subxcc: subxcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,subxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* subxcc-imm: subxcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,subxcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + SI tmp_x; + tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + { + BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* and: and $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* and-imm: and $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,and_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andcc: andcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,andcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andcc-imm: andcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,andcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* or: or $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* or-imm: or $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,or_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orcc: orcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,orcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orcc-imm: orcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,orcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xor: xor $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xor-imm: xor $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xorcc: xorcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xorcc-imm: xorcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andn: andn $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,andn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andn-imm: andn $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,andn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andncc: andncc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,andncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* andncc-imm: andncc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,andncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orn: orn $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,orn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orn-imm: orn $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,orn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orncc: orncc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,orncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* orncc-imm: orncc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,orncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnor: xnor $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnor-imm: xnor $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xnor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnorcc: xnorcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xnorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* xnorcc-imm: xnorcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,xnorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { +do { + { + BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); + { + SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sll: sll $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = SLLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sll-imm: sll $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sll_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = SLLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* srl: srl $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = SRLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* srl-imm: srl $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,srl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = SRLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sra: sra $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = SRASI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sra-imm: sra $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sra_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = SRASI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul: smul $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,smul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul-imm: smul $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,smul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul-cc: smulcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,smul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* smul-cc-imm: smulcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,smul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul: umul $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul-imm: umul $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,umul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul-cc: umulcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,umul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* umul-cc-imm: umulcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,umul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_res; + tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); + { + SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } + { + SI opval = TRUNCDISI (tmp_res); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (TRUNCDISI (tmp_res), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sdiv: sdiv $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTSIDI (GET_H_GR (f_rs2)))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sdiv-imm: sdiv $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sdiv_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTHIDI (f_simm13))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sdiv-cc: sdivcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sdiv_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTSIDI (GET_H_GR (f_rs2)))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (GET_H_GR (f_rd), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (GET_H_GR (f_rd), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* sdiv-cc-imm: sdivcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,sdiv_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTHIDI (f_simm13))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (GET_H_GR (f_rd), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (GET_H_GR (f_rd), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* udiv: udiv $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,udiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTSIDI (GET_H_GR (f_rs2)))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* udiv-imm: udiv $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,udiv_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTHIDI (f_simm13))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* udiv-cc: udivcc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,udiv_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTSIDI (GET_H_GR (f_rs2)))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (GET_H_GR (f_rd), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (GET_H_GR (f_rd), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* udiv-cc-imm: udivcc $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,udiv_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + DI tmp_dividend; + tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); + { + SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTHIDI (f_simm13))); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + BI opval = EQSI (GET_H_GR (f_rd), 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } + { + BI opval = LTSI (GET_H_GR (f_rd), 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = 0; + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* mulscc: mulscc $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,mulscc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + SI tmp_rd_tmp; + SI tmp_add_tmp; + SI tmp_tmp; + tmp_tmp = SRLSI (GET_H_GR (f_rs1), 1); +if (NEBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)), 0)) { + tmp_tmp = ORSI (tmp_tmp, 0x80000000); +} +if (NESI (ANDSI (GET_H_Y (), 1), 0)) { + tmp_add_tmp = GET_H_GR (f_rs2); +} else { + tmp_add_tmp = 0; +} + tmp_rd_tmp = ADDSI (tmp_tmp, tmp_add_tmp); +do { + SI tmp_x; + tmp_x = ADDCSI (tmp_tmp, tmp_add_tmp, 0); + { + BI opval = ADDCFSI (tmp_tmp, tmp_add_tmp, 0); + CPU (h_icc_c) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); + } + { + BI opval = ADDOFSI (tmp_tmp, tmp_add_tmp, 0); + CPU (h_icc_v) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); + } + { + BI opval = LTSI (tmp_x, 0); + CPU (h_icc_n) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); + } + { + BI opval = EQSI (tmp_x, 0); + CPU (h_icc_z) = opval; + TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); + } +} while (0); + { + SI opval = SRLSI (GET_H_Y (), 1); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } +if (NESI (ANDSI (GET_H_GR (f_rs1), 1), 0)) { + { + SI opval = ORSI (GET_H_Y (), 0x80000000); + SET_H_Y (opval); + TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); + } +} + { + SI opval = tmp_rd_tmp; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +} while (0); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* save: save $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,save) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = sparc32_do_save (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* save-imm: save $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,save_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = sparc32_do_save (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* restore: restore $rs1,$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,restore) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + + { + SI opval = sparc32_do_restore (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* restore-imm: restore $rs1,$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,restore_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + + { + SI opval = sparc32_do_restore (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* rett: rett $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,rett) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_CODE + +do { + { + USI opval = sparc32_do_rett (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* rett-imm: rett $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,rett_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_WR_PSR_IMM_CODE + +do { + { + USI opval = sparc32_do_rett (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* unimp: unimp $imm22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,unimp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ + EXTRACT_IFMT_UNIMP_CODE + +sparc_do_unimp (current_cpu, pc, f_imm22); + + SEM_NBRANCH_FINI (vpc, 0); + return status; +} + +/* call: call $disp30 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ + IADDR i_disp30; + EXTRACT_IFMT_CALL_CODE + i_disp30 = f_disp30; + +do { + { + SI opval = pc; + SET_H_GR (((UINT) 15), opval); + TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); + } +do { + { + USI opval = i_disp30; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* jmpl: jmpl $rs1+$rs2,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,jmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_REG_CODE + +do { + { + SI opval = pc; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + USI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* jmpl-imm: jmpl $rs1+$simm13,$rd */ + +SEM_STATUS +SEM_FN_NAME (sparc32,jmpl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ + EXTRACT_IFMT_LDSTUB_REG_IMM_CODE + +do { + { + SI opval = pc; + SET_H_GR (f_rd, opval); + TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); + } +do { + { + USI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ba: ba$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ba) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +do { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} while (0); +} while (0); + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ta: ta $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ta) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ta-imm: ta $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ta_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } + + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bn: bn$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_BA_CODE + +do { +do { +do { } while (0); /*nop*/ +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} while (0); +} while (0); + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tn: tn $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tn-imm: tn $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +do { } while (0); /*nop*/ + + SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bne: bne$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_z))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tne: tne $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_z))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tne-imm: tne $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tne_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_z))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* be: be$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_z)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* te: te $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,te) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_z)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* te-imm: te $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,te_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_z)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bg: bg$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tg: tg $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tg-imm: tg $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* ble: ble$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tle: tle $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tle) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tle-imm: tle $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tle_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 6); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bge: bge$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tge: tge $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tge-imm: tge $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tge_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bl: bl$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tl: tl $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tl-imm: tl $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bgu: bgu$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tgu: tgu $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tgu-imm: tgu $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tgu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bleu: bleu$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tleu: tleu $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tleu-imm: tleu $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tleu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bcc: bcc$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_c))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcc: tcc $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_c))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcc-imm: tcc $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_c))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bcs: bcs$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_c)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcs: tcs $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_c)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tcs-imm: tcs $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tcs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_c)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bpos: bpos$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_n))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tpos: tpos $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_n))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tpos-imm: tpos $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tpos_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_n))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bneg: bneg$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_n)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tneg: tneg $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_n)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tneg-imm: tneg $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tneg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_n)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bvc: bvc$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (NOTBI (CPU (h_icc_v))) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvc: tvc $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (NOTBI (CPU (h_icc_v))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvc-imm: tvc $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tvc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (NOTBI (CPU (h_icc_v))) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* bvs: bvs$a $disp22 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,bvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ + IADDR i_disp22; + EXTRACT_IFMT_BA_CODE + i_disp22 = f_disp22; + +do { +if (CPU (h_icc_v)) { + { + USI opval = i_disp22; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} else { +SEM_ANNUL_INSN (current_cpu, pc, f_a); +} +} while (0); + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvs: tvs $rs1,$rs2 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_CODE + +if (CPU (h_icc_v)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + +/* tvs-imm: tvs $rs1,$simm13 */ + +SEM_STATUS +SEM_FN_NAME (sparc32,tvs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) +{ + SEM_STATUS status = 0; + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = GET_H_PC (); + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ + EXTRACT_IFMT_TA_IMM_CODE + +if (CPU (h_icc_v)) { + { + USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); +; + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); + return status; +} + diff --git a/sim/sparc/sparc64.c b/sim/sparc/sparc64.c new file mode 100644 index 0000000..fb62187 --- /dev/null +++ b/sim/sparc/sparc64.c @@ -0,0 +1,264 @@ +/* sparc64 simulator support code + Copyright (C) 1999 Cygnus Solutions. */ + +#define WANT_CPU_SPARC64 + +#include "sim-main.h" +#include <signal.h> +#include "libiberty.h" +#include "bfd.h" +#include "cgen-mem.h" +#include "cgen-ops.h" +#include "targ-vals.h" +#include "trap64.h" + +/* Initialize the program counter. */ + +void +sparc64_init_pc (SIM_CPU *current_cpu, DI pc, DI npc) +{ + SET_H_PC (pc); + SET_H_NPC (npc); +} + +#if WITH_PROFILE_MODEL_P + +void +sparc64_model_mark_get_h_gr (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) +{ + if ((CPU_PROFILE_STATE (cpu)->h_gr & abuf->h_gr_get) != 0) + { + PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2; + if (TRACE_INSN_P (cpu)) + cgen_trace_printf (cpu, " ; Load stall of 2 cycles."); + } +} + +void +sparc64_model_mark_set_h_gr (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) +{ +} + +void +sparc64_model_mark_busy_reg (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) +{ + CPU_PROFILE_STATE (cpu)->h_gr = abuf->h_gr_set; +} + +void +sparc64_model_mark_unbusy_reg (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) +{ + CPU_PROFILE_STATE (cpu)->h_gr = 0; +} + +#endif /* WITH_PROFILE_MODEL_P */ + +UDI +sparc64_h_gr_get (SIM_CPU *current_cpu, unsigned int regno) +{ + return GET_INT_REG (cpu, regno); +} + +void +sparc64_h_gr_set (SIM_CPU *current_cpu, unsigned int regno, UDI new_val) +{ + SET_INT_REG (cpu, regno, new_val); +} + +DI * +sparc64_h_gr_regno_get_addr (SIM_CPU *current_cpu, int regno) +{ +} + +DI +sparc64_h_gr_regno_get (SIM_CPU *current_cpu, int regno) +{ +} + +void +sparc64_h_gr_regno_set (SIM_CPU *current_cpu, int regno, DI new_val) +{ +} + +DI +sparc64_do_save (SIM_CPU *current_cpu, DI rs1, DI rs2_simm13) +{ + DI rd; + + /* If this is a user program, watch for stack overflow ... */ + +#if 0 + if (STATE_user_prog && GET_AREG (GET_REG (REG_SP)) < mem_end) + { + if (user_prog) + fprintf (stderr, "sim: stack space exhausted!\n"); + sim_signal (SIM_SIGACCESS); + return 0; + } +#endif + + if (GET_CANSAVE (current_cpu) == 0) + { + return trap (TRAP_SPILL); + } + if (GET_CLEANWIN (current_cpu) - GET_CANRESTORE (current_cpu) == 0) + { + return trap (TRAP_CLEAN_WINDOW); + } + + /* The calculation is done using the old window's values + [those passed in to us]. */ + + rd = ADDDI (rs1, rs2_simm13); + + /* Switch to a new window. */ + + save_window (); + + return rd; +} + +DI +sparc64_do_restore (SIM_CPU *current_cpu, DI rs1, DI rs2_simm13) +{ + DI rd; + + return rd; + +} + +/* Initialize the register window mechanism. */ + +void +sparc64_alloc_register_windows (SIM_CPU *cpu, int nwindows) +{ + int ag,i,r,w; + DI *(*v)[32]; + + cpu->greg_lookup_table = (DI *(*)[2][32]) xmalloc (nwindows * 2 * 32 * sizeof (void *)); + cpu->globals = (DI (*)[][8]) zalloc (2 * 8 * sizeof (DI)); + cpu->win_regs = (DI (*)[][16]) zalloc (nwindows * 16 * sizeof (DI)); + + v = &cpu->greg_lookup_table[0][0]; + for (w = 0; w < nwindows; w++) + { + for (ag = 0; ag < 2; ag++, v++) + { + /* Initialize pointers to the global registers ... */ + for (r = 0; r < 8; r++) + (*v)[r] = &cpu->globals[ag][r]; + + /* Initialize pointers to the output registers ... */ + for (r = 0; r < 8; r++) + (*v)[r + 8] = &cpu->win_regs[(w == nwindows - 1 ? 0 : ((w + 1) * 16)) + r]; + + /* Initialize pointers to the local registers ... */ + for (r = 0; r < 8; r++) + (*v)[r + 16] = &cpu->win_regs[(w * 16) + 8 + r]; + + /* Initialize pointers to the input registers ... */ + for (r = 0; r < 8; r++) + (*v)[r + 24] = &cpu->win_regs[(w * 16) + r]; + } + } +} + +void +sparc64_free_register_windows (SIM_CPU *cpu) +{ + free (cpu->win_regs); + cpu->win_regs = NULL; + free (cpu->globals); + cpu->globals = NULL; + free (cpu->greg_lookup_table); + cpu->greg_lookup_table = NULL; +} + +/* Assign a new value to CWP. + + The register windows are recorded in a seemingly backwards manner. + %i0-7 live at lower addresses in memory than %o0-7 (even though they + have higher register numbers). This is because the stack grows upwards + in the sense that CWP increases during a "push" operation. + + FIXME: True for v9, but also for v8? */ + +void +sparc64_set_cwp (SIM_CPU *current_cpu, int x) +{ + if (x < 0 || x >= GET_NWINDOWS (cpu)) + abort (); + + /* We can't use SET_CWP here because it uses us. */ + + cpu->cgen_cpu.cpu.h_cwp = x; + + cpu->current_greg_lookup_table = &cpu->greg_lookup_table[x][GET_AG (cpu)][0]; +} + +/* Create a new window. We assume there is room. + + WARNING: The following must always be true: + + CANSAVE + CANRESTORE + OTHERWIN == NWINDOWS - 2 + + We only watch for this during saves. */ + +void +sparc64_save_window (SIM_CPU *current_cpu) +{ + if (GET_CANSAVE (cpu) + GET_CANRESTORE (cpu) + GET_OTHERWIN (cpu) != GET_NWINDOWS (cpu) - 2) + abort (); + + SET_CWP (cpu, ROUND_WIN (GET_CWP (cpu) + 1)); + SET_CANSAVE (cpu, ROUND_WIN (GET_CANSAVE (cpu) - 1)); + SET_CANRESTORE (cpu, ROUND_WIN (GET_CANRESTORE (cpu) + 1)); +} + +/* Pop a window. We assume no traps possible. */ + +void +sparc64_restore_window (SIM_CPU *current_cpu) +{ + SET_CWP (cpu, ROUND_WIN (GET_CWP (cpu) - 1)); + SET_CANSAVE (cpu, ROUND_WIN (GET_CANSAVE (cpu) + 1)); + SET_CANRESTORE (cpu, ROUND_WIN (GET_CANRESTORE (cpu) - 1)); +} + +/* Flush the register windows to memory. + This is necessary, for example, when we want to walk the stack in gdb. + + We use restore_window() and save_window() to traverse the register windows. + This is the cleanest and simplest thing to do. */ + +void +sparc64_flush_windows (SIM_CPU *cpu) +{ + int i,count = GET_CANRESTORE (cpu) + 1; + + /* Save the register windows, changing the current one as we go ... */ + + for (i = 0; i < count; i++) + { + AI sp = GET_INT_REG (cpu, REG_SP) /*+ stack_bias*/; + flush_one_window (cpu, sp, CURRENT_LREGS (cpu), CURRENT_IREGS (cpu)); + if (i + 1 != count) /* don't restore window if there isn't one */ + restore_window (cpu); + } + + /* Restore the window state ... */ + + for (i = 1; i < count; i++) + save_window (cpu); +} + +void +sparc64_flush_one_window (SIM_CPU *current_cpu, AI addr, DI *lregs, DI *iregs) +{ + sim_core_write_buffer (CPU_STATE (cpu), cpu, + sim_core_write_map, + lregs, addr, 8 * sizeof (DI)); + sim_core_write_buffer (CPU_STATE (cpu), cpu, + sim_core_write_map, + iregs, addr + 8 * sizeof (DI), 8 * sizeof (DI)); +} diff --git a/sim/sparc/trap64.h b/sim/sparc/trap64.h new file mode 100644 index 0000000..d51d8f1 --- /dev/null +++ b/sim/sparc/trap64.h @@ -0,0 +1,86 @@ +/* sparc64 trap definitions + Copyright (C) 1999 Cygnus Solutions. */ + +#ifndef TRAP64_H +#define TRAP64_H + +/* D1.2.4 page 107 */ + +typedef enum +{ + TRAP64_POWER_ON_RESET = 1, + TRAP64_WATCHDOG_RESET = 2, + TRAP64_EXTERNALLY_INITIATED_RESET = 3, + TRAP64_SOFTWARE_INITIATED_RESET = 4, + TRAP64_RED_STATE_EXCEPTION = 5, + TRAP64_INSN_ACCESS_EXCEPTION = 8, + TRAP64_INSN_ACCESS_MMU_MISS = 9, + TRAP64_INSN_ACCESS_ERROR = 10, + TRAP64_ILLEGAL_INSN = 16, + TRAP64_PRIVILEDGED_OPCODE = 17, + TRAP64_UNIMPLEMENTED_LDD = 18, + TRAP64_UNIMPLEMENTED_STD = 19, + TRAP64_FP_DISABLED = 32, + TRAP64_FP_EXCEPTION_IEEE_754 = 33, + TRAP64_FP_EXCEPTION_OTHER = 34, + TRAP64_TAG_OVERFLOW = 35, + TRAP64_CLEAN_WINDOW = 36, + TRAP64_DIVISION_BY_ZERO = 40, + TRAP64_INTERNAL_PROCESSOR_ERROR = 41, + TRAP64_DATA_ACCESS_EXCEPTION = 48, + TRAP64_DATA_ACCESS_MMU_MISS = 49, + TRAP64_DATA_ACCESS_ERROR = 50, + TRAP64_DATA_ACCESS_PROTECTION = 51, + TRAP64_MEM_ADDRESS_NOT_ALIGNED = 52, + TRAP64_LDDF_MEM_ADDRESS_NOT_ALIGNED = 53, /* impdep # 109 */ + TRAP64_STDF_MEM_ADDRESS_NOT_ALIGNED = 54, /* impdep # 110 */ + TRAP64_PRIVILEDGED_ACTION = 55, + TRAP64_LDQF_MEM_ADDRESS_NOT_ALIGNED = 56, /* impdep # 111 */ + TRAP64_STQF_MEM_ADDRESS_NOT_ALIGNED = 57, /* impdep # 112 */ + TRAP64_ASYNC_DATA_ERROR = 64, + TRAP64_INTERRUPT_LEVEL_0 = 65, /* n = 1..15 */ + TRAP64_IMPDEP_EXCEPTION_0 = 96, /* n = 0..31 */ + + /* IMPDEP codes used by the simulator in ENVIRONMENT_USER. */ + TRAP64_SIM_UNIMPLEMENTED_OPCODE = 124, + TRAP64_SIM_RESERVED_INSN = 125, + TRAP64_SIM_SPILL = 126, + TRAP64_SIM_FILL = 127, + + TRAP64_SPILL_0_NORMAL = 128, /* n = 0..7 */ + TRAP64_SPILL_0_OTHER = 160, /* n = 0..7 */ + TRAP64_FILL_0_NORMAL = 192, /* n = 0..7 */ + TRAP64_FILL_0_OTHER = 224, /* n = 0..7 */ + TRAP64_INSTRUCTION = 256, /* n = 0..127 */ + TRAP64_BREAKPOINT = 257, /* convention */ + TRAP64_MAX = 0x17f +} TRAP64_TYPE; + +#define MAX_NUM_TRAPS 1024 + +#define TRAP64_TABLE_SIZE (32 * MAX_NUM_TRAPS) /* in bytes */ + +/* We record the fact that the cpu is in error state by setting TL to be + something greater than MAXTL, usually MAXTL+1. */ + +#define ERROR_STATE_P() (GET_TL () > MAXTL) + +#if 0 +fastint trap (trap_type_e); +int trap_priority (trap_type_e); + +fastint reserved (void); +fastint deprecated (void); +fastint not_impl (void); +fastint illegal (void); +fastint priviledged (void); +fastint unimp_fpop (void); +fastint fp_disabled (void); + +/* When running user level programs, we supply all the necessary trap handlers. + These handlers run on the host, not in the emulation environment. */ + +typedef fastint (trap_handler_t) (void); +#endif + +#endif /* TRAP64_H */ |