diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mn10300/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/mn10300/simops.c | 12 |
2 files changed, 11 insertions, 5 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 6731891..a1e0301 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,7 @@ +Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix thinkos in last change to "inc dn". + Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com) * simops.c: "add imm,sp" does not effect the condition codes. diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index c3ecc4e..cebd184 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -1424,16 +1424,18 @@ void OP_F270 () void OP_40 () { int z,n,c,v; - unsigned int value; + unsigned int value, imm, reg1; - value = State.regs[REG_D0 + ((insn & 0xc) >> 2)] + 1; + reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)]; + imm = 1; + value = reg1 + imm; State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value; z = (value == 0); n = (value & 0x80000000); - c = (reg1 < reg2); - v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) - && (reg2 & 0x80000000) != (value & 0x80000000)); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) |