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-rw-r--r--sim/testsuite/d10v-elf/.Sanitize1
-rw-r--r--sim/testsuite/d10v-elf/t-sadd.s38
2 files changed, 39 insertions, 0 deletions
diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize
index 7ab96da..ad4fccc 100644
--- a/sim/testsuite/d10v-elf/.Sanitize
+++ b/sim/testsuite/d10v-elf/.Sanitize
@@ -21,6 +21,7 @@ t-rachi.s
t-rdt.s
t-rep.s
t-rte.s
+t-sadd.s
t-sp.s
t-sub.s
t-sub2w.s
diff --git a/sim/testsuite/d10v-elf/t-sadd.s b/sim/testsuite/d10v-elf/t-sadd.s
new file mode 100644
index 0000000..f3e4ebe
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-sadd.s
@@ -0,0 +1,38 @@
+.include "t-macros.i"
+
+ start
+
+ PSW_BITS = PSW_FX|PSW_ST|PSW_SM
+ loadpsw2 PSW_BITS
+
+ ;; Test normal sadd
+
+ loadacc2 a0 0x00 0x7fff 0xffff
+ loadacc2 a1 0xff 0x8000 0x0000
+ sadd a1, a0
+ checkacc2 1 a0 0x00 0x7fff 0xffff
+ checkacc2 2 a1 0xff 0x8000 0x7fff
+
+ ;; Test overflow
+
+ loadacc2 a0 0x00 0x0000 0x0000
+ loadacc2 a1 0x01 0x8000 0x0000
+ sadd a1, a0
+ checkacc2 3 a0 0x00 0x0000 0x0000
+ checkacc2 4 a1 0x00 0x7fff 0xffff
+
+ loadacc2 a0 0x00 0xffff 0xffff
+ loadacc2 a1 0x00 0xffff 0xffff
+ sadd a1, a0
+ checkacc2 5 a1 0x00 0x7fff 0xffff
+ checkacc2 6 a0 0x00 0xffff 0xffff
+
+ ;; Test underflow
+
+ loadacc2 a0 0x00 0x0000 0x0000
+ loadacc2 a1 0x80 0x8000 0x0000
+ sadd a1, a0
+ checkacc2 7 a0 0x00 0x0000 0x0000
+ checkacc2 8 a1 0xff 0x8000 0x0000
+
+ exit0