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-rw-r--r--sim/testsuite/ChangeLog20
-rw-r--r--sim/testsuite/sim/cris/asm/asr.ms4
-rw-r--r--sim/testsuite/sim/cris/asm/boundr.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/dstep.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/jsr.ms5
-rw-r--r--sim/testsuite/sim/cris/asm/lsr.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/movecr.ms4
-rw-r--r--sim/testsuite/sim/cris/asm/movecrt10.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/movecrt32.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/mover.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/neg.ms36
-rw-r--r--sim/testsuite/sim/cris/asm/nonvcv32.ms167
-rw-r--r--sim/testsuite/sim/cris/asm/op3.ms2
-rw-r--r--sim/testsuite/sim/cris/asm/testutils.inc6
14 files changed, 225 insertions, 31 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 168b05d..eb6ebf3 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,23 @@
+2007-10-22 Edgar E. Iglesias <edgar@axis.com>
+ Hans-Peter Nilsson <hp@axis.com>
+
+ * sim/cris/asm/testutils.inc (test_move_cc): Add missing call to
+ test_cc.
+ * sim/cris/asm/asr.ms: Correct expected condition code flags.
+ * sim/cris/asm/boundr.ms: Ditto.
+ * sim/cris/asm/dstep.ms: Ditto.
+ * sim/cris/asm/lsr.ms: Ditto.
+ * sim/cris/asm/movecr.ms: Ditto.
+ * sim/cris/asm/mover.ms: Ditto.
+ * sim/cris/asm/neg.ms: Ditto. Use test_cc, not test_move_cc.
+ * sim/cris/asm/op3.ms: Check the condition code flags after the insn
+ under test.
+ * sim/cris/asm/movecrt10.ms: Update expected number of simulated
+ cycles.
+ * sim/cris/asm/movecrt32.ms: Ditto.
+ * sim/cris/asm/jsr.ms: Don't use local label 8.
+ * sim/cris/asm/nonvcv32.ms: New test.
+
2007-10-11 Jesper Nilsson <jesper.nilsson@axis.com>
* sim/cris/c/freopen2.c: Added testcase.
diff --git a/sim/testsuite/sim/cris/asm/asr.ms b/sim/testsuite/sim/cris/asm/asr.ms
index d24ad4a..066bc73 100644
--- a/sim/testsuite/sim/cris/asm/asr.ms
+++ b/sim/testsuite/sim/cris/asm/asr.ms
@@ -205,13 +205,13 @@
move.d 0x5a67f19f,r3
moveq 12,r4
asr.b r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
dumpr3 ; 5a67f1ff
move.d 0x5a67f19f,r3
moveq 4,r4
asr.b r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
dumpr3 ; 5a67f1f9
move.d 0x5a67f19f,r3
diff --git a/sim/testsuite/sim/cris/asm/boundr.ms b/sim/testsuite/sim/cris/asm/boundr.ms
index bc6a90d..053c4ae 100644
--- a/sim/testsuite/sim/cris/asm/boundr.ms
+++ b/sim/testsuite/sim/cris/asm/boundr.ms
@@ -24,7 +24,7 @@
moveq -1,r4
move.d r4,r3
bound.d r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
dumpr3 ; ffffffff
move.d 0x5432f789,r4
diff --git a/sim/testsuite/sim/cris/asm/dstep.ms b/sim/testsuite/sim/cris/asm/dstep.ms
index 25beda0..8b32240 100644
--- a/sim/testsuite/sim/cris/asm/dstep.ms
+++ b/sim/testsuite/sim/cris/asm/dstep.ms
@@ -30,7 +30,7 @@
move.d 0x5432f789,r4
move.d 0x78134452,r3
dstep r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
dumpr3 ; 9bf3911b
move.d 0xffff,r3
diff --git a/sim/testsuite/sim/cris/asm/jsr.ms b/sim/testsuite/sim/cris/asm/jsr.ms
index 95dd7c5..c684fd3 100644
--- a/sim/testsuite/sim/cris/asm/jsr.ms
+++ b/sim/testsuite/sim/cris/asm/jsr.ms
@@ -41,7 +41,8 @@ x:
nop
quit
-8:
+; Can't use local label 8 or 9, as they're used by test_move_cc.
+y:
move srp,r3
sub.d 7b,r3
dumpr3
@@ -78,7 +79,7 @@ x:
move srp,r3
sub.d 7b,r3
dumpr3
- jump 8b
+ jump y
.if ..asm.arch.cris.v32
nop
.endif
diff --git a/sim/testsuite/sim/cris/asm/lsr.ms b/sim/testsuite/sim/cris/asm/lsr.ms
index e4991c6..a7c5d3d 100644
--- a/sim/testsuite/sim/cris/asm/lsr.ms
+++ b/sim/testsuite/sim/cris/asm/lsr.ms
@@ -127,7 +127,7 @@
moveq -1,r3
moveq 31,r4
lsr.w r4,r3
- test_move_cc 0 0 0 0
+ test_move_cc 0 1 0 0
dumpr3 ; ffff0000
moveq -1,r3
diff --git a/sim/testsuite/sim/cris/asm/movecr.ms b/sim/testsuite/sim/cris/asm/movecr.ms
index a408747..01bf7f0 100644
--- a/sim/testsuite/sim/cris/asm/movecr.ms
+++ b/sim/testsuite/sim/cris/asm/movecr.ms
@@ -13,12 +13,12 @@
moveq 0,r3
move.b 0x94,r3
- test_move_cc 0 0 0 0
+ test_move_cc 1 0 0 0
dumpr3
moveq -1,r3
move.w 0x4321,r3
- test_move_cc 1 0 0 0
+ test_move_cc 0 0 0 0
dumpr3
moveq 0,r3
diff --git a/sim/testsuite/sim/cris/asm/movecrt10.ms b/sim/testsuite/sim/cris/asm/movecrt10.ms
index c9e3704..d965bbc 100644
--- a/sim/testsuite/sim/cris/asm/movecrt10.ms
+++ b/sim/testsuite/sim/cris/asm/movecrt10.ms
@@ -1,6 +1,6 @@
#mach: crisv10
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
-#output: Basic clock cycles, total @: 22\n
+#output: Basic clock cycles, total @: 82\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
diff --git a/sim/testsuite/sim/cris/asm/movecrt32.ms b/sim/testsuite/sim/cris/asm/movecrt32.ms
index f0aba7f..75833a4 100644
--- a/sim/testsuite/sim/cris/asm/movecrt32.ms
+++ b/sim/testsuite/sim/cris/asm/movecrt32.ms
@@ -1,6 +1,6 @@
#mach: crisv32
#output: ffffff42\n94\nffff4321\n9234\n76543210\n76540000\n
-#output: Basic clock cycles, total @: 22\n
+#output: Basic clock cycles, total @: 82\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
diff --git a/sim/testsuite/sim/cris/asm/mover.ms b/sim/testsuite/sim/cris/asm/mover.ms
index 57b1d88..41a6474 100644
--- a/sim/testsuite/sim/cris/asm/mover.ms
+++ b/sim/testsuite/sim/cris/asm/mover.ms
@@ -8,7 +8,7 @@
moveq -30,r3
moveq 5,r4
move.b r4,r3
- test_move_cc 1 0 0 0
+ test_move_cc 0 0 0 0
dumpr3
move.w r4,r3
diff --git a/sim/testsuite/sim/cris/asm/neg.ms b/sim/testsuite/sim/cris/asm/neg.ms
index f2681ea..0a922a6 100644
--- a/sim/testsuite/sim/cris/asm/neg.ms
+++ b/sim/testsuite/sim/cris/asm/neg.ms
@@ -6,97 +6,97 @@
moveq 0,r3
moveq 1,r4
neg.d r4,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ffffffff
moveq 1,r3
moveq 0,r4
neg.d r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ffffffff
moveq 0,r3
neg.d r3,r3
- test_move_cc 0 0 1 0
+ test_cc 0 1 0 0
dumpr3 ; 0
move.d 0x80000000,r3
neg.d r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 1 1
dumpr3 ; 80000000
moveq -1,r3
neg.d r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
dumpr3 ; 1
move.d 0x456789ab,r3
neg.d r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ba987655
moveq 0,r3
moveq 1,r4
neg.w r4,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ffff
moveq 1,r3
moveq 0,r4
neg.w r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ffff
moveq 0,r3
neg.w r3,r3
- test_move_cc 0 0 1 0
+ test_cc 0 1 0 0
dumpr3 ; 0
move.d 0x89ab8000,r3
neg.w r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 1 1
dumpr3 ; 89ab8000
moveq -1,r3
neg.w r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
dumpr3 ; ffff0001
move.d 0x456789ab,r3
neg.w r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
dumpr3 ; 45677655
moveq 0,r3
moveq 1,r4
neg.b r4,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ff
moveq 1,r3
moveq 0,r4
neg.b r3,r3
- test_move_cc 1 0 0 0
+ test_cc 1 0 0 1
dumpr3 ; ff
moveq 0,r3
neg.b r3,r3
- test_move_cc 0 0 1 0
+ test_cc 0 1 0 0
dumpr3 ; 0
move.d 0x89abae80,r3
neg.b r3,r3
- test_move_cc 0 0 1 0
+ test_cc 1 0 1 1
dumpr3 ; 89abae80
moveq -1,r3
neg.b r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
dumpr3 ; ffffff01
move.d 0x456789ab,r3
neg.b r3,r3
- test_move_cc 0 0 0 0
+ test_cc 0 0 0 1
dumpr3 ; 45678955
quit
diff --git a/sim/testsuite/sim/cris/asm/nonvcv32.ms b/sim/testsuite/sim/cris/asm/nonvcv32.ms
new file mode 100644
index 0000000..7e6ee5b
--- /dev/null
+++ b/sim/testsuite/sim/cris/asm/nonvcv32.ms
@@ -0,0 +1,167 @@
+# mach: crisv32
+
+ .include "testutils.inc"
+
+; Check for various non-arithmetic insns that C and V are not affected
+; on v32 (where they were on v10), as the generic tests don't cover
+; that; they are cleared before testing.
+
+; First, a macro testing that VC are unaffected, not counting previous
+; register contents.
+ .macro nonvc0 insn op
+ move.d $r0,$r3
+ setf vc
+ .ifnc \insn,swapnwbr
+ \insn \op,$r3
+ .else
+ \insn $r3
+ .endif
+ bcc 9f
+ nop
+ bvc 9f
+ nop
+ move.d $r0,$r3
+ clearf vc
+ .ifnc \insn,swapnwbr
+ \insn \op,$r3
+ .else
+ \insn $r3
+ .endif
+ bcs 9f
+ nop
+ bvc 8f
+ nop
+9:
+ fail
+8:
+ .endm
+
+; Use the above, but initialize the non-parameter operand to a value.
+ .macro nonvc1 insn val op
+ move.d \val,$r0
+ nonvc0 \insn,\op
+ .endm
+
+; Use the above, iterating over various values.
+ .macro nonvc2 insn op
+ .irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
+ nonvc1 \insn,\p,\op
+ nonvc1 \insn,-\p,\op
+ .endr
+ .endm
+
+ .macro nonvc2q insn op min=-63 max=63
+ .if \op >= \min &&&& \op <= \max
+ nonvc2 \insn,\op
+ .endif
+ .endm
+
+; The above, for each .b .w .d insn variant.
+ .macro nonvcbwd insn op
+ .irp s,.b,.w,.d
+ nonvc2 \insn\s,\op
+ .endr
+ .endm
+
+; For various insns with register, dword constant and memory operands.
+ .macro nonvcitermcd op=[$r4]
+ nonvc2 and.d,\op
+ nonvc2 move.d,\op
+ nonvc2 or.d,\op
+ .endm
+
+; Similar, for various insns with register, word constant and memory operands.
+ .macro nonvcitermcw op=[$r4]
+ nonvcitermcd \op
+ nonvc2 and.w,\op
+ nonvc2 move.w,\op
+ nonvc2 or.w,\op
+ nonvc2 movs.w,\op
+ nonvc2 movu.w,\op
+ .endm
+
+; Similar, for various insns with register, byte constant and memory operands.
+ .macro nonvcitermcb op=[$r4]
+ nonvcitermcw \op
+ nonvc2 and.b,\op
+ nonvc2 move.b,\op
+ nonvc2 or.b,\op
+ nonvc2 movs.b,\op
+ nonvc2 movu.b,\op
+ .endm
+
+; Similar, for insns with quick constant operands.
+ .macro nonvciterq op
+ nonvcitermcb \op
+ nonvc2 bound.b,\op
+ nonvc2q andq,\op,min=-32,max=31
+ nonvc2q asrq,\op,min=0,max=31
+ nonvc2q lsrq,\op,min=0,max=31
+ nonvc2q orq,\op,min=-32,max=31
+ nonvc2q moveq,\op,min=-32,max=31
+ .endm
+
+; Similar, for insns with register operands.
+ .macro nonvciterr op
+ nonvcitermcb \op
+ nonvcbwd bound,\op
+ nonvc2 abs,\op
+ nonvcbwd asr,\op
+ nonvc2 dstep,\op
+ nonvcbwd lsr,\op
+ nonvcbwd lsl,\op
+ nonvc2 lz,\op
+ nonvc2 swapnwbr
+ nonvc2 xor,\op
+ .endm
+
+; Test all applicable constant, register and memory variants of a value.
+ .macro tst op
+; Constants
+ .if (\op <= 31 &&&& \op >= -32)
+ nonvciterq \op
+ .elseif (\op <= 255 &&&& \op >= -128)
+ nonvcitermcb \op
+ nonvcbwd bound,\op
+ .elseif (\op <= 65535 &&&& \op >= -32767)
+ nonvcitermcw \op
+ nonvc2 bound.w,\op
+ nonvc2 bound.d,\op
+ .else
+ nonvcitermcd \op
+ nonvc2 bound.d,\op
+ .endif
+; Registers
+ move.d \op,$r4
+ nonvciterr $r4
+; Memory
+ nonvcitermcb [$r5]
+ addq 4,$r5
+ .section .rodata
+ .dword \op
+ .previous
+ .endm
+
+; As above but negation too.
+ .macro tstpm op
+ tst \op
+ tst -\op
+ .endm
+
+
+; Set up for the actual test.
+
+ start
+ move.d c0,$r5
+
+ .section .rodata
+c0:
+ .previous
+
+; Finally, test.
+
+ .irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
+ tstpm \x
+ .endr
+
+ pass
diff --git a/sim/testsuite/sim/cris/asm/op3.ms b/sim/testsuite/sim/cris/asm/op3.ms
index 44fa83a..05e974c 100644
--- a/sim/testsuite/sim/cris/asm/op3.ms
+++ b/sim/testsuite/sim/cris/asm/op3.ms
@@ -43,8 +43,8 @@ x:
moveq 0,r5
bdap 2,r10
- test_move_cc 0 0 0 0
movu.b [r3],r5
+ test_move_cc 0 0 0 0
dumpr3 ; aa
move.d 0x42435567,r8
diff --git a/sim/testsuite/sim/cris/asm/testutils.inc b/sim/testsuite/sim/cris/asm/testutils.inc
index 457d581..962f4fc 100644
--- a/sim/testsuite/sim/cris/asm/testutils.inc
+++ b/sim/testsuite/sim/cris/asm/testutils.inc
@@ -277,7 +277,13 @@ _start:
.macro test_move_cc N Z V C
.if ..asm.arch.cris.v32
+ ; V and C aren't affected on v32, so to re-use the test-cases,
+ ; we fake them cleared. There's a separate test, nonvcv32.ms
+ ; covering this omission.
clearf vc
+ test_cc \N \Z 0 0
+ .else
+ test_cc \N \Z \V \C
.endif
.endm
generated by cgit v1.1 at 2024-12-04 10:15:40 +0000