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-rw-r--r--sim/testsuite/d10v-elf/ChangeLog5
-rw-r--r--sim/testsuite/d10v-elf/Makefile.in2
-rw-r--r--sim/testsuite/d10v-elf/t-sp.s17
-rw-r--r--sim/testsuite/d10v-elf/t-trap.s5
4 files changed, 29 insertions, 0 deletions
diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index b040b34..28530c0 100644
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,3 +1,8 @@
+Fri Feb 13 16:21:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * t-sp.s: New test.
+ * Makefile.in (TESTS): Update.
+
Wed Feb 11 17:58:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* t-macros.i: Update trap calls, func in r4, args in
diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in
index 07d22d2..92dc121 100644
--- a/sim/testsuite/d10v-elf/Makefile.in
+++ b/sim/testsuite/d10v-elf/Makefile.in
@@ -48,6 +48,8 @@ TESTS = \
t-rac.ok \
t-rachi.ok \
t-rep.ok \
+ t-rte.ok \
+ t-sp.ok \
t-sub2w.ok \
t-sub.ok \
t-subi.ok \
diff --git a/sim/testsuite/d10v-elf/t-sp.s b/sim/testsuite/d10v-elf/t-sp.s
new file mode 100644
index 0000000..84f9ad4
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-sp.s
@@ -0,0 +1,17 @@
+.include "t-macros.i"
+
+ start
+
+;;; Read/Write values to SPU/SPI
+
+ loadpsw2 0
+ ldi sp, 0xdead
+ loadpsw2 PSW_SM
+ ldi sp, 0xbeef
+
+ loadpsw2 0
+ check 1 sp 0xdead
+ loadpsw2 PSW_SM
+ check 2 sp 0xbeef
+
+ exit0
diff --git a/sim/testsuite/d10v-elf/t-trap.s b/sim/testsuite/d10v-elf/t-trap.s
new file mode 100644
index 0000000..6ac4ae0
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-trap.s
@@ -0,0 +1,5 @@
+.include "t-macros.i"
+
+ start
+
+ exit47