diff options
Diffstat (limited to 'sim')
119 files changed, 7466 insertions, 6627 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index c73709f..7c44a9b 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,24 +1,18 @@ +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * configure.in: Add support for MCore target. + * configure: Regenerate. + 1999-03-14 Stan Shebs <shebs@andros.cygnus.com> * Makefile.in (FLAGS_TO_PASS, TARGET_FLAGS_TO_PASS): Remove RUNTEST instead of commenting out, fixes portability problem. -1999-02-10 Doug Evans <devans@casey.cygnus.com> - - * configure.in (sparc*): Configure sparc subdir if --with-cgen or - --with-cgen-sim. - * configure: Rebuild. - 1999-02-08 Nick Clifton <nickc@cygnus.com> * configure.in: Add support for StrongARM target. * configure: Regenerate. -1999-02-02 Doug Evans <devans@casey.cygnus.com> - - * configure.in (sparc*): Configure sparc subdir if --with-cgen. - * configure: Rebuild. - 1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) * configure.in: Require autoconf 2.12.1 or higher. @@ -40,8 +34,8 @@ Fri Sep 25 10:12:19 1998 Christopher Faylor <cgf@cygnus.com> Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com> - * Makefile.in: Take RUNTEST out of FLAG_TO_PASS - so that make check can be invoked recursively. + * Makefile.in: Take RUNTEST out of FLAGS_TO_PASS so that make + check can be invoked recursively. Wed Apr 29 12:38:53 1998 Mark Alexander <marka@cygnus.com> diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index 4149366..9f6adf4 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,25 @@ +1999-04-06 Keith Seitz <keiths@cygnus.com> + + * wrapper.c (stop_simulator): New global. + (sim_stop): Set sim state to STOP and set + stop_simulator. + (sim_resume): Reset stop_simulator. + (sim_stop_reason): If stop_simulator is set, tell gdb + that the we took SIGINT. + * armemu.c (ARMul_Emulate26): Don't loop forever. Stop if + stop_simulator is set. + +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * armemu.c (ARMul_Emulate26): If NEED_UI_LOOP_HOOK, call ui_loop_hook + whenever the counter expires. + * Makefile.in (SIM_EXTRA_CFLAGS): Include define NEED_UI_LOOP_HOOK. + +1999-03-24 Nick Clifton <nickc@cygnus.com> + + * armemu.c (ARMul_Emulate26): Handle new breakpoint value. + * thumbemu.c (ARMul_ThumbDecode): Handle new breakpoint value. + Mon Sep 14 09:00:05 1998 Nick Clifton <nickc@cygnus.com> * wrapper.c (sim_open): Set endianness according to BFD or command diff --git a/sim/arm/Makefile.in b/sim/arm/Makefile.in index b6ae2af..e2f2b3c 100644 --- a/sim/arm/Makefile.in +++ b/sim/arm/Makefile.in @@ -18,7 +18,7 @@ ## COMMON_PRE_CONFIG_FRAG -SIM_EXTRA_CFLAGS = -DMODET +SIM_EXTRA_CFLAGS = -DMODET -DNEED_UI_LOOP_HOOK SIM_OBJS = armcopro.o armemu26.o armemu32.o arminit.o armos.o armsupp.o \ armvirt.o bag.o thumbemu.o wrapper.o sim-load.o diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 171f1c8..36b7bba 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -18,6 +18,7 @@ #include "armdefs.h" #include "armemu.h" +#include "armos.h" static ARMword GetDPRegRHS(ARMul_State *state, ARMword instr) ; static ARMword GetDPSRegRHS(ARMul_State *state, ARMword instr) ; @@ -43,6 +44,19 @@ static unsigned MultiplyAdd64(ARMul_State *state, ARMword instr,int signextend,i #define LDEFAULT (0) /* default : do nothing */ #define LSCC (1) /* set condition codes on result */ +#ifdef NEED_UI_LOOP_HOOK +/* How often to run the ui_loop update, when in use */ +#define UI_LOOP_POLL_INTERVAL 0x32000 + +/* Counter for the ui_loop_hook update */ +static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + +/* Actual hook to call to run through gdb's gui event loop */ +extern int (*ui_loop_hook) (int); +#endif /* NEED_UI_LOOP_HOOK */ + +extern int stop_simulator; + /***************************************************************************\ * short-hand macros for LDR/STR * \***************************************************************************/ @@ -2166,10 +2180,20 @@ mainswitch: break ; case 0x7f : /* Load Byte, WriteBack, Pre Inc, Reg */ - if (BIT(4)) { - ARMul_UndefInstr(state,instr) ; - break ; - } + if (BIT(4)) + { + /* Check for the special breakpoint opcode. + This value should correspond to the value defined + as ARM_BE_BREAKPOINT in gdb/arm-tdep.c. */ + if (BITS (0,19) == 0xfdefe) + { + if (! ARMul_OSHandleSWI (state, SWI_Breakpoint)) + ARMul_Abort (state, ARMul_SWIV); + } + else + ARMul_UndefInstr(state,instr) ; + break ; + } UNDEF_LSRBaseEQOffWb ; UNDEF_LSRBaseEQDestWb ; UNDEF_LSRPCBaseWb ; @@ -2549,11 +2573,19 @@ mainswitch: donext: #endif +#ifdef NEED_UI_LOOP_HOOK + if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) + { + ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + ui_loop_hook (0); + } +#endif /* NEED_UI_LOOP_HOOK */ + if (state->Emulate == ONCE) state->Emulate = STOP; else if (state->Emulate != RUN) break; - } while (1) ; /* do loop */ + } while (!stop_simulator) ; /* do loop */ state->decoded = decoded ; state->loaded = loaded ; diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c index eaf6e0c..c610b97 100644 --- a/sim/arm/thumbemu.c +++ b/sim/arm/thumbemu.c @@ -29,6 +29,7 @@ existing ARM simulator. */ #include "armdefs.h" #include "armemu.h" +#include "armos.h" /* Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field, with the following Thumb instruction @@ -356,6 +357,9 @@ ARMul_ThumbDecode (state,pc,tinstr,ainstr) /* Breakpoint must be handled specially. */ if ((tinstr & 0x00FF) == 0x18) *ainstr |= ((tinstr & 0x00FF) << 16); + /* New breakpoint value. See gdb/arm-tdep.c */ + else if ((tinstr & 0x00FF) == 0xFE) + * ainstr |= SWI_Breakpoint; else *ainstr |= (tinstr & 0x00FF); } diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index 4038004..7d725b8 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -50,6 +50,8 @@ static int verbosity; /* Non-zero to set big endian mode. */ static int big_endian; +int stop_simulator; + static void init () { @@ -154,7 +156,9 @@ int sim_stop (sd) SIM_DESC sd; { - return 0; + state->Emulate = STOP; + stop_simulator = 1; + return 1; } void @@ -163,6 +167,7 @@ sim_resume (sd, step, siggnal) int step, siggnal; { state->EndCondition = 0; + stop_simulator = 0; if (step) { @@ -435,7 +440,12 @@ sim_stop_reason (sd, reason, sigrc) enum sim_stop *reason; int *sigrc; { - if (state->EndCondition == 0) + if (stop_simulator) + { + *reason = sim_stopped; + *sigrc = SIGINT; + } + else if (state->EndCondition == 0) { *reason = sim_exited; *sigrc = state->Reg[0] & 255; diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index bde0710..ed3c601 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,56 @@ +Fri Apr 16 16:43:22 1999 Doug Evans <devans@charmed.cygnus.com> + + * sim-core.c (device_error,device_io_read_buffer, + device_io_write_buffer): Delete decls. + * sim-core.h: Put them here. + + * sim-core.c (sim_core_read_buffer): Pass sd to device_io_read_buffer. + (sim_core_write_buffer): Pass sd to device_io_write_buffer. + * sim-n-core.h (sim_core_read_aligned_N): Ditto. + (sim_core_write_aligned_N): Ditto. + +1999-04-14 Stephane Carrez <stcarrez@worldnet.fr> + + * sim-memopt.c (sim_memory_uninstall): Don't look into + free()d memory. + +1999-04-14 Doug Evans <devans@casey.cygnus.com> + + * cgen-utils.scm (virtual_insn_entries): Update attribute definition. + +1999-04-13 Doug Evans <devans@casey.cygnus.com> + + * sim-core.c (sim_core_read_buffer): Handle NULL cpu when WITH_DEVICES. + (sim_core_write_buffer): Ditto. + +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * sim-io.c (sim_io_poll_quit): Only call the poll_quit callback + after the interval counter has expired. + (POLL_QUIT_INTERVAL): Define. Used to tweak the frequency of + poll_quit callbacks. May be overridden by Makefile. + (poll_quit_counter): New global. + * sim-events.c: Remove all mentions of ui_loop_hook. The + host callback "poll_quit" will serve the purpose. + * run.c: Add definition of ui_loop_hook when NEED_UI_LOOP_HOOK + is defined. + * nrun.c: Remove declaration of ui_loop_hook. + +Wed Mar 31 18:55:41 1999 Doug Evans <devans@canuck.cygnus.com> + + * cgen-run.c (sim_resume): Don't tell main loop to run "forever" + if being used by gdb. + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * cgen-types.h (XF,TF): Tweak. + * cgen-ops.h: Redo inline support. Delete DI_FN_SUPPORT, + in cgen-types.h. + (SUBWORD*,JOIN*): Define. + * cgen-trace.c (sim_cgen_disassemble_insn): Update, base_insn_bitsize + moved into cpu descriptor. + * sim-model.h (MACH): New member `num'. + 1999-02-09 Doug Evans <devans@casey.cygnus.com> * Make-common.in (CGEN_READ_SCM): Renamed from CGEN_MAIN_SCM. diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h index 1ec0e6c..6b89859 100644 --- a/sim/common/cgen-ops.h +++ b/sim/common/cgen-ops.h @@ -1,5 +1,5 @@ /* Semantics ops support for CGEN-based simulators. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of the GNU Simulators. @@ -23,6 +23,13 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef CGEN_SEM_OPS_H #define CGEN_SEM_OPS_H +#if defined (__GNUC__) && ! defined (SEMOPS_DEFINE_INLINE) +#define SEMOPS_DEFINE_INLINE +#define SEMOPS_INLINE extern inline +#else +#define SEMOPS_INLINE +#endif + /* Semantic operations. At one point this file was machine generated. Maybe it will be again. */ @@ -357,6 +364,7 @@ extern DI EXTSIDI PARAMS ((SI)); #else #define EXTSIDI(x) ((DI) (SI) (x)) #endif + #if defined (SF_FN_SUPPORT) || defined (DF_FN_SUPPORT) extern DF EXTSFDF PARAMS ((SF)); #else @@ -387,6 +395,7 @@ extern TF EXTXFTF PARAMS ((XF)); #else #define EXTXFTF(x) ((TF) (XF) (x)) #endif + #define ZEXTBIQI(x) ((QI) (BI) (x)) #define ZEXTBIHI(x) ((HI) (BI) (x)) #define ZEXTBISI(x) ((SI) (BI) (x)) @@ -413,6 +422,7 @@ extern DI ZEXTSIDI PARAMS ((SI)); #else #define ZEXTSIDI(x) ((DI) (USI) (x)) #endif + #define TRUNCQIBI(x) ((BI) (QI) (x)) #define TRUNCHIBI(x) ((BI) (HI) (x)) #define TRUNCHIQI(x) ((QI) (HI) (x)) @@ -439,6 +449,7 @@ extern SI TRUNCDISI PARAMS ((DI)); #else #define TRUNCDISI(x) ((SI) (DI) (x)) #endif + #if defined (DF_FN_SUPPORT) || defined (SF_FN_SUPPORT) extern SF TRUNCDFSF PARAMS ((DF)); #else @@ -469,6 +480,7 @@ extern XF TRUNCTFXF PARAMS ((TF)); #else #define TRUNCTFXF(x) ((XF) (TF) (x)) #endif + #if defined (SF_FN_SUPPORT) extern SF FLOATQISF PARAMS ((QI)); #else @@ -549,6 +561,7 @@ extern TF FLOATDITF PARAMS ((DI)); #else #define FLOATDITF(x) ((TF) (DI) (x)) #endif + #if defined (SF_FN_SUPPORT) extern SF UFLOATQISF PARAMS ((QI)); #else @@ -629,6 +642,7 @@ extern TF UFLOATDITF PARAMS ((DI)); #else #define UFLOATDITF(x) ((TF) (UDI) (x)) #endif + #if defined (SF_FN_SUPPORT) extern BI FIXSFBI PARAMS ((SF)); #else @@ -729,6 +743,7 @@ extern DI FIXTFDI PARAMS ((TF)); #else #define FIXTFDI(x) ((DI) (TF) (x)) #endif + #if defined (SF_FN_SUPPORT) extern QI UFIXSFQI PARAMS ((SF)); #else @@ -810,15 +825,118 @@ extern DI UFIXTFDI PARAMS ((TF)); #define UFIXTFDI(x) ((UDI) (TF) (x)) #endif -/* Semantic support utilities. */ - -#ifdef __GNUC__ +/* Composing/decomposing the various types. */ #ifdef SEMOPS_DEFINE_INLINE -#define SEMOPS_INLINE + +SEMOPS_INLINE SF +SUBWORDSISF (SIM_CPU *cpu, SI in) +{ + union { SI in; SF out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE SI +SUBWORDSFSI (SIM_CPU *cpu, SF in) +{ + union { SF in; SI out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE SI +SUBWORDDISI (SIM_CPU *cpu, DI in, int word) +{ + /* ??? endianness issues undecided */ + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + { + if (word == 0) + return (UDI) in >> 32; + else + return in; + } + else + { + if (word == 1) + return (UDI) in >> 32; + else + return in; + } +} + +SEMOPS_INLINE SI +SUBWORDDFSI (SIM_CPU *cpu, DF in, int word) +{ + /* ??? endianness issues undecided */ + union { DF in; SI out[2]; } x; + x.in = in; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + return x.out[word]; + else + return x.out[!word]; +} + +SEMOPS_INLINE SI +SUBWORDTFSI (SIM_CPU *cpu, TF in, int word) +{ + /* ??? endianness issues undecided */ + union { TF in; SI out[4]; } x; + x.in = in; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + return x.out[word]; + else + return x.out[word ^ 3]; +} + +SEMOPS_INLINE DI +JOINSIDI (SIM_CPU *cpu, SI x0, SI x1) +{ + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + return MAKEDI (x0, x1); + else + return MAKEDI (x1, x0); +} + +SEMOPS_INLINE DF +JOINSIDF (SIM_CPU *cpu, SI x0, SI x1) +{ + union { SI in[2]; DF out; } x; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + x.in[0] = x0, x.in[1] = x1; + else + x.in[1] = x0, x.in[0] = x1; + return x.out; +} + +SEMOPS_INLINE TF +JOINSITF (SIM_CPU *cpu, SI x0, SI x1, SI x2, SI x3) +{ + union { SI in[4]; TF out; } x; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + x.in[0] = x0, x.in[1] = x1, x.in[2] = x2, x.in[3] = x3; + else + x.in[3] = x0, x.in[2] = x1, x.in[1] = x2, x.in[0] = x3; + return x.out; +} + #else -#define SEMOPS_INLINE extern inline -#endif + +SF SUBWORDSISF (SIM_CPU *, SI); +SI SUBWORDSFSI (SIM_CPU *, SF); +SI SUBWORDDISI (SIM_CPU *, DI, int); +SI SUBWORDDFSI (SIM_CPU *, DF, int); +SI SUBWORDTFSI (SIM_CPU *, TF, int); + +DI JOINSIDI (SIM_CPU *, SI, SI); +DF JOINSIDF (SIM_CPU *, SI, SI); +TF JOINSITF (SIM_CPU *, SI, SI, SI, SI); + +#endif /* SUBWORD,JOIN */ + +/* Semantic support utilities. */ + +#ifdef SEMOPS_DEFINE_INLINE SEMOPS_INLINE SI ADDCSI (SI a, SI b, BI c) @@ -877,21 +995,5 @@ UBI SUBCFSI (SI, SI, BI); UBI SUBOFSI (SI, SI, BI); #endif - -/* DI mode support if "long long" doesn't exist. - At one point CGEN supported K&R C compilers, and ANSI C compilers without - "long long". One can argue the various merits of keeping this in or - throwing it out. I went to the trouble of adding it so for the time being - I'm leaving it in. */ - -#ifdef DI_FN_SUPPORT - -DI make_struct_di (SI, SI); -/* FIXME: needed? */ -DI CONVHIDI (HI); -DI CONVSIDI (SI); -SI CONVDISI (DI); - -#endif /* DI_FN_SUPPORT */ #endif /* CGEN_SEM_OPS_H */ diff --git a/sim/common/cgen-run.c b/sim/common/cgen-run.c index 07ee191..031bc1c 100644 --- a/sim/common/cgen-run.c +++ b/sim/common/cgen-run.c @@ -93,9 +93,13 @@ sim_resume (SIM_DESC sd, int step, int siggnal) way to identify this case. */ int max_insns = (step ? 1 - : (nr_cpus == 1 /*&& wip:no-events*/) + : (nr_cpus == 1 + /*&& wip:no-events*/ + /* Don't do this if running under gdb, need to + poll ui for events. */ + && STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE) ? 0 - : 4); /*FIXME: magic number*/ + : 8); /*FIXME: magic number*/ int fast_p = STATE_RUN_FAST_P (sd); sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus); diff --git a/sim/common/cgen-trace.c b/sim/common/cgen-trace.c index 9b7d1fa..db852d5 100644 --- a/sim/common/cgen-trace.c +++ b/sim/common/cgen-trace.c @@ -380,12 +380,12 @@ sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc, insn_length); - switch (min (CGEN_BASE_INSN_SIZE, insn_length)) + switch (min (cd->base_insn_bitsize, insn_bit_length)) { case 0 : return; /* fake insn, typically "compile" (aka "invalid") */ - case 1 : insn_value = insn_buf.bytes[0]; break; - case 2 : insn_value = T2H_2 (insn_buf.shorts[0]); break; - case 4 : insn_value = T2H_4 (insn_buf.words[0]); break; + case 8 : insn_value = insn_buf.bytes[0]; break; + case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break; + case 32 : insn_value = T2H_4 (insn_buf.words[0]); break; default: abort (); } diff --git a/sim/common/cgen-types.h b/sim/common/cgen-types.h index e57e601..28c7205 100644 --- a/sim/common/cgen-types.h +++ b/sim/common/cgen-types.h @@ -100,10 +100,10 @@ extern DI make_struct_di (SI, SI); /* FIXME: Need to provide libraries if these aren't appropriate for target, or user's needs. */ -typedef float SF; -typedef double DF; -typedef double XF; /* FIXME: configure, provide library */ -typedef double TF; /* FIXME: configure, provide library */ +typedef float SF; /* FIXME: struct */ +typedef double DF; /* FIXME: struct */ +typedef struct { SI parts[3]; } XF; /* FIXME: configure, provide library */ +typedef struct { SI parts[4]; } TF; /* FIXME: configure, provide library */ /* These are used to record extracted raw data from an instruction, among other things. It must be a host data type, and not a target one. */ diff --git a/sim/common/cgen-utils.c b/sim/common/cgen-utils.c index 2faff5c..b1c9f02 100644 --- a/sim/common/cgen-utils.c +++ b/sim/common/cgen-utils.c @@ -59,28 +59,22 @@ const char *mode_names[] = { static const CGEN_IBASE virtual_insn_entries[] = { { - VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0, - { CGEN_INSN_NBOOL_ATTRS, V, { 0 } } + VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0, { V, { 0 } } }, { - VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0, - { CGEN_INSN_NBOOL_ATTRS, V, { 0 } } + VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0, { V, { 0 } } }, { - VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0, - { CGEN_INSN_NBOOL_ATTRS, V, { 0 } } + VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0, { V, { 0 } } }, { - VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0, - { CGEN_INSN_NBOOL_ATTRS, V, { 0 } } + VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0, { V, { 0 } } }, { - VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0, - { CGEN_INSN_NBOOL_ATTRS, V, { 0 } } + VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0, { V, { 0 } } }, { - VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0, - { CGEN_INSN_NBOOL_ATTRS, V, { 0 } } + VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0, { V, { 0 } } } }; diff --git a/sim/common/nrun.c b/sim/common/nrun.c index 42be33e..2f13b1f 100644 --- a/sim/common/nrun.c +++ b/sim/common/nrun.c @@ -206,9 +206,3 @@ usage () fprintf (stderr, "Run `%s --help' for full list of options.\n", myname); exit (1); } - - -#ifdef __CYGWIN32__ -/* no-op GUI update hook for standalone sim */ -void (*ui_loop_hook) PARAMS ((int)) = NULL; -#endif diff --git a/sim/common/run.c b/sim/common/run.c index 2a701bc..72d7509 100644 --- a/sim/common/run.c +++ b/sim/common/run.c @@ -56,12 +56,16 @@ extern host_callback default_callback; static char *myname; - /* NOTE: sim_size() and sim_trace() are going away */ extern int sim_trace PARAMS ((SIM_DESC sd)); extern int getopt (); +#ifdef NEED_UI_LOOP_HOOK +/* Gdb foolery. This is only needed for gdb using a gui. */ +int (*ui_loop_hook) PARAMS ((int signo)); +#endif + static SIM_DESC sd; static RETSIGTYPE diff --git a/sim/common/sim-core.c b/sim/common/sim-core.c index 36627a2..f7579c4 100644 --- a/sim/common/sim-core.c +++ b/sim/common/sim-core.c @@ -29,13 +29,6 @@ #include "sim-hw.h" #endif -#if (WITH_DEVICES) -/* TODO: create sim/common/device.h */ -void device_error (device *me, char* message, ...); -int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia); -int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia); -#endif - /* "core" module install handler. This is called via sim_module_install to install the "core" @@ -534,6 +527,7 @@ sim_core_read_buffer (SIM_DESC sd, if (mapping->device != NULL) { int nr_bytes = len - count; + sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA; if (raddr + nr_bytes - 1> mapping->bound) nr_bytes = mapping->bound - raddr + 1; if (device_io_read_buffer (mapping->device, @@ -541,8 +535,9 @@ sim_core_read_buffer (SIM_DESC sd, mapping->space, raddr, nr_bytes, + sd, cpu, - CIA_GET (cpu)) != nr_bytes) + cia) != nr_bytes) break; count += nr_bytes; continue; @@ -599,6 +594,7 @@ sim_core_write_buffer (SIM_DESC sd, && mapping->device != NULL) { int nr_bytes = len - count; + sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA; if (raddr + nr_bytes - 1 > mapping->bound) nr_bytes = mapping->bound - raddr + 1; if (device_io_write_buffer (mapping->device, @@ -606,8 +602,9 @@ sim_core_write_buffer (SIM_DESC sd, mapping->space, raddr, nr_bytes, + sd, cpu, - CIA_GET(cpu)) != nr_bytes) + cia) != nr_bytes) break; count += nr_bytes; continue; diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h index 7bf15a3..182569e 100644 --- a/sim/common/sim-core.h +++ b/sim/common/sim-core.h @@ -340,4 +340,13 @@ DECLARE_SIM_CORE_READ_N(misaligned,7,8) #undef DECLARE_SIM_CORE_READ_N +#if (WITH_DEVICES) +/* TODO: create sim/common/device.h */ +/* These are defined with each particular cpu. */ +void device_error (device *me, char* message, ...); +int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); +int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); +#endif + + #endif diff --git a/sim/common/sim-events.c b/sim/common/sim-events.c index 4b7d9b4..fc21164 100644 --- a/sim/common/sim-events.c +++ b/sim/common/sim-events.c @@ -39,15 +39,6 @@ #include <signal.h> /* For SIGPROCMASK et.al. */ -#if __CYGWIN32__ -/* The ui_loop_hook is called to keep the GUI alive while the simulator - is running. The counter is to make sure we do not wake it too often. -*/ - -extern void (*ui_loop_hook) PARAMS ((int)); -static unsigned int ui_loop_hook_counter = 0; -#endif - typedef enum { watch_invalid, @@ -1171,18 +1162,6 @@ sim_events_process (SIM_DESC sd) /* this round of processing complete */ events->nr_ticks_to_process = 0; - -#if __CYGWIN32__ - /* Now call the ui_loop_hook to give the gui a chance to - process events. */ - - if (ui_loop_hook != NULL) - { - /* attempt to limit calls to 1-10 per second */ - if (! (ui_loop_hook_counter++ & 0xf)) - (*ui_loop_hook) (-2); /* magic */ - } -#endif } #endif diff --git a/sim/common/sim-io.c b/sim/common/sim-io.c index f3d2f67..26f4445 100644 --- a/sim/common/sim-io.c +++ b/sim/common/sim-io.c @@ -33,6 +33,13 @@ #include <unistd.h> #endif +/* Define the rate at which the simulator should poll the host + for a quit. */ +#ifndef POLL_QUIT_INTERVAL +#define POLL_QUIT_INTERVAL 0x10 +#endif + +static int poll_quit_count = POLL_QUIT_INTERVAL; /* See the file include/callbacks.h for a description */ @@ -304,9 +311,12 @@ sim_io_error(SIM_DESC sd, void sim_io_poll_quit(SIM_DESC sd) { - if (STATE_CALLBACK (sd)->poll_quit != NULL) - if (STATE_CALLBACK (sd)->poll_quit (STATE_CALLBACK (sd))) - sim_stop (sd); + if (STATE_CALLBACK (sd)->poll_quit != NULL && poll_quit_count-- < 0) + { + poll_quit_count = POLL_QUIT_INTERVAL; + if (STATE_CALLBACK (sd)->poll_quit (STATE_CALLBACK (sd))) + sim_stop (sd); + } } diff --git a/sim/common/sim-memopt.c b/sim/common/sim-memopt.c index be52a66..6e12a45 100644 --- a/sim/common/sim-memopt.c +++ b/sim/common/sim-memopt.c @@ -449,6 +449,10 @@ sim_memory_uninstall (SIM_DESC sd) /* delete it and its aliases */ alias = *entry; + + /* next victim */ + *entry = (*entry)->next; + while (alias != NULL) { sim_memopt *dead = alias; @@ -456,9 +460,6 @@ sim_memory_uninstall (SIM_DESC sd) sim_core_detach (sd, NULL, dead->level, dead->space, dead->addr); zfree (dead); } - - /* next victim */ - *entry = (*entry)->next; } } diff --git a/sim/common/sim-model.h b/sim/common/sim-model.h index 6f7769a..5272815 100644 --- a/sim/common/sim-model.h +++ b/sim/common/sim-model.h @@ -79,6 +79,9 @@ typedef struct { /* This is the argument to bfd_scan_arch. */ const char *bfd_name; #define MACH_BFD_NAME(m) ((m)->bfd_name) + enum mach_attr num; +#define MACH_NUM(m) ((m)->num) + int word_bitsize; #define MACH_WORD_BITSIZE(m) ((m)->word_bitsize) int addr_bitsize; diff --git a/sim/common/sim-n-core.h b/sim/common/sim-n-core.h index 46eca03..7a04a9f 100644 --- a/sim/common/sim-n-core.h +++ b/sim/common/sim-n-core.h @@ -167,7 +167,7 @@ sim_core_read_aligned_N(sim_cpu *cpu, if (WITH_CALLBACK_MEMORY && mapping->device != NULL) { unsigned_M data; - if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N) + if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N) device_error (mapping->device, "internal error - %s - io_read_buffer should not fail", XSTRING (sim_core_read_aligned_N)); val = T2H_M (data); @@ -298,7 +298,7 @@ sim_core_write_aligned_N(sim_cpu *cpu, if (WITH_CALLBACK_MEMORY && mapping->device != NULL) { unsigned_M data = H2T_M (val); - if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N) + if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N) device_error (mapping->device, "internal error - %s - io_write_buffer should not fail", XSTRING (sim_core_write_aligned_N)); break; diff --git a/sim/configure b/sim/configure index 9257de9..4d0232e 100755 --- a/sim/configure +++ b/sim/configure @@ -1413,6 +1413,7 @@ case "${target}" in h8500-*-*) sim_target=h8500 ;; i960-*-*) sim_target=i960 ;; m32r-*-*) sim_target=m32r ;; + mcore-*-*) sim_target=mcore ;; mips*-*-*) # The MIPS simulator can only be compiled by gcc. sim_target=mips @@ -1463,35 +1464,20 @@ case "${target}" in z8k*-*-*) sim_target=z8k ;; sparc64-*-*) only_if_gcc=yes - if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then - sim_target=sparc - extra_subdirs="${extra_subdirs} testsuite" - else - sim_target=none # Don't build erc32 if sparc64. - fi + sim_target=none # Don't build erc32 if sparc64. ;; sparclite*-*-* | sparc86x*-*-*) # The SPARC simulator can only be compiled by gcc. only_if_gcc=yes - if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then - sim_target=sparc - extra_subdirs="${extra_subdirs} testsuite" - else - sim_target=erc32 - fi + sim_target=erc32 ;; sparc*-*-*) # The SPARC simulator can only be compiled by gcc. only_if_gcc=yes - if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then - sim_target=sparc - extra_subdirs="${extra_subdirs} testsuite" - else - # Unfortunately erc32 won't build on many hosts, so only enable - # it if the user really really wants it. - only_if_enabled=yes - sim_target=erc32 - fi + # Unfortunately erc32 won't build on many hosts, so only enable + # it if the user really really wants it. + only_if_enabled=yes + sim_target=erc32 ;; *) sim_target=none ;; esac diff --git a/sim/configure.in b/sim/configure.in index 5e316da..c373049 100644 --- a/sim/configure.in +++ b/sim/configure.in @@ -61,6 +61,7 @@ case "${target}" in h8500-*-*) sim_target=h8500 ;; i960-*-*) sim_target=i960 ;; m32r-*-*) sim_target=m32r ;; + mcore-*-*) sim_target=mcore ;; mips*-*-*) # The MIPS simulator can only be compiled by gcc. sim_target=mips @@ -111,35 +112,20 @@ case "${target}" in z8k*-*-*) sim_target=z8k ;; sparc64-*-*) only_if_gcc=yes - if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then - sim_target=sparc - extra_subdirs="${extra_subdirs} testsuite" - else - sim_target=none # Don't build erc32 if sparc64. - fi + sim_target=none # Don't build erc32 if sparc64. ;; sparclite*-*-* | sparc86x*-*-*) # The SPARC simulator can only be compiled by gcc. only_if_gcc=yes - if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then - sim_target=sparc - extra_subdirs="${extra_subdirs} testsuite" - else - sim_target=erc32 - fi + sim_target=erc32 ;; sparc*-*-*) # The SPARC simulator can only be compiled by gcc. only_if_gcc=yes - if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then - sim_target=sparc - extra_subdirs="${extra_subdirs} testsuite" - else - # Unfortunately erc32 won't build on many hosts, so only enable - # it if the user really really wants it. - only_if_enabled=yes - sim_target=erc32 - fi + # Unfortunately erc32 won't build on many hosts, so only enable + # it if the user really really wants it. + only_if_enabled=yes + sim_target=erc32 ;; *) sim_target=none ;; esac diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 73b8c92..2c0297a 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,24 @@ +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * interp.c (ui_loop_hook_counter): New global (when NEED_UI_LOOP_HOOK + defined). + (sim_resume): If the counter has expired, call the ui_loop_hook, + if defined. + (UI_LOOP_POLL_INTERVAL): Define. Used to tweak the frequency of + ui_loop_hook calls. + * Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK. + +Wed Mar 10 19:32:13 1999 Nick Clifton <nickc@cygnus.com> + + * simops.c: If load instruction with auto increment/decrement + addressing is used when the destination register is the same as + the address register, then ignore the auto increment/decrement. + +Wed Mar 10 19:32:13 1999 Martin M. Hunt <hunt@cygnus.com> + + * simops.c (OP_5F00): Ifdef SYS_stat case because + not all systems have it defined. + 1999-01-26 Jason Molenda (jsm@bugshack.cygnus.com) * simops.c (OP_5607): Correct saturation comparison/assignment. diff --git a/sim/d10v/Makefile.in b/sim/d10v/Makefile.in index 0732327..602ffff 100644 --- a/sim/d10v/Makefile.in +++ b/sim/d10v/Makefile.in @@ -20,6 +20,7 @@ SIM_OBJS = interp.o table.o simops.o endian.o sim-load.o SIM_EXTRA_CLEAN = clean-extra +SIM_EXTRA_CFLAGS = -DNEED_UI_LOOP_HOOK INCLUDE = d10v_sim.h $(srcroot)/include/callback.h targ-vals.h endian.c diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 17c964f..4602ed2 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -39,6 +39,17 @@ static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value) extern void sim_set_profile PARAMS ((int n)); extern void sim_set_profile_size PARAMS ((int n)); +#ifdef NEED_UI_LOOP_HOOK +/* How often to run the ui_loop update, when in use */ +#define UI_LOOP_POLL_INTERVAL 0x14000 + +/* Counter for the ui_loop_hook update */ +static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + +/* Actual hook to call to run through gdb's gui event loop */ +extern int (*ui_loop_hook) PARAMS ((int signo)); +#endif /* NEED_UI_LOOP_HOOK */ + #ifndef INLINE #if defined(__GNUC__) && defined(__OPTIMIZE__) #define INLINE __inline__ @@ -784,6 +795,13 @@ sim_resume (sd, step, siggnal) /* Writeback all the DATA / PC changes */ SLOT_FLUSH (); +#ifdef NEED_UI_LOOP_HOOK + if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) + { + ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + ui_loop_hook (0); + } +#endif /* NEED_UI_LOOP_HOOK */ } while ( !State.exception && !stop_simulator); diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index c64ba42..0614c9f 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1333,7 +1333,8 @@ OP_6601 () trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); tmp = RLW (addr); SET_GPR32 (OP[0], tmp); - INC_ADDR (OP[1], -4); + if (OP[0] != OP[1]) + INC_ADDR (OP[1], -4); trace_output_32 (tmp); } @@ -1346,7 +1347,8 @@ OP_6201 () trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); tmp = RLW (addr); SET_GPR32 (OP[0], tmp); - INC_ADDR (OP[1], 4); + if (OP[0] != OP[1]) + INC_ADDR (OP[1], 4); trace_output_32 (tmp); } @@ -3124,6 +3126,7 @@ OP_5F00 () trace_output_void (); break; +#ifdef TARGET_SYS_stat case TARGET_SYS_stat: trace_input ("<stat>", OP_R0, OP_R1, OP_VOID); /* stat system call */ @@ -3152,6 +3155,7 @@ OP_5F00 () } trace_output_16 (result); break; +#endif case TARGET_SYS_chown: trace_input ("<chown>", OP_R0, OP_R1, OP_R2); diff --git a/sim/d30v/ChangeLog b/sim/d30v/ChangeLog index 668d89e..7687595 100644 --- a/sim/d30v/ChangeLog +++ b/sim/d30v/ChangeLog @@ -1,3 +1,16 @@ +1999-03-16 Martin Hunt <hunt@cygnus.com> + From Frank Ch. Eigler <fche@cygnus.com> + + * cpu.h (mvtsys_left_p): New flag for MVTSYS instruction history. + * d30v-insns (mvtsys): Set this flag instead of left_kills_right_p. + (do_sath): Detect MVTSYS by new flag. + * engine.c (unqueue_writes): Detect MVTSYS by new flag. + (do_2_short, do_parallel): Initialize new flag. + +1999-02-26 Frank Ch. Eigler <fche@cygnus.com> + + * tconfig.in (SIM_HANDLES_LMA): Make it so. + 1999-01-12 Frank Ch. Eigler <fche@cygnus.com> * engine.c (unqueue_writes): Make PSW conflict resolution code diff --git a/sim/d30v/cpu.h b/sim/d30v/cpu.h index 6190e61..d24a4ac 100644 --- a/sim/d30v/cpu.h +++ b/sim/d30v/cpu.h @@ -115,6 +115,7 @@ struct _sim_cpu { int trace_trap_p; /* If unknown traps dump out the regs */ int trace_action; /* trace bits at end of instructions */ int left_kills_right_p; /* left insn kills insn in right slot of -> */ + int mvtsys_left_p; /* left insn was mvtsys */ int did_trap; /* we did a trap & need to finish it */ struct _write32 write32; /* queued up 32-bit writes */ struct _write64 write64; /* queued up 64-bit writes */ diff --git a/sim/d30v/d30v-insns b/sim/d30v/d30v-insns index 6dc4f6b..5b34e80 100644 --- a/sim/d30v/d30v-insns +++ b/sim/d30v/d30v-insns @@ -1520,11 +1520,11 @@ _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS else { unsigned32 value = Rb; + CPU->mvtsys_left_p = 1; if (CR == processor_status_word_cr) { unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */ value = ds | (value & PSW_VALID); - CPU->left_kills_right_p = 1; } else if (CR == backup_processor_status_word_cr || CR == debug_backup_processor_status_word_cr) @@ -1537,19 +1537,16 @@ _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS case 1: /* PSWL */ WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31), PSW_VALID & 0x0000ffff); - CPU->left_kills_right_p = 1; break; case 2: /* PSWH */ { unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */ WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds, (PSW_VALID | ds) & 0xffff0000); - CPU->left_kills_right_p = 1; } break; case 3: /* FLAG */ PSW_FLAG_SET_QUEUE(CR, Rb & 1); - CPU->left_kills_right_p = 1; break; default: sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID"); @@ -1745,7 +1742,7 @@ void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int u if (updates_f4) { /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */ - if(STATE_CPU (sd, 0)->left_kills_right_p) + if(STATE_CPU (sd, 0)->mvtsys_left_p) unqueue_writes (sd, STATE_CPU (sd, 0), cia); PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1)); } diff --git a/sim/d30v/engine.c b/sim/d30v/engine.c index 402a2f5..2bbaad1 100644 --- a/sim/d30v/engine.c +++ b/sim/d30v/engine.c @@ -134,9 +134,9 @@ unqueue_writes (SIM_DESC sd, if (ptr == psw_addr) { - /* If MU instruction was not a MVTSYS (lkr), resolve PSW + /* If MU instruction was not a MVTSYS, resolve PSW contention in favour of IU. */ - if(! STATE_CPU (sd, 0)->left_kills_right_p) + if(! STATE_CPU (sd, 0)->mvtsys_left_p) { /* Detect contention in parallel writes to the same PSW flags. The hardware allows the updates from IU to prevail over @@ -249,6 +249,7 @@ do_2_short (SIM_DESC sd, /* run the first instruction */ STATE_CPU (sd, 0)->unit = unit; STATE_CPU (sd, 0)->left_kills_right_p = 0; + STATE_CPU (sd, 0)->mvtsys_left_p = 0; nia = s_idecode_issue(sd, insn1, cia); @@ -267,6 +268,7 @@ do_2_short (SIM_DESC sd, } STATE_CPU (sd, 0)->left_kills_right_p = 0; + STATE_CPU (sd, 0)->mvtsys_left_p = 0; return nia; } @@ -283,6 +285,7 @@ do_parallel (SIM_DESC sd, /* run the first instruction */ STATE_CPU (sd, 0)->unit = memory_unit; STATE_CPU (sd, 0)->left_kills_right_p = 0; + STATE_CPU (sd, 0)->mvtsys_left_p = 0; nia_left = s_idecode_issue(sd, left_insn, cia); diff --git a/sim/d30v/tconfig.in b/sim/d30v/tconfig.in index c742b36..4efbb91 100644 --- a/sim/d30v/tconfig.in +++ b/sim/d30v/tconfig.in @@ -2,3 +2,7 @@ /* Define this to enable the intrinsic breakpoint mechanism. */ #define SIM_HAVE_BREAKPOINTS + +/* See sim-hload.c. We properly handle LMA. */ +#define SIM_HANDLES_LMA 1 + diff --git a/sim/erc32/ChangeLog b/sim/erc32/ChangeLog index b908a50..4375a58 100644 --- a/sim/erc32/ChangeLog +++ b/sim/erc32/ChangeLog @@ -1,3 +1,8 @@ +1999-03-03 DJ Delorie <dj@cygnus.com> + + * configure.in: add termcap and -luser32 for host=cygwin + * configure: regenerate + 1999-02-11 Hugo Tyson <hmt@cygnus.co.uk> * exec.c (dispatch_instruction): diff --git a/sim/erc32/configure b/sim/erc32/configure index 793acef..d08ac33 100755 --- a/sim/erc32/configure +++ b/sim/erc32/configure @@ -132,8 +132,10 @@ sim_inline="-DDEFAULT_INLINE=0" + + # Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.12.2 +# Generated automatically using autoconf version 2.13 # Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. # # This configure script is free software; the Free Software Foundation @@ -483,7 +485,7 @@ EOF verbose=yes ;; -version | --version | --versio | --versi | --vers) - echo "configure generated by autoconf version 2.12.2" + echo "configure generated by autoconf version 2.13" exit 0 ;; -with-* | --with-*) @@ -673,7 +675,7 @@ fi echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 -echo "configure:677: checking how to run the C preprocessor" >&5 +echo "configure:679: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -688,13 +690,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext <<EOF -#line 692 "configure" +#line 694 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:698: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:700: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -705,13 +707,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext <<EOF -#line 709 "configure" +#line 711 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:715: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:717: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -722,13 +724,13 @@ else rm -rf conftest* CPP="${CC-cc} -nologo -E" cat > conftest.$ac_ext <<EOF -#line 726 "configure" +#line 728 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:732: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:734: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -753,7 +755,7 @@ fi echo "$ac_t""$CPP" 1>&6 echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 -echo "configure:757: checking whether ${MAKE-make} sets \${MAKE}" >&5 +echo "configure:759: checking whether ${MAKE-make} sets \${MAKE}" >&5 set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -780,7 +782,7 @@ else fi echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 -echo "configure:784: checking for POSIXized ISC" >&5 +echo "configure:786: checking for POSIXized ISC" >&5 if test -d /etc/conf/kconfig.d && grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 then @@ -801,12 +803,12 @@ else fi echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 -echo "configure:805: checking for ANSI C header files" >&5 +echo "configure:807: checking for ANSI C header files" >&5 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 810 "configure" +#line 812 "configure" #include "confdefs.h" #include <stdlib.h> #include <stdarg.h> @@ -814,7 +816,7 @@ else #include <float.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:818: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:820: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -831,7 +833,7 @@ rm -f conftest* if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 835 "configure" +#line 837 "configure" #include "confdefs.h" #include <string.h> EOF @@ -849,7 +851,7 @@ fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 853 "configure" +#line 855 "configure" #include "confdefs.h" #include <stdlib.h> EOF @@ -870,7 +872,7 @@ if test "$cross_compiling" = yes; then : else cat > conftest.$ac_ext <<EOF -#line 874 "configure" +#line 876 "configure" #include "confdefs.h" #include <ctype.h> #define ISLOWER(c) ('a' <= (c) && (c) <= 'z') @@ -881,7 +883,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); exit (0); } EOF -if { (eval echo configure:885: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:887: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then : else @@ -905,12 +907,12 @@ EOF fi echo $ac_n "checking for working const""... $ac_c" 1>&6 -echo "configure:909: checking for working const" >&5 +echo "configure:911: checking for working const" >&5 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 914 "configure" +#line 916 "configure" #include "confdefs.h" int main() { @@ -959,7 +961,7 @@ ccp = (char const *const *) p; ; return 0; } EOF -if { (eval echo configure:963: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:965: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_const=yes else @@ -980,21 +982,21 @@ EOF fi echo $ac_n "checking for inline""... $ac_c" 1>&6 -echo "configure:984: checking for inline" >&5 +echo "configure:986: checking for inline" >&5 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat > conftest.$ac_ext <<EOF -#line 991 "configure" +#line 993 "configure" #include "confdefs.h" int main() { } $ac_kw foo() { ; return 0; } EOF -if { (eval echo configure:998: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1000: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_inline=$ac_kw; break else @@ -1020,12 +1022,12 @@ EOF esac echo $ac_n "checking for off_t""... $ac_c" 1>&6 -echo "configure:1024: checking for off_t" >&5 +echo "configure:1026: checking for off_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1029 "configure" +#line 1031 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -1034,7 +1036,7 @@ else #endif EOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - egrep "off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then rm -rf conftest* ac_cv_type_off_t=yes else @@ -1053,12 +1055,12 @@ EOF fi echo $ac_n "checking for size_t""... $ac_c" 1>&6 -echo "configure:1057: checking for size_t" >&5 +echo "configure:1059: checking for size_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1062 "configure" +#line 1064 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -1067,7 +1069,7 @@ else #endif EOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - egrep "size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then rm -rf conftest* ac_cv_type_size_t=yes else @@ -1088,19 +1090,19 @@ fi # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 -echo "configure:1092: checking for working alloca.h" >&5 +echo "configure:1094: checking for working alloca.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1097 "configure" +#line 1099 "configure" #include "confdefs.h" #include <alloca.h> int main() { char *p = alloca(2 * sizeof(int)); ; return 0; } EOF -if { (eval echo configure:1104: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1106: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_header_alloca_h=yes else @@ -1121,12 +1123,12 @@ EOF fi echo $ac_n "checking for alloca""... $ac_c" 1>&6 -echo "configure:1125: checking for alloca" >&5 +echo "configure:1127: checking for alloca" >&5 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1130 "configure" +#line 1132 "configure" #include "confdefs.h" #ifdef __GNUC__ @@ -1154,7 +1156,7 @@ int main() { char *p = (char *) alloca(1); ; return 0; } EOF -if { (eval echo configure:1158: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1160: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_func_alloca_works=yes else @@ -1186,12 +1188,12 @@ EOF echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 -echo "configure:1190: checking whether alloca needs Cray hooks" >&5 +echo "configure:1192: checking whether alloca needs Cray hooks" >&5 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1195 "configure" +#line 1197 "configure" #include "confdefs.h" #if defined(CRAY) && ! defined(CRAY2) webecray @@ -1216,12 +1218,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6 if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:1220: checking for $ac_func" >&5 +echo "configure:1222: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1225 "configure" +#line 1227 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -1244,7 +1246,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:1248: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1250: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -1271,7 +1273,7 @@ done fi echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 -echo "configure:1275: checking stack direction for C alloca" >&5 +echo "configure:1277: checking stack direction for C alloca" >&5 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1279,7 +1281,7 @@ else ac_cv_c_stack_direction=0 else cat > conftest.$ac_ext <<EOF -#line 1283 "configure" +#line 1285 "configure" #include "confdefs.h" find_stack_direction () { @@ -1298,7 +1300,7 @@ main () exit (find_stack_direction() < 0); } EOF -if { (eval echo configure:1302: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:1304: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_stack_direction=1 else @@ -1323,17 +1325,17 @@ for ac_hdr in unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:1327: checking for $ac_hdr" >&5 +echo "configure:1329: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1332 "configure" +#line 1334 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1337: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1339: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -1362,12 +1364,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:1366: checking for $ac_func" >&5 +echo "configure:1368: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1371 "configure" +#line 1373 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -1390,7 +1392,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:1394: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1396: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -1415,7 +1417,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:1419: checking for working mmap" >&5 +echo "configure:1421: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1423,7 +1425,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 1427 "configure" +#line 1429 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -1563,7 +1565,7 @@ main() } EOF -if { (eval echo configure:1567: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:1569: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -1636,7 +1638,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } fi echo $ac_n "checking host system type""... $ac_c" 1>&6 -echo "configure:1640: checking host system type" >&5 +echo "configure:1642: checking host system type" >&5 host_alias=$host case "$host_alias" in @@ -1657,7 +1659,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$host" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6 -echo "configure:1661: checking target system type" >&5 +echo "configure:1663: checking target system type" >&5 target_alias=$target case "$target_alias" in @@ -1675,7 +1677,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$target" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6 -echo "configure:1679: checking build system type" >&5 +echo "configure:1681: checking build system type" >&5 build_alias=$build case "$build_alias" in @@ -1719,7 +1721,7 @@ test "$program_transform_name" = "" && program_transform_name="s,x,x," # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1723: checking for $ac_word" >&5 +echo "configure:1725: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1727,7 +1729,8 @@ else ac_cv_prog_CC="$CC" # Let the user override the test. else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_prog_CC="gcc" @@ -1748,7 +1751,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1752: checking for $ac_word" >&5 +echo "configure:1755: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1757,7 +1760,8 @@ else else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" ac_prog_rejected=no - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then @@ -1798,7 +1802,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1802: checking for $ac_word" >&5 +echo "configure:1806: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1806,7 +1810,8 @@ else ac_cv_prog_CC="$CC" # Let the user override the test. else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_prog_CC="cl" @@ -1829,7 +1834,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:1833: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:1838: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -1838,12 +1843,14 @@ ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' cross_compiling=$ac_cv_prog_cc_cross -cat > conftest.$ac_ext <<EOF -#line 1843 "configure" +cat > conftest.$ac_ext << EOF + +#line 1849 "configure" #include "confdefs.h" + main(){return(0);} EOF -if { (eval echo configure:1847: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1854: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -1857,18 +1864,24 @@ else ac_cv_prog_cc_works=no fi rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:1867: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:1880: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:1872: checking whether we are using GNU C" >&5 +echo "configure:1885: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1877,7 +1890,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1881: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1894: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -1896,7 +1909,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:1900: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:1913: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1939,7 +1952,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:1943: checking for a BSD compatible install" >&5 +echo "configure:1956: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1987,6 +2000,8 @@ echo "$ac_t""$INSTALL" 1>&6 # It thinks the first close brace ends the variable substitution. test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' + test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' @@ -2005,7 +2020,7 @@ AR=${AR-ar} # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2009: checking for $ac_word" >&5 +echo "configure:2024: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2013,7 +2028,8 @@ else ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_prog_RANLIB="ranlib" @@ -2039,17 +2055,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2043: checking for $ac_hdr" >&5 +echo "configure:2059: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2048 "configure" +#line 2064 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2053: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2069: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2079,12 +2095,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2083: checking for $ac_func" >&5 +echo "configure:2099: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2088 "configure" +#line 2104 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2107,7 +2123,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2111: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2127: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2136,12 +2152,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2140: checking for $ac_func" >&5 +echo "configure:2156: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2145 "configure" +#line 2161 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2164,7 +2180,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2168: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2184: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2198,19 +2214,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:2202: checking for LC_MESSAGES" >&5 +echo "configure:2218: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2207 "configure" +#line 2223 "configure" #include "confdefs.h" #include <locale.h> int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:2214: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2230: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -2231,7 +2247,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:2235: checking whether NLS is requested" >&5 +echo "configure:2251: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -2251,7 +2267,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:2255: checking whether included gettext is requested" >&5 +echo "configure:2271: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -2270,17 +2286,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:2274: checking for libintl.h" >&5 +echo "configure:2290: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2279 "configure" +#line 2295 "configure" #include "confdefs.h" #include <libintl.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2284: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2300: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2297,19 +2313,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:2301: checking for gettext in libc" >&5 +echo "configure:2317: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2306 "configure" +#line 2322 "configure" #include "confdefs.h" #include <libintl.h> int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:2313: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2329: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -2325,7 +2341,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:2329: checking for bindtextdomain in -lintl" >&5 +echo "configure:2345: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -2333,7 +2349,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <<EOF -#line 2337 "configure" +#line 2353 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -2344,7 +2360,7 @@ int main() { bindtextdomain() ; return 0; } EOF -if { (eval echo configure:2348: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2364: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -2360,19 +2376,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:2364: checking for gettext in libintl" >&5 +echo "configure:2380: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2369 "configure" +#line 2385 "configure" #include "confdefs.h" int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:2376: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2392: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -2400,7 +2416,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2404: checking for $ac_word" >&5 +echo "configure:2420: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2434,12 +2450,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2438: checking for $ac_func" >&5 +echo "configure:2454: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2443 "configure" +#line 2459 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2462,7 +2478,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2466: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2482: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2489,7 +2505,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2493: checking for $ac_word" >&5 +echo "configure:2509: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2502,7 +2518,8 @@ else ;; *) IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_path_GMSGFMT="$ac_dir/$ac_word" @@ -2524,7 +2541,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2528: checking for $ac_word" >&5 +echo "configure:2545: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2556,7 +2573,7 @@ else fi cat > conftest.$ac_ext <<EOF -#line 2560 "configure" +#line 2577 "configure" #include "confdefs.h" int main() { @@ -2564,7 +2581,7 @@ extern int _nl_msg_cat_cntr; return _nl_msg_cat_cntr ; return 0; } EOF -if { (eval echo configure:2568: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -2596,7 +2613,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2600: checking for $ac_word" >&5 +echo "configure:2617: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2630,7 +2647,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2634: checking for $ac_word" >&5 +echo "configure:2651: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2643,7 +2660,8 @@ else ;; *) IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_path_GMSGFMT="$ac_dir/$ac_word" @@ -2665,7 +2683,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2669: checking for $ac_word" >&5 +echo "configure:2687: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2755,7 +2773,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:2759: checking for catalogs to be installed" >&5 +echo "configure:2777: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -2783,17 +2801,17 @@ echo "configure:2759: checking for catalogs to be installed" >&5 if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:2787: checking for linux/version.h" >&5 +echo "configure:2805: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2792 "configure" +#line 2810 "configure" #include "confdefs.h" #include <linux/version.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2797: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2815: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2862,17 +2880,17 @@ for ac_hdr in stdlib.h string.h strings.h unistd.h time.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2866: checking for $ac_hdr" >&5 +echo "configure:2884: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2871 "configure" +#line 2889 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2876: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2894: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2902,17 +2920,17 @@ for ac_hdr in sys/time.h sys/resource.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2906: checking for $ac_hdr" >&5 +echo "configure:2924: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2911 "configure" +#line 2929 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2916: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2934: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2942,17 +2960,57 @@ for ac_hdr in fcntl.h fpu_control.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2946: checking for $ac_hdr" >&5 +echo "configure:2964: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2951 "configure" +#line 2969 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2956: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2974: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <<EOF +#define $ac_tr_hdr 1 +EOF + +else + echo "$ac_t""no" 1>&6 +fi +done + +for ac_hdr in dlfcn.h errno.h sys/stat.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3004: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <<EOF +#line 3009 "configure" +#include "confdefs.h" +#include <$ac_hdr> +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3014: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2981,12 +3039,12 @@ done for ac_func in getrusage time sigaction __setfpucw do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2985: checking for $ac_func" >&5 +echo "configure:3043: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2990 "configure" +#line 3048 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3009,7 +3067,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3013: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3071: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3036,7 +3094,7 @@ done # Check for socket libraries echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6 -echo "configure:3040: checking for bind in -lsocket" >&5 +echo "configure:3098: checking for bind in -lsocket" >&5 ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3044,7 +3102,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lsocket $LIBS" cat > conftest.$ac_ext <<EOF -#line 3048 "configure" +#line 3106 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3055,7 +3113,7 @@ int main() { bind() ; return 0; } EOF -if { (eval echo configure:3059: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3117: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3083,7 +3141,7 @@ else fi echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6 -echo "configure:3087: checking for gethostbyname in -lnsl" >&5 +echo "configure:3145: checking for gethostbyname in -lnsl" >&5 ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3091,7 +3149,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lnsl $LIBS" cat > conftest.$ac_ext <<EOF -#line 3095 "configure" +#line 3153 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3102,7 +3160,7 @@ int main() { gethostbyname() ; return 0; } EOF -if { (eval echo configure:3106: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3164: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3278,12 +3336,12 @@ fi echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 -echo "configure:3282: checking return type of signal handlers" >&5 +echo "configure:3340: checking return type of signal handlers" >&5 if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3287 "configure" +#line 3345 "configure" #include "confdefs.h" #include <sys/types.h> #include <signal.h> @@ -3300,7 +3358,7 @@ int main() { int i; ; return 0; } EOF -if { (eval echo configure:3304: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:3362: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_type_signal=void else @@ -3320,7 +3378,7 @@ EOF echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:3324: checking for executable suffix" >&5 +echo "configure:3382: checking for executable suffix" >&5 if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3368,17 +3426,17 @@ for ac_hdr in stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3372: checking for $ac_hdr" >&5 +echo "configure:3430: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3377 "configure" +#line 3435 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3382: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3440: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3405,8 +3463,39 @@ fi done -echo $ac_n "checking for main in -ltermcap""... $ac_c" 1>&6 -echo "configure:3410: checking for main in -ltermcap" >&5 +# In the Cygwin environment, we need some additional flags. +echo $ac_n "checking for cygwin""... $ac_c" 1>&6 +echo "configure:3469: checking for cygwin" >&5 +if eval "test \"`echo '$''{'sim_cv_os_cygwin'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <<EOF +#line 3474 "configure" +#include "confdefs.h" + +#ifdef __CYGWIN__ +lose +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "lose" >/dev/null 2>&1; then + rm -rf conftest* + sim_cv_os_cygwin=yes +else + rm -rf conftest* + sim_cv_os_cygwin=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$sim_cv_os_cygwin" 1>&6 + +if test x$sim_cv_os_cygwin = xyes; then + TERMCAP='`if test -r ../../libtermcap/libtermcap.a; then echo ../../libtermcap/libtermcap.a; else echo -ltermcap; fi` -luser32' +else + echo $ac_n "checking for main in -ltermcap""... $ac_c" 1>&6 +echo "configure:3499: checking for main in -ltermcap" >&5 ac_lib_var=`echo termcap'_'main | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3414,14 +3503,14 @@ else ac_save_LIBS="$LIBS" LIBS="-ltermcap $LIBS" cat > conftest.$ac_ext <<EOF -#line 3418 "configure" +#line 3507 "configure" #include "confdefs.h" int main() { main() ; return 0; } EOF -if { (eval echo configure:3425: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3514: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3442,6 +3531,7 @@ else TERMCAP="" fi +fi @@ -3469,7 +3559,7 @@ EOF # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. (set) 2>&1 | - case `(ac_space=' '; set) 2>&1 | grep ac_space` in + case `(ac_space=' '; set | grep ac_space) 2>&1` in *ac_space=\ *) # `set' does not quote correctly, so add quotes (double-quote substitution # turns \\\\ into \\, and sed turns \\ into \). @@ -3536,7 +3626,7 @@ do echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; -version | --version | --versio | --versi | --vers | --ver | --ve | --v) - echo "$CONFIG_STATUS generated by autoconf version 2.12.2" + echo "$CONFIG_STATUS generated by autoconf version 2.13" exit 0 ;; -help | --help | --hel | --he | --h) echo "\$ac_cs_usage"; exit 0 ;; @@ -3580,6 +3670,7 @@ s%@SHELL@%$SHELL%g s%@CFLAGS@%$CFLAGS%g s%@CPPFLAGS@%$CPPFLAGS%g s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g s%@DEFS@%$DEFS%g s%@LDFLAGS@%$LDFLAGS%g s%@LIBS@%$LIBS%g @@ -3615,6 +3706,7 @@ s%@build_vendor@%$build_vendor%g s%@build_os@%$build_os%g s%@CC@%$CC%g s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g +s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g s%@INSTALL_DATA@%$INSTALL_DATA%g s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g s%@HDEFINES@%$HDEFINES%g diff --git a/sim/erc32/configure.in b/sim/erc32/configure.in index c139f71..cef343d 100644 --- a/sim/erc32/configure.in +++ b/sim/erc32/configure.in @@ -7,7 +7,18 @@ SIM_AC_COMMON AC_CHECK_HEADERS(stdlib.h) -AC_CHECK_LIB(termcap, main, TERMCAP=-ltermcap, TERMCAP="") +# In the Cygwin environment, we need some additional flags. +AC_CACHE_CHECK([for cygwin], sim_cv_os_cygwin, +[AC_EGREP_CPP(lose, [ +#ifdef __CYGWIN__ +lose +#endif],[sim_cv_os_cygwin=yes],[sim_cv_os_cygwin=no])]) + +if test x$sim_cv_os_cygwin = xyes; then + TERMCAP='`if test -r ../../libtermcap/libtermcap.a; then echo ../../libtermcap/libtermcap.a; else echo -ltermcap; fi` -luser32' +else + AC_CHECK_LIB(termcap, main, TERMCAP=-ltermcap, TERMCAP="") +fi AC_SUBST(TERMCAP) SIM_AC_OUTPUT diff --git a/sim/fr30/ChangeLog b/sim/fr30/ChangeLog index dd399aa..7d0f18d 100644 --- a/sim/fr30/ChangeLog +++ b/sim/fr30/ChangeLog @@ -1,3 +1,44 @@ +Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com> + + * devices.c (device_io_read_buffer): New arg `sd'. + (device_io_write_buffer): New arg `sd'. + (device_error): Give proper arg spec. + +1999-04-10 Doug Evans <devans@casey.cygnus.com> + + * cpu.h,sem-switch.c,sem.c: Rebuild. + +1999-03-27 Doug Evans <devans@casey.cygnus.com> + + * decode.c: Rebuild. + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,model.c: Rebuild. + * fr30.c (fr30bf_fetch_register): Replace calls to a_fr30_h_* with + calls to fr30bf_h_*. + (fr30bf_store_register): Ditto. + * traps.c (setup_int): Ditto. + * sim-if.c (sim_open): Update call to fr30_cgen_cpu_open. + +Mon Mar 22 13:13:05 1999 Dave Brolley <brolley@cygnus.com> + + * configure.in: Use SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT). + * configure: Regenerate. + * cpu.h: Regenerate. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,cpu.c,cpu.h: Rebuild. + * fr30-sim.h (GET_H_SBIT,SET_H_SBIT): Delete. + (GET_H_CCR,SET_H_CCR,GET_H_SCR,SET_H_SCR,GET_H_ILM,SET_H_ILM): Delete. + (GET_H_PS,SET_H_PS,GET_H_DR,SET_H_DR): Delete. + * sim-if.c (sim_open): Update call to fr30_cgen_cpu_open. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * cpu.h: Rebuild. + 1999-02-09 Doug Evans <devans@casey.cygnus.com> * Makefile.in (SIM_EXTRA_DEPS): Add fr30-desc.h, delete cpu-opc.h. diff --git a/sim/fr30/arch.c b/sim/fr30/arch.c index db6e23e..55eea0d 100644 --- a/sim/fr30/arch.c +++ b/sim/fr30/arch.c @@ -33,663 +33,3 @@ const MACH *sim_machs[] = 0 }; -/* Get the value of h-pc. */ - -USI -a_fr30_h_pc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_pc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pc. */ - -void -a_fr30_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_pc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-gr. */ - -SI -a_fr30_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_gr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-gr. */ - -void -a_fr30_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_gr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cr. */ - -SI -a_fr30_h_cr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_cr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-cr. */ - -void -a_fr30_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_cr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-dr. */ - -SI -a_fr30_h_dr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_dr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-dr. */ - -void -a_fr30_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_dr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ps. */ - -USI -a_fr30_h_ps_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ps_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ps. */ - -void -a_fr30_h_ps_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ps_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-r13. */ - -SI -a_fr30_h_r13_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_r13_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-r13. */ - -void -a_fr30_h_r13_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_r13_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-r14. */ - -SI -a_fr30_h_r14_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_r14_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-r14. */ - -void -a_fr30_h_r14_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_r14_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-r15. */ - -SI -a_fr30_h_r15_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_r15_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-r15. */ - -void -a_fr30_h_r15_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_r15_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-nbit. */ - -BI -a_fr30_h_nbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_nbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-nbit. */ - -void -a_fr30_h_nbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_nbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-zbit. */ - -BI -a_fr30_h_zbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_zbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-zbit. */ - -void -a_fr30_h_zbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_zbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-vbit. */ - -BI -a_fr30_h_vbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_vbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-vbit. */ - -void -a_fr30_h_vbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_vbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cbit. */ - -BI -a_fr30_h_cbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_cbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cbit. */ - -void -a_fr30_h_cbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_cbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ibit. */ - -BI -a_fr30_h_ibit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ibit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ibit. */ - -void -a_fr30_h_ibit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ibit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-sbit. */ - -BI -a_fr30_h_sbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_sbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-sbit. */ - -void -a_fr30_h_sbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_sbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tbit. */ - -BI -a_fr30_h_tbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_tbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tbit. */ - -void -a_fr30_h_tbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_tbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-d0bit. */ - -BI -a_fr30_h_d0bit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_d0bit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-d0bit. */ - -void -a_fr30_h_d0bit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_d0bit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-d1bit. */ - -BI -a_fr30_h_d1bit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_d1bit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-d1bit. */ - -void -a_fr30_h_d1bit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_d1bit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ccr. */ - -UQI -a_fr30_h_ccr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ccr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ccr. */ - -void -a_fr30_h_ccr_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ccr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-scr. */ - -UQI -a_fr30_h_scr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_scr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-scr. */ - -void -a_fr30_h_scr_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_scr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ilm. */ - -UQI -a_fr30_h_ilm_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ilm_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ilm. */ - -void -a_fr30_h_ilm_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ilm_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - diff --git a/sim/fr30/arch.h b/sim/fr30/arch.h index 7bde11d..ffc516e 100644 --- a/sim/fr30/arch.h +++ b/sim/fr30/arch.h @@ -27,48 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #define TARGET_BIG_ENDIAN 1 -/* Cover fns for register access. */ -USI a_fr30_h_pc_get (SIM_CPU *); -void a_fr30_h_pc_set (SIM_CPU *, USI); -SI a_fr30_h_gr_get (SIM_CPU *, UINT); -void a_fr30_h_gr_set (SIM_CPU *, UINT, SI); -SI a_fr30_h_cr_get (SIM_CPU *, UINT); -void a_fr30_h_cr_set (SIM_CPU *, UINT, SI); -SI a_fr30_h_dr_get (SIM_CPU *, UINT); -void a_fr30_h_dr_set (SIM_CPU *, UINT, SI); -USI a_fr30_h_ps_get (SIM_CPU *); -void a_fr30_h_ps_set (SIM_CPU *, USI); -SI a_fr30_h_r13_get (SIM_CPU *); -void a_fr30_h_r13_set (SIM_CPU *, SI); -SI a_fr30_h_r14_get (SIM_CPU *); -void a_fr30_h_r14_set (SIM_CPU *, SI); -SI a_fr30_h_r15_get (SIM_CPU *); -void a_fr30_h_r15_set (SIM_CPU *, SI); -BI a_fr30_h_nbit_get (SIM_CPU *); -void a_fr30_h_nbit_set (SIM_CPU *, BI); -BI a_fr30_h_zbit_get (SIM_CPU *); -void a_fr30_h_zbit_set (SIM_CPU *, BI); -BI a_fr30_h_vbit_get (SIM_CPU *); -void a_fr30_h_vbit_set (SIM_CPU *, BI); -BI a_fr30_h_cbit_get (SIM_CPU *); -void a_fr30_h_cbit_set (SIM_CPU *, BI); -BI a_fr30_h_ibit_get (SIM_CPU *); -void a_fr30_h_ibit_set (SIM_CPU *, BI); -BI a_fr30_h_sbit_get (SIM_CPU *); -void a_fr30_h_sbit_set (SIM_CPU *, BI); -BI a_fr30_h_tbit_get (SIM_CPU *); -void a_fr30_h_tbit_set (SIM_CPU *, BI); -BI a_fr30_h_d0bit_get (SIM_CPU *); -void a_fr30_h_d0bit_set (SIM_CPU *, BI); -BI a_fr30_h_d1bit_get (SIM_CPU *); -void a_fr30_h_d1bit_set (SIM_CPU *, BI); -UQI a_fr30_h_ccr_get (SIM_CPU *); -void a_fr30_h_ccr_set (SIM_CPU *, UQI); -UQI a_fr30_h_scr_get (SIM_CPU *); -void a_fr30_h_scr_set (SIM_CPU *, UQI); -UQI a_fr30_h_ilm_get (SIM_CPU *); -void a_fr30_h_ilm_set (SIM_CPU *, UQI); - /* Enum declaration for model types. */ typedef enum model_type { MODEL_FR30_1, MODEL_MAX diff --git a/sim/fr30/configure b/sim/fr30/configure index 43063ad..b650e0c 100644 --- a/sim/fr30/configure +++ b/sim/fr30/configure @@ -3482,7 +3482,7 @@ else fi fi -wire_alignment="NONSTRICT_ALIGNMENT" +wire_alignment="FORCED_ALIGNMENT" default_alignment="" # Check whether --enable-sim-alignment or --disable-sim-alignment was given. diff --git a/sim/fr30/configure.in b/sim/fr30/configure.in index fc25dfc..cb01e13 100644 --- a/sim/fr30/configure.in +++ b/sim/fr30/configure.in @@ -6,7 +6,7 @@ AC_INIT(Makefile.in) SIM_AC_COMMON SIM_AC_OPTION_ENDIAN(BIG_ENDIAN) -SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT) +SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT) SIM_AC_OPTION_HOSTENDIAN SIM_AC_OPTION_SCACHE(16384) SIM_AC_OPTION_DEFAULT_MODEL(fr30-1) diff --git a/sim/fr30/cpu.c b/sim/fr30/cpu.c index c339a93..fb94688 100644 --- a/sim/fr30/cpu.c +++ b/sim/fr30/cpu.c @@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #define WANT_CPU_FR30BF #include "sim-main.h" +#include "cgen-ops.h" /* Get the value of h-pc. */ diff --git a/sim/fr30/cpu.h b/sim/fr30/cpu.h index 9a02863..13aceb4 100644 --- a/sim/fr30/cpu.h +++ b/sim/fr30/cpu.h @@ -50,21 +50,27 @@ typedef struct { #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) /* dedicated registers */ SI h_dr[6]; -/* GET_H_DR macro user-written */ -/* SET_H_DR macro user-written */ - /* program status */ +#define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index) +#define SET_H_DR(index, x) \ +do { \ +fr30bf_h_dr_set_handler (current_cpu, (index), (x));\ +} while (0) + /* processor status */ USI h_ps; -/* GET_H_PS macro user-written */ -/* SET_H_PS macro user-written */ - /* General Register 13 explicitely required */ +#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu) +#define SET_H_PS(x) \ +do { \ +fr30bf_h_ps_set_handler (current_cpu, (x));\ +} while (0) + /* General Register 13 explicitly required */ SI h_r13; #define GET_H_R13() CPU (h_r13) #define SET_H_R13(x) (CPU (h_r13) = (x)) - /* General Register 14 explicitely required */ + /* General Register 14 explicitly required */ SI h_r14; #define GET_H_R14() CPU (h_r14) #define SET_H_R14(x) (CPU (h_r14) = (x)) - /* General Register 15 explicitely required */ + /* General Register 15 explicitly required */ SI h_r15; #define GET_H_R15() CPU (h_r15) #define SET_H_R15(x) (CPU (h_r15) = (x)) @@ -88,10 +94,13 @@ typedef struct { BI h_ibit; #define GET_H_IBIT() CPU (h_ibit) #define SET_H_IBIT(x) (CPU (h_ibit) = (x)) - /* stack bit */ + /* stack bit */ BI h_sbit; -/* GET_H_SBIT macro user-written */ -/* SET_H_SBIT macro user-written */ +#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu) +#define SET_H_SBIT(x) \ +do { \ +fr30bf_h_sbit_set_handler (current_cpu, (x));\ +} while (0) /* trace trap bit */ BI h_tbit; #define GET_H_TBIT() CPU (h_tbit) @@ -104,18 +113,27 @@ typedef struct { BI h_d1bit; #define GET_H_D1BIT() CPU (h_d1bit) #define SET_H_D1BIT(x) (CPU (h_d1bit) = (x)) - /* condition code bits */ + /* condition code bits */ UQI h_ccr; -/* GET_H_CCR macro user-written */ -/* SET_H_CCR macro user-written */ +#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu) +#define SET_H_CCR(x) \ +do { \ +fr30bf_h_ccr_set_handler (current_cpu, (x));\ +} while (0) /* system condition bits */ UQI h_scr; -/* GET_H_SCR macro user-written */ -/* SET_H_SCR macro user-written */ - /* interrupt level mask */ +#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu) +#define SET_H_SCR(x) \ +do { \ +fr30bf_h_scr_set_handler (current_cpu, (x));\ +} while (0) + /* interrupt level mask */ UQI h_ilm; -/* GET_H_ILM macro user-written */ -/* SET_H_ILM macro user-written */ +#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu) +#define SET_H_ILM(x) \ +do { \ +fr30bf_h_ilm_set_handler (current_cpu, (x));\ +} while (0) } hardware; #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) } FR30BF_CPU_DATA; @@ -918,9 +936,9 @@ struct scache { f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_i20_4 = EXTRACT_UINT (insn, 16, 8, 4); \ f_i20_16 = (0|(EXTRACT_UINT (word_1, 16, 0, 16) << 0)); \ -do {\ +{\ f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\ -} while (0);\ +}\ f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ @@ -933,12 +951,14 @@ do {\ UINT f_Ri; \ /* Contents of trailing part of insn. */ \ UINT word_1; \ + UINT word_2; \ unsigned int length; #define EXTRACT_IFMT_LDI32_CODE \ length = 6; \ - word_1 = GETIMEMUSI (current_cpu, pc + 2); \ + word_1 = GETIMEMUHI (current_cpu, pc + 2); \ + word_2 = GETIMEMUHI (current_cpu, pc + 4); \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_i32 = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \ + f_i32 = (0|(EXTRACT_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_UINT (word_1, 16, 0, 16) << 16)); \ f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ diff --git a/sim/fr30/decode.c b/sim/fr30/decode.c index c6d1656..e41c45f 100644 --- a/sim/fr30/decode.c +++ b/sim/fr30/decode.c @@ -46,6 +46,11 @@ with this program; if not, write to the Free Software Foundation, Inc., #define FAST(fn) #endif +/* The INSN_ prefix is not here and is instead part of the `insn' argument + to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ +#define IDX(insn) CONCAT2 (FR30BF_,insn) +#define TYPE(insn) CONCAT2 (FR30_,insn) + /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -53,11 +58,6 @@ with this program; if not, write to the Free Software Foundation, Inc., addition of instructions nor an SMP machine with different cpus). */ static IDESC fr30bf_insn_data[FR30BF_INSN_MAX]; -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (FR30BF_,insn) -#define TYPE(insn) CONCAT2 (FR30_,insn) - /* Commas between elements are contained in the macros. Some of these are conditionally compiled out. */ @@ -241,6 +241,9 @@ static const struct insn_sem fr30bf_insn_sem_invalid = VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }; +#undef FMT +#undef FULL +#undef FAST #undef IDX #undef TYPE @@ -302,64 +305,6 @@ fr30bf_init_idesc_table (SIM_CPU *cpu) CPU_IDESC (cpu) = table; } -/* Enum declaration for all instruction semantic formats. */ -typedef enum sfmt { - FMT_EMPTY, FMT_ADD, FMT_ADDI, FMT_ADD2 - , FMT_ADDC, FMT_ADDN, FMT_ADDNI, FMT_ADDN2 - , FMT_CMP, FMT_CMPI, FMT_CMP2, FMT_AND - , FMT_ANDM, FMT_ANDH, FMT_ANDB, FMT_BANDL - , FMT_BTSTL, FMT_MUL, FMT_MULU, FMT_MULH - , FMT_DIV0S, FMT_DIV0U, FMT_DIV1, FMT_DIV2 - , FMT_DIV3, FMT_DIV4S, FMT_LSL, FMT_LSLI - , FMT_LDI8, FMT_LDI20, FMT_LDI32, FMT_LD - , FMT_LDUH, FMT_LDUB, FMT_LDR13, FMT_LDR13UH - , FMT_LDR13UB, FMT_LDR14, FMT_LDR14UH, FMT_LDR14UB - , FMT_LDR15, FMT_LDR15GR, FMT_LDR15DR, FMT_LDR15PS - , FMT_ST, FMT_STH, FMT_STB, FMT_STR13 - , FMT_STR13H, FMT_STR13B, FMT_STR14, FMT_STR14H - , FMT_STR14B, FMT_STR15, FMT_STR15GR, FMT_STR15DR - , FMT_STR15PS, FMT_MOV, FMT_MOVDR, FMT_MOVPS - , FMT_MOV2DR, FMT_MOV2PS, FMT_JMP, FMT_CALLR - , FMT_CALL, FMT_RET, FMT_INT, FMT_INTE - , FMT_RETI, FMT_BRAD, FMT_BNOD, FMT_BEQD - , FMT_BCD, FMT_BND, FMT_BVD, FMT_BLTD - , FMT_BLED, FMT_BLSD, FMT_DMOVR13, FMT_DMOVR13H - , FMT_DMOVR13B, FMT_DMOVR13PI, FMT_DMOVR13PIH, FMT_DMOVR13PIB - , FMT_DMOVR15PI, FMT_DMOV2R13, FMT_DMOV2R13H, FMT_DMOV2R13B - , FMT_DMOV2R13PI, FMT_DMOV2R13PIH, FMT_DMOV2R13PIB, FMT_DMOV2R15PD - , FMT_LDRES, FMT_COPOP, FMT_COPLD, FMT_COPST - , FMT_NOP, FMT_ANDCCR, FMT_STILM, FMT_ADDSP - , FMT_EXTSB, FMT_EXTUB, FMT_EXTSH, FMT_EXTUH - , FMT_LDM0, FMT_LDM1, FMT_STM0, FMT_STM1 - , FMT_ENTER, FMT_LEAVE, FMT_XCHB -} SFMT; - -/* The decoder uses this to record insns and direct extraction handling. */ - -typedef struct { - const IDESC *idesc; -#ifdef __GNUC__ - void *sfmt; -#else - enum sfmt sfmt; -#endif -} DECODE_DESC; - -/* Macro to go from decode phase to extraction phase. */ - -#ifdef __GNUC__ -#define GOTO_EXTRACT(id) goto *(id)->sfmt -#else -#define GOTO_EXTRACT(id) goto extract -#endif - -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) -#endif - /* Given an instruction, return a pointer to its IDESC entry. */ const IDESC * @@ -367,309 +312,342 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_INT base_insn, ARGBUF *abuf) { - /* Result of decoder, used by extractor. */ - const DECODE_DESC *idecode; - - /* First decode the instruction. */ + /* Result of decoder. */ + FR30BF_INSN_TYPE itype; { -#define I(insn) & fr30bf_insn_data[CONCAT2 (FR30BF_,insn)] -#ifdef __GNUC__ -#define E(fmt) && case_ex_##fmt -#else -#define E(fmt) fmt -#endif - CGEN_INSN_INT insn = base_insn; - static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) }; - - { -#ifdef __GNUC__ - static const void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_7, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_23, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_151, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_159, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - }; -#endif - static const DECODE_DESC insns[256] = { - { I (INSN_LDR13), E (FMT_LDR13) }, { I (INSN_LDR13UH), E (FMT_LDR13UH) }, - { I (INSN_LDR13UB), E (FMT_LDR13UB) }, { I (INSN_LDR15), E (FMT_LDR15) }, - { I (INSN_LD), E (FMT_LD) }, { I (INSN_LDUH), E (FMT_LDUH) }, - { I (INSN_LDUB), E (FMT_LDUB) }, { 0 }, - { I (INSN_DMOV2R13), E (FMT_DMOV2R13) }, { I (INSN_DMOV2R13H), E (FMT_DMOV2R13H) }, - { I (INSN_DMOV2R13B), E (FMT_DMOV2R13B) }, { I (INSN_DMOV2R15PD), E (FMT_DMOV2R15PD) }, - { I (INSN_DMOV2R13PI), E (FMT_DMOV2R13PI) }, { I (INSN_DMOV2R13PIH), E (FMT_DMOV2R13PIH) }, - { I (INSN_DMOV2R13PIB), E (FMT_DMOV2R13PIB) }, { I (INSN_ENTER), E (FMT_ENTER) }, - { I (INSN_STR13), E (FMT_STR13) }, { I (INSN_STR13H), E (FMT_STR13H) }, - { I (INSN_STR13B), E (FMT_STR13B) }, { I (INSN_STR15), E (FMT_STR15) }, - { I (INSN_ST), E (FMT_ST) }, { I (INSN_STH), E (FMT_STH) }, - { I (INSN_STB), E (FMT_STB) }, { 0 }, - { I (INSN_DMOVR13), E (FMT_DMOVR13) }, { I (INSN_DMOVR13H), E (FMT_DMOVR13H) }, - { I (INSN_DMOVR13B), E (FMT_DMOVR13B) }, { I (INSN_DMOVR15PI), E (FMT_DMOVR15PI) }, - { I (INSN_DMOVR13PI), E (FMT_DMOVR13PI) }, { I (INSN_DMOVR13PIH), E (FMT_DMOVR13PIH) }, - { I (INSN_DMOVR13PIB), E (FMT_DMOVR13PIB) }, { I (INSN_INT), E (FMT_INT) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_BANDL), E (FMT_BANDL) }, { I (INSN_BANDH), E (FMT_BANDL) }, - { I (INSN_AND), E (FMT_AND) }, { I (INSN_ANDCCR), E (FMT_ANDCCR) }, - { I (INSN_ANDM), E (FMT_ANDM) }, { I (INSN_ANDH), E (FMT_ANDH) }, - { I (INSN_ANDB), E (FMT_ANDB) }, { I (INSN_STILM), E (FMT_STILM) }, - { I (INSN_BTSTL), E (FMT_BTSTL) }, { I (INSN_BTSTH), E (FMT_BTSTL) }, - { I (INSN_XCHB), E (FMT_XCHB) }, { I (INSN_MOV), E (FMT_MOV) }, - { I (INSN_LDM0), E (FMT_LDM0) }, { I (INSN_LDM1), E (FMT_LDM1) }, - { I (INSN_STM0), E (FMT_STM0) }, { I (INSN_STM1), E (FMT_STM1) }, - { I (INSN_BORL), E (FMT_BANDL) }, { I (INSN_BORH), E (FMT_BANDL) }, - { I (INSN_OR), E (FMT_AND) }, { I (INSN_ORCCR), E (FMT_ANDCCR) }, - { I (INSN_ORM), E (FMT_ANDM) }, { I (INSN_ORH), E (FMT_ANDH) }, - { I (INSN_ORB), E (FMT_ANDB) }, { 0 }, - { I (INSN_BEORL), E (FMT_BANDL) }, { I (INSN_BEORH), E (FMT_BANDL) }, - { I (INSN_EOR), E (FMT_AND) }, { I (INSN_LDI20), E (FMT_LDI20) }, - { I (INSN_EORM), E (FMT_ANDM) }, { I (INSN_EORH), E (FMT_ANDH) }, - { I (INSN_EORB), E (FMT_ANDB) }, { 0 }, - { I (INSN_ADDNI), E (FMT_ADDNI) }, { I (INSN_ADDN2), E (FMT_ADDN2) }, - { I (INSN_ADDN), E (FMT_ADDN) }, { I (INSN_ADDSP), E (FMT_ADDSP) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADD2), E (FMT_ADD2) }, - { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_ADDC), E (FMT_ADDC) }, - { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMP2), E (FMT_CMP2) }, - { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_MULU), E (FMT_MULU) }, - { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_SUBC), E (FMT_ADDC) }, - { I (INSN_SUBN), E (FMT_ADDN) }, { I (INSN_MUL), E (FMT_MUL) }, - { I (INSN_LSRI), E (FMT_LSLI) }, { I (INSN_LSR2), E (FMT_LSLI) }, - { I (INSN_LSR), E (FMT_LSL) }, { I (INSN_MOV2DR), E (FMT_MOV2DR) }, - { I (INSN_LSLI), E (FMT_LSLI) }, { I (INSN_LSL2), E (FMT_LSLI) }, - { I (INSN_LSL), E (FMT_LSL) }, { I (INSN_MOVDR), E (FMT_MOVDR) }, - { I (INSN_ASRI), E (FMT_LSLI) }, { I (INSN_ASR2), E (FMT_LSLI) }, - { I (INSN_ASR), E (FMT_LSL) }, { I (INSN_MULUH), E (FMT_MULH) }, - { I (INSN_LDRES), E (FMT_LDRES) }, { I (INSN_STRES), E (FMT_LDRES) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MULH), E (FMT_MULH) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_BRA), E (FMT_BRAD) }, { I (INSN_BNO), E (FMT_BNOD) }, - { I (INSN_BEQ), E (FMT_BEQD) }, { I (INSN_BNE), E (FMT_BEQD) }, - { I (INSN_BC), E (FMT_BCD) }, { I (INSN_BNC), E (FMT_BCD) }, - { I (INSN_BN), E (FMT_BND) }, { I (INSN_BP), E (FMT_BND) }, - { I (INSN_BV), E (FMT_BVD) }, { I (INSN_BNV), E (FMT_BVD) }, - { I (INSN_BLT), E (FMT_BLTD) }, { I (INSN_BGE), E (FMT_BLTD) }, - { I (INSN_BLE), E (FMT_BLED) }, { I (INSN_BGT), E (FMT_BLED) }, - { I (INSN_BLS), E (FMT_BLSD) }, { I (INSN_BHI), E (FMT_BLSD) }, - { I (INSN_BRAD), E (FMT_BRAD) }, { I (INSN_BNOD), E (FMT_BNOD) }, - { I (INSN_BEQD), E (FMT_BEQD) }, { I (INSN_BNED), E (FMT_BEQD) }, - { I (INSN_BCD), E (FMT_BCD) }, { I (INSN_BNCD), E (FMT_BCD) }, - { I (INSN_BND), E (FMT_BND) }, { I (INSN_BPD), E (FMT_BND) }, - { I (INSN_BVD), E (FMT_BVD) }, { I (INSN_BNVD), E (FMT_BVD) }, - { I (INSN_BLTD), E (FMT_BLTD) }, { I (INSN_BGED), E (FMT_BLTD) }, - { I (INSN_BLED), E (FMT_BLED) }, { I (INSN_BGTD), E (FMT_BLED) }, - { I (INSN_BLSD), E (FMT_BLSD) }, { I (INSN_BHID), E (FMT_BLSD) }, - }; - unsigned int val; - val = (((insn >> 8) & (255 << 0))); - DECODE_SWITCH (0, val) + CGEN_INSN_INT insn = base_insn; + + { + unsigned int val = (((insn >> 8) & (255 << 0))); + switch (val) + { + case 0 : itype = FR30BF_INSN_LDR13; goto extract_fmt_ldr13; + case 1 : itype = FR30BF_INSN_LDR13UH; goto extract_fmt_ldr13uh; + case 2 : itype = FR30BF_INSN_LDR13UB; goto extract_fmt_ldr13ub; + case 3 : itype = FR30BF_INSN_LDR15; goto extract_fmt_ldr15; + case 4 : itype = FR30BF_INSN_LD; goto extract_fmt_ld; + case 5 : itype = FR30BF_INSN_LDUH; goto extract_fmt_lduh; + case 6 : itype = FR30BF_INSN_LDUB; goto extract_fmt_ldub; + case 7 : { - CASE (0, 7) : + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDR15GR), E (FMT_LDR15GR) }, { I (INSN_MOV2PS), E (FMT_MOV2PS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_LDR15DR), E (FMT_LDR15DR) }, { I (INSN_LDR15PS), E (FMT_LDR15PS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_LDR15GR; goto extract_fmt_ldr15gr; + case 1 : itype = FR30BF_INSN_MOV2PS; goto extract_fmt_mov2ps; + case 8 : itype = FR30BF_INSN_LDR15DR; goto extract_fmt_ldr15dr; + case 9 : itype = FR30BF_INSN_LDR15PS; goto extract_fmt_ldr15ps; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 23) : + } + case 8 : itype = FR30BF_INSN_DMOV2R13; goto extract_fmt_dmov2r13; + case 9 : itype = FR30BF_INSN_DMOV2R13H; goto extract_fmt_dmov2r13h; + case 10 : itype = FR30BF_INSN_DMOV2R13B; goto extract_fmt_dmov2r13b; + case 11 : itype = FR30BF_INSN_DMOV2R15PD; goto extract_fmt_dmov2r15pd; + case 12 : itype = FR30BF_INSN_DMOV2R13PI; goto extract_fmt_dmov2r13pi; + case 13 : itype = FR30BF_INSN_DMOV2R13PIH; goto extract_fmt_dmov2r13pih; + case 14 : itype = FR30BF_INSN_DMOV2R13PIB; goto extract_fmt_dmov2r13pib; + case 15 : itype = FR30BF_INSN_ENTER; goto extract_fmt_enter; + case 16 : itype = FR30BF_INSN_STR13; goto extract_fmt_str13; + case 17 : itype = FR30BF_INSN_STR13H; goto extract_fmt_str13h; + case 18 : itype = FR30BF_INSN_STR13B; goto extract_fmt_str13b; + case 19 : itype = FR30BF_INSN_STR15; goto extract_fmt_str15; + case 20 : itype = FR30BF_INSN_ST; goto extract_fmt_st; + case 21 : itype = FR30BF_INSN_STH; goto extract_fmt_sth; + case 22 : itype = FR30BF_INSN_STB; goto extract_fmt_stb; + case 23 : + { + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STR15GR), E (FMT_STR15GR) }, { I (INSN_MOVPS), E (FMT_MOVPS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_STR15DR), E (FMT_STR15DR) }, { I (INSN_STR15PS), E (FMT_STR15PS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_STR15GR; goto extract_fmt_str15gr; + case 1 : itype = FR30BF_INSN_MOVPS; goto extract_fmt_movps; + case 8 : itype = FR30BF_INSN_STR15DR; goto extract_fmt_str15dr; + case 9 : itype = FR30BF_INSN_STR15PS; goto extract_fmt_str15ps; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 151) : + } + case 24 : itype = FR30BF_INSN_DMOVR13; goto extract_fmt_dmovr13; + case 25 : itype = FR30BF_INSN_DMOVR13H; goto extract_fmt_dmovr13h; + case 26 : itype = FR30BF_INSN_DMOVR13B; goto extract_fmt_dmovr13b; + case 27 : itype = FR30BF_INSN_DMOVR15PI; goto extract_fmt_dmovr15pi; + case 28 : itype = FR30BF_INSN_DMOVR13PI; goto extract_fmt_dmovr13pi; + case 29 : itype = FR30BF_INSN_DMOVR13PIH; goto extract_fmt_dmovr13pih; + case 30 : itype = FR30BF_INSN_DMOVR13PIB; goto extract_fmt_dmovr13pib; + case 31 : itype = FR30BF_INSN_INT; goto extract_fmt_int; + case 32 : /* fall through */ + case 33 : /* fall through */ + case 34 : /* fall through */ + case 35 : /* fall through */ + case 36 : /* fall through */ + case 37 : /* fall through */ + case 38 : /* fall through */ + case 39 : /* fall through */ + case 40 : /* fall through */ + case 41 : /* fall through */ + case 42 : /* fall through */ + case 43 : /* fall through */ + case 44 : /* fall through */ + case 45 : /* fall through */ + case 46 : /* fall through */ + case 47 : itype = FR30BF_INSN_LDR14; goto extract_fmt_ldr14; + case 48 : /* fall through */ + case 49 : /* fall through */ + case 50 : /* fall through */ + case 51 : /* fall through */ + case 52 : /* fall through */ + case 53 : /* fall through */ + case 54 : /* fall through */ + case 55 : /* fall through */ + case 56 : /* fall through */ + case 57 : /* fall through */ + case 58 : /* fall through */ + case 59 : /* fall through */ + case 60 : /* fall through */ + case 61 : /* fall through */ + case 62 : /* fall through */ + case 63 : itype = FR30BF_INSN_STR14; goto extract_fmt_str14; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : /* fall through */ + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : /* fall through */ + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : /* fall through */ + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : itype = FR30BF_INSN_LDR14UH; goto extract_fmt_ldr14uh; + case 80 : /* fall through */ + case 81 : /* fall through */ + case 82 : /* fall through */ + case 83 : /* fall through */ + case 84 : /* fall through */ + case 85 : /* fall through */ + case 86 : /* fall through */ + case 87 : /* fall through */ + case 88 : /* fall through */ + case 89 : /* fall through */ + case 90 : /* fall through */ + case 91 : /* fall through */ + case 92 : /* fall through */ + case 93 : /* fall through */ + case 94 : /* fall through */ + case 95 : itype = FR30BF_INSN_STR14H; goto extract_fmt_str14h; + case 96 : /* fall through */ + case 97 : /* fall through */ + case 98 : /* fall through */ + case 99 : /* fall through */ + case 100 : /* fall through */ + case 101 : /* fall through */ + case 102 : /* fall through */ + case 103 : /* fall through */ + case 104 : /* fall through */ + case 105 : /* fall through */ + case 106 : /* fall through */ + case 107 : /* fall through */ + case 108 : /* fall through */ + case 109 : /* fall through */ + case 110 : /* fall through */ + case 111 : itype = FR30BF_INSN_LDR14UB; goto extract_fmt_ldr14ub; + case 112 : /* fall through */ + case 113 : /* fall through */ + case 114 : /* fall through */ + case 115 : /* fall through */ + case 116 : /* fall through */ + case 117 : /* fall through */ + case 118 : /* fall through */ + case 119 : /* fall through */ + case 120 : /* fall through */ + case 121 : /* fall through */ + case 122 : /* fall through */ + case 123 : /* fall through */ + case 124 : /* fall through */ + case 125 : /* fall through */ + case 126 : /* fall through */ + case 127 : itype = FR30BF_INSN_STR14B; goto extract_fmt_str14b; + case 128 : itype = FR30BF_INSN_BANDL; goto extract_fmt_bandl; + case 129 : itype = FR30BF_INSN_BANDH; goto extract_fmt_bandl; + case 130 : itype = FR30BF_INSN_AND; goto extract_fmt_and; + case 131 : itype = FR30BF_INSN_ANDCCR; goto extract_fmt_andccr; + case 132 : itype = FR30BF_INSN_ANDM; goto extract_fmt_andm; + case 133 : itype = FR30BF_INSN_ANDH; goto extract_fmt_andh; + case 134 : itype = FR30BF_INSN_ANDB; goto extract_fmt_andb; + case 135 : itype = FR30BF_INSN_STILM; goto extract_fmt_stilm; + case 136 : itype = FR30BF_INSN_BTSTL; goto extract_fmt_btstl; + case 137 : itype = FR30BF_INSN_BTSTH; goto extract_fmt_btstl; + case 138 : itype = FR30BF_INSN_XCHB; goto extract_fmt_xchb; + case 139 : itype = FR30BF_INSN_MOV; goto extract_fmt_mov; + case 140 : itype = FR30BF_INSN_LDM0; goto extract_fmt_ldm0; + case 141 : itype = FR30BF_INSN_LDM1; goto extract_fmt_ldm1; + case 142 : itype = FR30BF_INSN_STM0; goto extract_fmt_stm0; + case 143 : itype = FR30BF_INSN_STM1; goto extract_fmt_stm1; + case 144 : itype = FR30BF_INSN_BORL; goto extract_fmt_bandl; + case 145 : itype = FR30BF_INSN_BORH; goto extract_fmt_bandl; + case 146 : itype = FR30BF_INSN_OR; goto extract_fmt_and; + case 147 : itype = FR30BF_INSN_ORCCR; goto extract_fmt_andccr; + case 148 : itype = FR30BF_INSN_ORM; goto extract_fmt_andm; + case 149 : itype = FR30BF_INSN_ORH; goto extract_fmt_andh; + case 150 : itype = FR30BF_INSN_ORB; goto extract_fmt_andb; + case 151 : + { + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_JMP), E (FMT_JMP) }, { I (INSN_CALLR), E (FMT_CALLR) }, - { I (INSN_RET), E (FMT_RET) }, { I (INSN_RETI), E (FMT_RETI) }, - { I (INSN_DIV0S), E (FMT_DIV0S) }, { I (INSN_DIV0U), E (FMT_DIV0U) }, - { I (INSN_DIV1), E (FMT_DIV1) }, { I (INSN_DIV2), E (FMT_DIV2) }, - { I (INSN_EXTSB), E (FMT_EXTSB) }, { I (INSN_EXTUB), E (FMT_EXTUB) }, - { I (INSN_EXTSH), E (FMT_EXTSH) }, { I (INSN_EXTUH), E (FMT_EXTUH) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_JMP; goto extract_fmt_jmp; + case 1 : itype = FR30BF_INSN_CALLR; goto extract_fmt_callr; + case 2 : itype = FR30BF_INSN_RET; goto extract_fmt_ret; + case 3 : itype = FR30BF_INSN_RETI; goto extract_fmt_reti; + case 4 : itype = FR30BF_INSN_DIV0S; goto extract_fmt_div0s; + case 5 : itype = FR30BF_INSN_DIV0U; goto extract_fmt_div0u; + case 6 : itype = FR30BF_INSN_DIV1; goto extract_fmt_div1; + case 7 : itype = FR30BF_INSN_DIV2; goto extract_fmt_div2; + case 8 : itype = FR30BF_INSN_EXTSB; goto extract_fmt_extsb; + case 9 : itype = FR30BF_INSN_EXTUB; goto extract_fmt_extub; + case 10 : itype = FR30BF_INSN_EXTSH; goto extract_fmt_extsh; + case 11 : itype = FR30BF_INSN_EXTUH; goto extract_fmt_extuh; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 159) : + } + case 152 : itype = FR30BF_INSN_BEORL; goto extract_fmt_bandl; + case 153 : itype = FR30BF_INSN_BEORH; goto extract_fmt_bandl; + case 154 : itype = FR30BF_INSN_EOR; goto extract_fmt_and; + case 155 : itype = FR30BF_INSN_LDI20; goto extract_fmt_ldi20; + case 156 : itype = FR30BF_INSN_EORM; goto extract_fmt_andm; + case 157 : itype = FR30BF_INSN_EORH; goto extract_fmt_andh; + case 158 : itype = FR30BF_INSN_EORB; goto extract_fmt_andb; + case 159 : + { + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_JMPD), E (FMT_JMP) }, { I (INSN_CALLRD), E (FMT_CALLR) }, - { I (INSN_RET_D), E (FMT_RET) }, { I (INSN_INTE), E (FMT_INTE) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIV3), E (FMT_DIV3) }, { I (INSN_DIV4S), E (FMT_DIV4S) }, - { I (INSN_LDI32), E (FMT_LDI32) }, { I (INSN_LEAVE), E (FMT_LEAVE) }, - { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_COPOP), E (FMT_COPOP) }, { I (INSN_COPLD), E (FMT_COPLD) }, - { I (INSN_COPST), E (FMT_COPST) }, { I (INSN_COPSV), E (FMT_COPST) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_JMPD; goto extract_fmt_jmp; + case 1 : itype = FR30BF_INSN_CALLRD; goto extract_fmt_callr; + case 2 : itype = FR30BF_INSN_RET_D; goto extract_fmt_ret; + case 3 : itype = FR30BF_INSN_INTE; goto extract_fmt_inte; + case 6 : itype = FR30BF_INSN_DIV3; goto extract_fmt_div3; + case 7 : itype = FR30BF_INSN_DIV4S; goto extract_fmt_div4s; + case 8 : itype = FR30BF_INSN_LDI32; goto extract_fmt_ldi32; + case 9 : itype = FR30BF_INSN_LEAVE; goto extract_fmt_leave; + case 10 : itype = FR30BF_INSN_NOP; goto extract_fmt_nop; + case 12 : itype = FR30BF_INSN_COPOP; goto extract_fmt_copop; + case 13 : itype = FR30BF_INSN_COPLD; goto extract_fmt_copld; + case 14 : itype = FR30BF_INSN_COPST; goto extract_fmt_copst; + case 15 : itype = FR30BF_INSN_COPSV; goto extract_fmt_copst; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - DEFAULT (0) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); } - ENDSWITCH (0) + case 160 : itype = FR30BF_INSN_ADDNI; goto extract_fmt_addni; + case 161 : itype = FR30BF_INSN_ADDN2; goto extract_fmt_addn2; + case 162 : itype = FR30BF_INSN_ADDN; goto extract_fmt_addn; + case 163 : itype = FR30BF_INSN_ADDSP; goto extract_fmt_addsp; + case 164 : itype = FR30BF_INSN_ADDI; goto extract_fmt_addi; + case 165 : itype = FR30BF_INSN_ADD2; goto extract_fmt_add2; + case 166 : itype = FR30BF_INSN_ADD; goto extract_fmt_add; + case 167 : itype = FR30BF_INSN_ADDC; goto extract_fmt_addc; + case 168 : itype = FR30BF_INSN_CMPI; goto extract_fmt_cmpi; + case 169 : itype = FR30BF_INSN_CMP2; goto extract_fmt_cmp2; + case 170 : itype = FR30BF_INSN_CMP; goto extract_fmt_cmp; + case 171 : itype = FR30BF_INSN_MULU; goto extract_fmt_mulu; + case 172 : itype = FR30BF_INSN_SUB; goto extract_fmt_add; + case 173 : itype = FR30BF_INSN_SUBC; goto extract_fmt_addc; + case 174 : itype = FR30BF_INSN_SUBN; goto extract_fmt_addn; + case 175 : itype = FR30BF_INSN_MUL; goto extract_fmt_mul; + case 176 : itype = FR30BF_INSN_LSRI; goto extract_fmt_lsli; + case 177 : itype = FR30BF_INSN_LSR2; goto extract_fmt_lsli; + case 178 : itype = FR30BF_INSN_LSR; goto extract_fmt_lsl; + case 179 : itype = FR30BF_INSN_MOV2DR; goto extract_fmt_mov2dr; + case 180 : itype = FR30BF_INSN_LSLI; goto extract_fmt_lsli; + case 181 : itype = FR30BF_INSN_LSL2; goto extract_fmt_lsli; + case 182 : itype = FR30BF_INSN_LSL; goto extract_fmt_lsl; + case 183 : itype = FR30BF_INSN_MOVDR; goto extract_fmt_movdr; + case 184 : itype = FR30BF_INSN_ASRI; goto extract_fmt_lsli; + case 185 : itype = FR30BF_INSN_ASR2; goto extract_fmt_lsli; + case 186 : itype = FR30BF_INSN_ASR; goto extract_fmt_lsl; + case 187 : itype = FR30BF_INSN_MULUH; goto extract_fmt_mulh; + case 188 : itype = FR30BF_INSN_LDRES; goto extract_fmt_ldres; + case 189 : itype = FR30BF_INSN_STRES; goto extract_fmt_ldres; + case 191 : itype = FR30BF_INSN_MULH; goto extract_fmt_mulh; + case 192 : /* fall through */ + case 193 : /* fall through */ + case 194 : /* fall through */ + case 195 : /* fall through */ + case 196 : /* fall through */ + case 197 : /* fall through */ + case 198 : /* fall through */ + case 199 : /* fall through */ + case 200 : /* fall through */ + case 201 : /* fall through */ + case 202 : /* fall through */ + case 203 : /* fall through */ + case 204 : /* fall through */ + case 205 : /* fall through */ + case 206 : /* fall through */ + case 207 : itype = FR30BF_INSN_LDI8; goto extract_fmt_ldi8; + case 208 : /* fall through */ + case 209 : /* fall through */ + case 210 : /* fall through */ + case 211 : /* fall through */ + case 212 : /* fall through */ + case 213 : /* fall through */ + case 214 : /* fall through */ + case 215 : itype = FR30BF_INSN_CALL; goto extract_fmt_call; + case 216 : /* fall through */ + case 217 : /* fall through */ + case 218 : /* fall through */ + case 219 : /* fall through */ + case 220 : /* fall through */ + case 221 : /* fall through */ + case 222 : /* fall through */ + case 223 : itype = FR30BF_INSN_CALLD; goto extract_fmt_call; + case 224 : itype = FR30BF_INSN_BRA; goto extract_fmt_brad; + case 225 : itype = FR30BF_INSN_BNO; goto extract_fmt_bnod; + case 226 : itype = FR30BF_INSN_BEQ; goto extract_fmt_beqd; + case 227 : itype = FR30BF_INSN_BNE; goto extract_fmt_beqd; + case 228 : itype = FR30BF_INSN_BC; goto extract_fmt_bcd; + case 229 : itype = FR30BF_INSN_BNC; goto extract_fmt_bcd; + case 230 : itype = FR30BF_INSN_BN; goto extract_fmt_bnd; + case 231 : itype = FR30BF_INSN_BP; goto extract_fmt_bnd; + case 232 : itype = FR30BF_INSN_BV; goto extract_fmt_bvd; + case 233 : itype = FR30BF_INSN_BNV; goto extract_fmt_bvd; + case 234 : itype = FR30BF_INSN_BLT; goto extract_fmt_bltd; + case 235 : itype = FR30BF_INSN_BGE; goto extract_fmt_bltd; + case 236 : itype = FR30BF_INSN_BLE; goto extract_fmt_bled; + case 237 : itype = FR30BF_INSN_BGT; goto extract_fmt_bled; + case 238 : itype = FR30BF_INSN_BLS; goto extract_fmt_blsd; + case 239 : itype = FR30BF_INSN_BHI; goto extract_fmt_blsd; + case 240 : itype = FR30BF_INSN_BRAD; goto extract_fmt_brad; + case 241 : itype = FR30BF_INSN_BNOD; goto extract_fmt_bnod; + case 242 : itype = FR30BF_INSN_BEQD; goto extract_fmt_beqd; + case 243 : itype = FR30BF_INSN_BNED; goto extract_fmt_beqd; + case 244 : itype = FR30BF_INSN_BCD; goto extract_fmt_bcd; + case 245 : itype = FR30BF_INSN_BNCD; goto extract_fmt_bcd; + case 246 : itype = FR30BF_INSN_BND; goto extract_fmt_bnd; + case 247 : itype = FR30BF_INSN_BPD; goto extract_fmt_bnd; + case 248 : itype = FR30BF_INSN_BVD; goto extract_fmt_bvd; + case 249 : itype = FR30BF_INSN_BNVD; goto extract_fmt_bvd; + case 250 : itype = FR30BF_INSN_BLTD; goto extract_fmt_bltd; + case 251 : itype = FR30BF_INSN_BGED; goto extract_fmt_bltd; + case 252 : itype = FR30BF_INSN_BLED; goto extract_fmt_bled; + case 253 : itype = FR30BF_INSN_BGTD; goto extract_fmt_bled; + case 254 : itype = FR30BF_INSN_BLSD; goto extract_fmt_blsd; + case 255 : itype = FR30BF_INSN_BHID; goto extract_fmt_blsd; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + } } -#undef I -#undef E } /* The instruction has been decoded, now extract the fields. */ - extract: - { -#ifndef __GNUC__ - switch (idecode->sfmt) -#endif - { - - CASE (ex, FMT_EMPTY) : + extract_fmt_empty: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_empty.f EXTRACT_IFMT_EMPTY_VARS /* */ @@ -680,11 +658,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADD) : + extract_fmt_add: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_add.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -706,11 +685,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDI) : + extract_fmt_addi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addi.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -731,11 +711,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADD2) : + extract_fmt_add2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_add2.f EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */ @@ -756,11 +737,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDC) : + extract_fmt_addc: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addc.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -782,11 +764,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDN) : + extract_fmt_addn: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addn.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -808,11 +791,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDNI) : + extract_fmt_addni: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addni.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -833,11 +817,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDN2) : + extract_fmt_addn2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addn2.f EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */ @@ -858,11 +843,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMP) : + extract_fmt_cmp: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmp.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -883,11 +869,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI) : + extract_fmt_cmpi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpi.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -907,11 +894,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMP2) : + extract_fmt_cmp2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmp2.f EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */ @@ -931,11 +919,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_AND) : + extract_fmt_and: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_and.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -957,11 +946,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDM) : + extract_fmt_andm: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andm.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -982,11 +972,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDH) : + extract_fmt_andh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1007,11 +998,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDB) : + extract_fmt_andb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1032,11 +1024,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BANDL) : + extract_fmt_bandl: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_bandl.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -1056,11 +1049,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BTSTL) : + extract_fmt_btstl: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_btstl.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -1080,11 +1074,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MUL) : + extract_fmt_mul: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mul.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1105,11 +1100,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULU) : + extract_fmt_mulu: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulu.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1130,11 +1126,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULH) : + extract_fmt_mulh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1155,11 +1152,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV0S) : + extract_fmt_div0s: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div0s.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1178,11 +1176,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV0U) : + extract_fmt_div0u: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div0u.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1193,11 +1192,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div0u", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV1) : + extract_fmt_div1: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div1.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1216,11 +1216,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV2) : + extract_fmt_div2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div2.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1239,11 +1240,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV3) : + extract_fmt_div3: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div3.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -1254,11 +1256,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div3", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV4S) : + extract_fmt_div4s: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div4s.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -1269,11 +1272,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div4s", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LSL) : + extract_fmt_lsl: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lsl.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1295,11 +1299,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LSLI) : + extract_fmt_lsli: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lsli.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -1320,11 +1325,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI8) : + extract_fmt_ldi8: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldi8.f EXTRACT_IFMT_LDI8_VARS /* f-op1 f-i8 f-Ri */ @@ -1344,11 +1350,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI20) : + extract_fmt_ldi20: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldi20.f EXTRACT_IFMT_LDI20_VARS /* f-op1 f-i20 f-op2 f-Ri */ @@ -1368,11 +1375,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI32) : + extract_fmt_ldi32: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldi32.f EXTRACT_IFMT_LDI32_VARS /* f-op1 f-i32 f-op2 f-op3 f-Ri */ @@ -1392,11 +1400,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD) : + extract_fmt_ld: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1417,11 +1426,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDUH) : + extract_fmt_lduh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lduh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1442,11 +1452,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDUB) : + extract_fmt_ldub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldub.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1467,11 +1478,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR13) : + extract_fmt_ldr13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr13.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1493,11 +1505,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR13UH) : + extract_fmt_ldr13uh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr13uh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1519,11 +1532,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR13UB) : + extract_fmt_ldr13ub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr13ub.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1545,11 +1559,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR14) : + extract_fmt_ldr14: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr14.f EXTRACT_IFMT_LDR14_VARS /* f-op1 f-disp10 f-Ri */ @@ -1570,11 +1585,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR14UH) : + extract_fmt_ldr14uh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr14uh.f EXTRACT_IFMT_LDR14UH_VARS /* f-op1 f-disp9 f-Ri */ @@ -1595,11 +1611,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR14UB) : + extract_fmt_ldr14ub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr14ub.f EXTRACT_IFMT_LDR14UB_VARS /* f-op1 f-disp8 f-Ri */ @@ -1620,11 +1637,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15) : + extract_fmt_ldr15: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15.f EXTRACT_IFMT_LDR15_VARS /* f-op1 f-op2 f-udisp6 f-Ri */ @@ -1645,11 +1663,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15GR) : + extract_fmt_ldr15gr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15gr.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1671,11 +1690,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15DR) : + extract_fmt_ldr15dr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15dr.f EXTRACT_IFMT_LDR15DR_VARS /* f-op1 f-op2 f-op3 f-Rs2 */ @@ -1695,11 +1715,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15PS) : + extract_fmt_ldr15ps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15ps.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -1718,11 +1739,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST) : + extract_fmt_st: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1743,11 +1765,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STH) : + extract_fmt_sth: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_sth.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1768,11 +1791,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STB) : + extract_fmt_stb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1793,11 +1817,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR13) : + extract_fmt_str13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str13.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1819,11 +1844,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR13H) : + extract_fmt_str13h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str13h.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1845,11 +1871,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR13B) : + extract_fmt_str13b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str13b.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1871,11 +1898,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR14) : + extract_fmt_str14: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str14.f EXTRACT_IFMT_LDR14_VARS /* f-op1 f-disp10 f-Ri */ @@ -1896,11 +1924,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR14H) : + extract_fmt_str14h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str14h.f EXTRACT_IFMT_LDR14UH_VARS /* f-op1 f-disp9 f-Ri */ @@ -1921,11 +1950,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR14B) : + extract_fmt_str14b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str14b.f EXTRACT_IFMT_LDR14UB_VARS /* f-op1 f-disp8 f-Ri */ @@ -1946,11 +1976,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15) : + extract_fmt_str15: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15.f EXTRACT_IFMT_LDR15_VARS /* f-op1 f-op2 f-udisp6 f-Ri */ @@ -1971,11 +2002,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15GR) : + extract_fmt_str15gr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15gr.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1996,11 +2028,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15DR) : + extract_fmt_str15dr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15dr.f EXTRACT_IFMT_LDR15DR_VARS /* f-op1 f-op2 f-op3 f-Rs2 */ @@ -2020,11 +2053,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15PS) : + extract_fmt_str15ps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15ps.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2043,11 +2077,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOV) : + extract_fmt_mov: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mov.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -2068,11 +2103,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVDR) : + extract_fmt_movdr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movdr.f EXTRACT_IFMT_MOVDR_VARS /* f-op1 f-op2 f-Rs1 f-Ri */ @@ -2092,11 +2128,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVPS) : + extract_fmt_movps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movps.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2115,11 +2152,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOV2DR) : + extract_fmt_mov2dr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mov2dr.f EXTRACT_IFMT_MOVDR_VARS /* f-op1 f-op2 f-Rs1 f-Ri */ @@ -2139,11 +2177,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOV2PS) : + extract_fmt_mov2ps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mov2ps.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2162,11 +2201,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_JMP) : + extract_fmt_jmp: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2186,11 +2226,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALLR) : + extract_fmt_callr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_callr.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2210,11 +2251,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALL) : + extract_fmt_call: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_call.f EXTRACT_IFMT_CALL_VARS /* f-op1 f-op5 f-rel12 */ @@ -2233,11 +2275,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RET) : + extract_fmt_ret: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_ret.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2255,11 +2298,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_INT) : + extract_fmt_int: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_int.f EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */ @@ -2278,11 +2322,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_INTE) : + extract_fmt_inte: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_inte.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2300,11 +2345,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RETI) : + extract_fmt_reti: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_reti.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2322,11 +2368,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BRAD) : + extract_fmt_brad: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_brad.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2345,11 +2392,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BNOD) : + extract_fmt_bnod: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_bnod.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2360,11 +2408,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bnod", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BEQD) : + extract_fmt_beqd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_beqd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2383,11 +2432,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BCD) : + extract_fmt_bcd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bcd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2406,11 +2456,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BND) : + extract_fmt_bnd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bnd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2429,11 +2480,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BVD) : + extract_fmt_bvd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bvd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2452,11 +2504,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BLTD) : + extract_fmt_bltd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bltd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2475,11 +2528,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BLED) : + extract_fmt_bled: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bled.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2498,11 +2552,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BLSD) : + extract_fmt_blsd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_blsd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2521,11 +2576,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13) : + extract_fmt_dmovr13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2544,11 +2600,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13H) : + extract_fmt_dmovr13h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13h.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2567,11 +2624,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13B) : + extract_fmt_dmovr13b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13b.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2590,11 +2648,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13PI) : + extract_fmt_dmovr13pi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13pi.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2614,11 +2673,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13PIH) : + extract_fmt_dmovr13pih: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13pih.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2638,11 +2698,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13PIB) : + extract_fmt_dmovr13pib: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13pib.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2662,11 +2723,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR15PI) : + extract_fmt_dmovr15pi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr15pi.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2686,11 +2748,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13) : + extract_fmt_dmov2r13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2709,11 +2772,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13H) : + extract_fmt_dmov2r13h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13h.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2732,11 +2796,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13B) : + extract_fmt_dmov2r13b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13b.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2755,11 +2820,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13PI) : + extract_fmt_dmov2r13pi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13pi.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2779,11 +2845,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13PIH) : + extract_fmt_dmov2r13pih: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13pih.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2803,11 +2870,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13PIB) : + extract_fmt_dmov2r13pib: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13pib.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2827,11 +2895,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R15PD) : + extract_fmt_dmov2r15pd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r15pd.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2851,11 +2920,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDRES) : + extract_fmt_ldres: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldres.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -2875,11 +2945,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_COPOP) : + extract_fmt_copop: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_copop.f EXTRACT_IFMT_COPOP_VARS /* f-op1 f-ccc f-op2 f-op3 f-CRj f-u4c f-CRi */ @@ -2890,11 +2961,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copop", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_COPLD) : + extract_fmt_copld: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_copld.f EXTRACT_IFMT_COPLD_VARS /* f-op1 f-ccc f-op2 f-op3 f-Rjc f-u4c f-CRi */ @@ -2905,11 +2977,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copld", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_COPST) : + extract_fmt_copst: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_copst.f EXTRACT_IFMT_COPST_VARS /* f-op1 f-ccc f-op2 f-op3 f-CRj f-u4c f-Ric */ @@ -2920,11 +2993,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copst", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOP) : + extract_fmt_nop: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_nop.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2935,11 +3009,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDCCR) : + extract_fmt_andccr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andccr.f EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */ @@ -2951,11 +3026,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andccr", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STILM) : + extract_fmt_stilm: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stilm.f EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */ @@ -2967,11 +3043,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stilm", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDSP) : + extract_fmt_addsp: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addsp.f EXTRACT_IFMT_ADDSP_VARS /* f-op1 f-op2 f-s10 */ @@ -2991,11 +3068,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTSB) : + extract_fmt_extsb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extsb.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3015,11 +3093,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTUB) : + extract_fmt_extub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extub.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3039,11 +3118,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTSH) : + extract_fmt_extsh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extsh.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3063,11 +3143,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTUH) : + extract_fmt_extuh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extuh.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3087,11 +3168,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDM0) : + extract_fmt_ldm0: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldm0.f EXTRACT_IFMT_LDM0_VARS /* f-op1 f-op2 f-reglist_low_ld */ @@ -3119,11 +3201,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDM1) : + extract_fmt_ldm1: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldm1.f EXTRACT_IFMT_LDM1_VARS /* f-op1 f-op2 f-reglist_hi_ld */ @@ -3150,11 +3233,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STM0) : + extract_fmt_stm0: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stm0.f EXTRACT_IFMT_STM0_VARS /* f-op1 f-op2 f-reglist_low_st */ @@ -3182,11 +3266,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STM1) : + extract_fmt_stm1: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stm1.f EXTRACT_IFMT_STM1_VARS /* f-op1 f-op2 f-reglist_hi_st */ @@ -3213,11 +3298,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ENTER) : + extract_fmt_enter: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_enter.f EXTRACT_IFMT_ENTER_VARS /* f-op1 f-op2 f-u10 */ @@ -3239,11 +3325,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LEAVE) : + extract_fmt_leave: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_leave.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -3264,11 +3351,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_XCHB) : + extract_fmt_xchb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_xchb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -3290,14 +3378,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); - } - - - } - ENDSWITCH (ex) - + return idesc; } - return idecode->idesc; } diff --git a/sim/fr30/devices.c b/sim/fr30/devices.c index f378a52..a3d47cf 100644 --- a/sim/fr30/devices.c +++ b/sim/fr30/devices.c @@ -31,10 +31,8 @@ device fr30_devices; int device_io_read_buffer (device *me, void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) return nr_bytes; @@ -69,10 +67,8 @@ device_io_read_buffer (device *me, void *source, int space, int device_io_write_buffer (device *me, const void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - #if WITH_SCACHE if (addr == MCCR_ADDR) { @@ -96,4 +92,7 @@ device_io_write_buffer (device *me, const void *source, int space, return nr_bytes; } -void device_error () {} +void +device_error (device *me, char *message, ...) +{ +} diff --git a/sim/fr30/fr30-sim.h b/sim/fr30/fr30-sim.h index b9018ef..dbb8117 100644 --- a/sim/fr30/fr30-sim.h +++ b/sim/fr30/fr30-sim.h @@ -33,33 +33,21 @@ with this program; if not, write to the Free Software Foundation, Inc., extern BI fr30bf_h_sbit_get_handler (SIM_CPU *); extern void fr30bf_h_sbit_set_handler (SIM_CPU *, BI); -#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu) -#define SET_H_SBIT(val) fr30bf_h_sbit_set_handler (current_cpu, (val)) extern UQI fr30bf_h_ccr_get_handler (SIM_CPU *); extern void fr30bf_h_ccr_set_handler (SIM_CPU *, UQI); -#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu) -#define SET_H_CCR(val) fr30bf_h_ccr_set_handler (current_cpu, (val)) extern UQI fr30bf_h_scr_get_handler (SIM_CPU *); extern void fr30bf_h_scr_set_handler (SIM_CPU *, UQI); -#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu) -#define SET_H_SCR(val) fr30bf_h_scr_set_handler (current_cpu, (val)) extern UQI fr30bf_h_ilm_get_handler (SIM_CPU *); extern void fr30bf_h_ilm_set_handler (SIM_CPU *, UQI); -#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu) -#define SET_H_ILM(val) fr30bf_h_ilm_set_handler (current_cpu, (val)) extern USI fr30bf_h_ps_get_handler (SIM_CPU *); extern void fr30bf_h_ps_set_handler (SIM_CPU *, USI); -#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu) -#define SET_H_PS(val) fr30bf_h_ps_set_handler (current_cpu, (val)) extern SI fr30bf_h_dr_get_handler (SIM_CPU *, UINT); extern void fr30bf_h_dr_set_handler (SIM_CPU *, UINT, SI); -#define GET_H_DR(regno) fr30bf_h_dr_get_handler (current_cpu, (regno)) -#define SET_H_DR(regno, val) fr30bf_h_dr_set_handler (current_cpu, (regno), (val)) #define GETTWI GETTSI #define SETTWI SETTSI diff --git a/sim/fr30/fr30.c b/sim/fr30/fr30.c index 78b9b7ce..5133654 100644 --- a/sim/fr30/fr30.c +++ b/sim/fr30/fr30.c @@ -48,15 +48,15 @@ int fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { if (rn < 16) - SETTWI (buf, a_fr30_h_gr_get (current_cpu, rn)); + SETTWI (buf, fr30bf_h_gr_get (current_cpu, rn)); else switch (rn) { case PC_REGNUM : - SETTWI (buf, a_fr30_h_pc_get (current_cpu)); + SETTWI (buf, fr30bf_h_pc_get (current_cpu)); break; case PS_REGNUM : - SETTWI (buf, a_fr30_h_ps_get (current_cpu)); + SETTWI (buf, fr30bf_h_ps_get (current_cpu)); break; case TBR_REGNUM : case RP_REGNUM : @@ -64,7 +64,7 @@ fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len case USP_REGNUM : case MDH_REGNUM : case MDL_REGNUM : - SETTWI (buf, a_fr30_h_dr_get (current_cpu, + SETTWI (buf, fr30bf_h_dr_get (current_cpu, decode_gdb_dr_regnum (rn))); break; default : @@ -80,15 +80,15 @@ int fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { if (rn < 16) - a_fr30_h_gr_set (current_cpu, rn, GETTWI (buf)); + fr30bf_h_gr_set (current_cpu, rn, GETTWI (buf)); else switch (rn) { case PC_REGNUM : - a_fr30_h_pc_set (current_cpu, GETTWI (buf)); + fr30bf_h_pc_set (current_cpu, GETTWI (buf)); break; case PS_REGNUM : - a_fr30_h_ps_set (current_cpu, GETTWI (buf)); + fr30bf_h_ps_set (current_cpu, GETTWI (buf)); break; case TBR_REGNUM : case RP_REGNUM : @@ -96,7 +96,7 @@ fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len case USP_REGNUM : case MDH_REGNUM : case MDL_REGNUM : - a_fr30_h_dr_set (current_cpu, + fr30bf_h_dr_set (current_cpu, decode_gdb_dr_regnum (rn), GETTWI (buf)); break; diff --git a/sim/fr30/model.c b/sim/fr30/model.c index 7be6305..a4d0714 100644 --- a/sim/fr30/model.c +++ b/sim/fr30/model.c @@ -3996,7 +3996,7 @@ fr30_init_cpu (SIM_CPU *cpu) const MACH fr30_mach = { - "fr30", "fr30", + "fr30", "fr30", MACH_FR30, 32, 32, & fr30_models[0], & fr30bf_imp_properties, fr30_init_cpu, fr30bf_prepare_run diff --git a/sim/fr30/sem-switch.c b/sim/fr30/sem-switch.c index 86950b2..ace4bca 100644 --- a/sim/fr30/sem-switch.c +++ b/sim/fr30/sem-switch.c @@ -403,7 +403,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -419,7 +419,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -430,8 +430,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -446,7 +446,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0); CPU (h_vbit) = opval; @@ -462,7 +462,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -473,8 +473,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -489,7 +489,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0); CPU (h_vbit) = opval; @@ -505,7 +505,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -516,8 +516,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -532,7 +532,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -550,7 +550,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -561,8 +561,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -634,7 +634,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -650,7 +650,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -661,8 +661,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -677,7 +677,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -695,7 +695,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -706,8 +706,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -741,7 +741,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); @@ -754,7 +754,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -765,8 +765,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -781,7 +781,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0); @@ -794,7 +794,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -805,8 +805,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -821,7 +821,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0); @@ -834,7 +834,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -845,8 +845,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -861,13 +861,13 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -878,8 +878,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -894,13 +894,13 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -911,8 +911,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -927,13 +927,13 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -944,8 +944,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -960,10 +960,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -974,13 +974,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -995,10 +995,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1009,13 +1009,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1030,10 +1030,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1044,13 +1044,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1065,10 +1065,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1079,13 +1079,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1100,10 +1100,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1114,13 +1114,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1135,10 +1135,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1149,13 +1149,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1170,10 +1170,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1184,13 +1184,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1205,10 +1205,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1219,13 +1219,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1240,10 +1240,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1254,13 +1254,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1389,7 +1389,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1402,7 +1402,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1417,7 +1417,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1430,7 +1430,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1445,7 +1445,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri))); { @@ -1473,7 +1473,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1488,7 +1488,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri))); { @@ -1516,7 +1516,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1531,7 +1531,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri))); SET_H_DR (((UINT) 5), opval); @@ -1547,7 +1547,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1562,7 +1562,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535)); SET_H_DR (((UINT) 5), opval); @@ -1578,7 +1578,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1593,7 +1593,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = LTSI (GET_H_DR (((UINT) 5)), 0); CPU (h_d0bit) = opval; @@ -1619,7 +1619,7 @@ if (NEBI (CPU (h_d0bit), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -1635,7 +1635,7 @@ if (NEBI (CPU (h_d0bit), 0)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = 0; CPU (h_d0bit) = opval; @@ -1651,7 +1651,7 @@ do { SET_H_DR (((UINT) 4), opval); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} #undef FLD } @@ -1666,7 +1666,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; { SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1); @@ -1686,7 +1686,7 @@ if (LTSI (GET_H_DR (((UINT) 5)), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1694,9 +1694,9 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1704,10 +1704,10 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) { -do { +{ { SI opval = tmp_tmp; SET_H_DR (((UINT) 4), opval); @@ -1718,14 +1718,14 @@ do { SET_H_DR (((UINT) 5), opval); TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } -} while (0); +} } { BI opval = EQSI (GET_H_DR (((UINT) 4)), 0); CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -1741,10 +1741,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1752,9 +1752,9 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1762,10 +1762,10 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (EQSI (tmp_tmp, 0)) { -do { +{ { BI opval = 1; CPU (h_zbit) = opval; @@ -1778,7 +1778,7 @@ do { written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1787,7 +1787,7 @@ do { TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -1849,11 +1849,11 @@ if (EQBI (CPU (h_d1bit), 1)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1866,7 +1866,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1885,7 +1885,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -1901,11 +1901,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1918,7 +1918,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1937,7 +1937,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -1953,11 +1953,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1970,7 +1970,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1989,7 +1989,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2005,11 +2005,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2022,7 +2022,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2041,7 +2041,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2057,11 +2057,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2074,7 +2074,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2093,7 +2093,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2109,11 +2109,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2126,7 +2126,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2145,7 +2145,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2161,11 +2161,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2178,7 +2178,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2197,7 +2197,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2213,11 +2213,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2230,7 +2230,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2249,7 +2249,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2265,11 +2265,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2282,7 +2282,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2301,7 +2301,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2564,7 +2564,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); * FLD (i_Ri) = opval; @@ -2578,7 +2578,7 @@ if (NESI (FLD (f_Ri), 15)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -2594,7 +2594,7 @@ if (NESI (FLD (f_Ri), 15)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); { @@ -2607,7 +2607,7 @@ do { SET_H_DR (FLD (f_Rs2), opval); TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval); } -} while (0); +} #undef FLD } @@ -2622,7 +2622,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SET_H_PS (opval); @@ -2633,7 +2633,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} #undef FLD } @@ -2838,7 +2838,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -2851,7 +2851,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -2866,7 +2866,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GET_H_DR (FLD (f_Rs2)); { @@ -2879,7 +2879,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -2894,7 +2894,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -2905,7 +2905,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -3037,13 +3037,13 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = * FLD (i_Ri); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3060,7 +3060,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3071,7 +3071,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3088,8 +3088,8 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3100,8 +3100,8 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3118,7 +3118,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3129,7 +3129,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3146,8 +3146,8 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3158,8 +3158,8 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3197,13 +3197,13 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GET_H_DR (((UINT) 1)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3220,7 +3220,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3229,7 +3229,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3246,7 +3246,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3255,7 +3255,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3273,7 +3273,7 @@ do { vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (EQBI (GET_H_SBIT (), 0)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3298,9 +3298,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval); } -} while (0); +} } else { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3325,7 +3325,7 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval); } -} while (0); +} } abuf->written = written; @@ -3344,13 +3344,13 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = FLD (i_label9); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3387,9 +3387,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ do { } while (0); /*nop*/ -} while (0); +} #undef FLD } @@ -3420,7 +3420,7 @@ do { } while (0); /*nop*/ SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_zbit)) { { USI opval = FLD (i_label9); @@ -3429,7 +3429,7 @@ if (CPU (h_zbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3472,7 +3472,7 @@ if (CPU (h_zbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3481,7 +3481,7 @@ if (NOTBI (CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3524,7 +3524,7 @@ if (NOTBI (CPU (h_zbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_cbit)) { { USI opval = FLD (i_label9); @@ -3533,7 +3533,7 @@ if (CPU (h_cbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3576,7 +3576,7 @@ if (CPU (h_cbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); @@ -3585,7 +3585,7 @@ if (NOTBI (CPU (h_cbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3628,7 +3628,7 @@ if (NOTBI (CPU (h_cbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_nbit)) { { USI opval = FLD (i_label9); @@ -3637,7 +3637,7 @@ if (CPU (h_nbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3680,7 +3680,7 @@ if (CPU (h_nbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3689,7 +3689,7 @@ if (NOTBI (CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3732,7 +3732,7 @@ if (NOTBI (CPU (h_nbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_vbit)) { { USI opval = FLD (i_label9); @@ -3741,7 +3741,7 @@ if (CPU (h_vbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3784,7 +3784,7 @@ if (CPU (h_vbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); @@ -3793,7 +3793,7 @@ if (NOTBI (CPU (h_vbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3836,7 +3836,7 @@ if (NOTBI (CPU (h_vbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3845,7 +3845,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3888,7 +3888,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); @@ -3897,7 +3897,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3940,7 +3940,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3949,7 +3949,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3992,7 +3992,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4001,7 +4001,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4044,7 +4044,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -4053,7 +4053,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4096,7 +4096,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4105,7 +4105,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4204,7 +4204,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4215,7 +4215,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4230,7 +4230,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMHI (current_cpu, pc, FLD (f_dir9), opval); @@ -4241,7 +4241,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4256,7 +4256,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMQI (current_cpu, pc, FLD (f_dir8), opval); @@ -4267,7 +4267,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4282,7 +4282,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4293,7 +4293,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} #undef FLD } @@ -4365,7 +4365,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10)); SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4376,7 +4376,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4391,7 +4391,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9)); SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4402,7 +4402,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4417,7 +4417,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8)); SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4428,7 +4428,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4443,7 +4443,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -4454,7 +4454,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4734,9 +4734,9 @@ do { } while (0); /*nop*/ IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 0)]) = opval; @@ -4749,10 +4749,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 1)]) = opval; @@ -4765,10 +4765,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 2)]) = opval; @@ -4781,10 +4781,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 3)]) = opval; @@ -4797,10 +4797,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 4)]) = opval; @@ -4813,10 +4813,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 5)]) = opval; @@ -4829,10 +4829,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 6)]) = opval; @@ -4845,10 +4845,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 128)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 7)]) = opval; @@ -4861,9 +4861,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; #undef FLD @@ -4879,9 +4879,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 8)]) = opval; @@ -4894,10 +4894,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 9)]) = opval; @@ -4910,10 +4910,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 10)]) = opval; @@ -4926,10 +4926,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 11)]) = opval; @@ -4942,10 +4942,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 12)]) = opval; @@ -4958,10 +4958,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 13)]) = opval; @@ -4974,10 +4974,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 14)]) = opval; @@ -4990,7 +4990,7 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 128)) { { @@ -5000,7 +5000,7 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -5016,9 +5016,9 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_st), 1)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5031,10 +5031,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5047,10 +5047,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5063,10 +5063,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5079,10 +5079,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5095,10 +5095,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5111,10 +5111,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5127,10 +5127,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5143,9 +5143,9 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; #undef FLD @@ -5161,9 +5161,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_st), 1)) { -do { +{ SI tmp_save_r15; tmp_save_r15 = CPU (h_gr[((UINT) 15)]); { @@ -5178,10 +5178,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5194,10 +5194,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5210,10 +5210,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5226,10 +5226,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5242,10 +5242,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5258,10 +5258,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5274,10 +5274,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5290,9 +5290,9 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; #undef FLD @@ -5308,7 +5308,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4); { @@ -5326,7 +5326,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} #undef FLD } @@ -5341,7 +5341,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5352,7 +5352,7 @@ do { CPU (h_gr[((UINT) 14)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); } -} while (0); +} #undef FLD } @@ -5367,7 +5367,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -5380,7 +5380,7 @@ do { SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } diff --git a/sim/fr30/sem.c b/sim/fr30/sem.c index 8224c33..e35c421 100644 --- a/sim/fr30/sem.c +++ b/sim/fr30/sem.c @@ -191,7 +191,7 @@ SEM_FN_NAME (fr30bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -207,7 +207,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -218,8 +218,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -236,7 +236,7 @@ SEM_FN_NAME (fr30bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0); CPU (h_vbit) = opval; @@ -252,7 +252,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -263,8 +263,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -281,7 +281,7 @@ SEM_FN_NAME (fr30bf,add2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0); CPU (h_vbit) = opval; @@ -297,7 +297,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -308,8 +308,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -326,7 +326,7 @@ SEM_FN_NAME (fr30bf,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -344,7 +344,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -355,8 +355,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -436,7 +436,7 @@ SEM_FN_NAME (fr30bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -452,7 +452,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -463,8 +463,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -481,7 +481,7 @@ SEM_FN_NAME (fr30bf,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -499,7 +499,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -510,8 +510,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -549,7 +549,7 @@ SEM_FN_NAME (fr30bf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); @@ -562,7 +562,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -573,8 +573,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -591,7 +591,7 @@ SEM_FN_NAME (fr30bf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0); @@ -604,7 +604,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -615,8 +615,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -633,7 +633,7 @@ SEM_FN_NAME (fr30bf,cmp2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0); @@ -646,7 +646,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -657,8 +657,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -675,13 +675,13 @@ SEM_FN_NAME (fr30bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -692,8 +692,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -710,13 +710,13 @@ SEM_FN_NAME (fr30bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -727,8 +727,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -745,13 +745,13 @@ SEM_FN_NAME (fr30bf,eor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -762,8 +762,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -780,10 +780,10 @@ SEM_FN_NAME (fr30bf,andm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -794,13 +794,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -817,10 +817,10 @@ SEM_FN_NAME (fr30bf,andh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -831,13 +831,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -854,10 +854,10 @@ SEM_FN_NAME (fr30bf,andb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -868,13 +868,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -891,10 +891,10 @@ SEM_FN_NAME (fr30bf,orm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -905,13 +905,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -928,10 +928,10 @@ SEM_FN_NAME (fr30bf,orh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -942,13 +942,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -965,10 +965,10 @@ SEM_FN_NAME (fr30bf,orb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -979,13 +979,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1002,10 +1002,10 @@ SEM_FN_NAME (fr30bf,eorm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1016,13 +1016,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1039,10 +1039,10 @@ SEM_FN_NAME (fr30bf,eorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1053,13 +1053,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1076,10 +1076,10 @@ SEM_FN_NAME (fr30bf,eorb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1090,13 +1090,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1239,7 +1239,7 @@ SEM_FN_NAME (fr30bf,btstl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1252,7 +1252,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1269,7 +1269,7 @@ SEM_FN_NAME (fr30bf,btsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1282,7 +1282,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1299,7 +1299,7 @@ SEM_FN_NAME (fr30bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri))); { @@ -1327,7 +1327,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1344,7 +1344,7 @@ SEM_FN_NAME (fr30bf,mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri))); { @@ -1372,7 +1372,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1389,7 +1389,7 @@ SEM_FN_NAME (fr30bf,mulh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri))); SET_H_DR (((UINT) 5), opval); @@ -1405,7 +1405,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1422,7 +1422,7 @@ SEM_FN_NAME (fr30bf,muluh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535)); SET_H_DR (((UINT) 5), opval); @@ -1438,7 +1438,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1455,7 +1455,7 @@ SEM_FN_NAME (fr30bf,div0s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = LTSI (GET_H_DR (((UINT) 5)), 0); CPU (h_d0bit) = opval; @@ -1481,7 +1481,7 @@ if (NEBI (CPU (h_d0bit), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -1499,7 +1499,7 @@ SEM_FN_NAME (fr30bf,div0u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = 0; CPU (h_d0bit) = opval; @@ -1515,7 +1515,7 @@ do { SET_H_DR (((UINT) 4), opval); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1532,7 +1532,7 @@ SEM_FN_NAME (fr30bf,div1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; { SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1); @@ -1552,7 +1552,7 @@ if (LTSI (GET_H_DR (((UINT) 5)), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1560,9 +1560,9 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1570,10 +1570,10 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) { -do { +{ { SI opval = tmp_tmp; SET_H_DR (((UINT) 4), opval); @@ -1584,14 +1584,14 @@ do { SET_H_DR (((UINT) 5), opval); TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } -} while (0); +} } { BI opval = EQSI (GET_H_DR (((UINT) 4)), 0); CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1609,10 +1609,10 @@ SEM_FN_NAME (fr30bf,div2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1620,9 +1620,9 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1630,10 +1630,10 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (EQSI (tmp_tmp, 0)) { -do { +{ { BI opval = 1; CPU (h_zbit) = opval; @@ -1646,7 +1646,7 @@ do { written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1655,7 +1655,7 @@ do { TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -1723,11 +1723,11 @@ SEM_FN_NAME (fr30bf,lsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1740,7 +1740,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1759,7 +1759,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1777,11 +1777,11 @@ SEM_FN_NAME (fr30bf,lsli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1794,7 +1794,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1813,7 +1813,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1831,11 +1831,11 @@ SEM_FN_NAME (fr30bf,lsl2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1848,7 +1848,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1867,7 +1867,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1885,11 +1885,11 @@ SEM_FN_NAME (fr30bf,lsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -1902,7 +1902,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1921,7 +1921,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1939,11 +1939,11 @@ SEM_FN_NAME (fr30bf,lsri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -1956,7 +1956,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1975,7 +1975,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1993,11 +1993,11 @@ SEM_FN_NAME (fr30bf,lsr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2010,7 +2010,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2029,7 +2029,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2047,11 +2047,11 @@ SEM_FN_NAME (fr30bf,asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2064,7 +2064,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2083,7 +2083,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2101,11 +2101,11 @@ SEM_FN_NAME (fr30bf,asri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2118,7 +2118,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2137,7 +2137,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2155,11 +2155,11 @@ SEM_FN_NAME (fr30bf,asr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2172,7 +2172,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2191,7 +2191,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2482,7 +2482,7 @@ SEM_FN_NAME (fr30bf,ldr15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); * FLD (i_Ri) = opval; @@ -2496,7 +2496,7 @@ if (NESI (FLD (f_Ri), 15)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -2514,7 +2514,7 @@ SEM_FN_NAME (fr30bf,ldr15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); { @@ -2527,7 +2527,7 @@ do { SET_H_DR (FLD (f_Rs2), opval); TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2544,7 +2544,7 @@ SEM_FN_NAME (fr30bf,ldr15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SET_H_PS (opval); @@ -2555,7 +2555,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2782,7 +2782,7 @@ SEM_FN_NAME (fr30bf,str15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -2795,7 +2795,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2812,7 +2812,7 @@ SEM_FN_NAME (fr30bf,str15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GET_H_DR (FLD (f_Rs2)); { @@ -2825,7 +2825,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2842,7 +2842,7 @@ SEM_FN_NAME (fr30bf,str15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -2853,7 +2853,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2999,13 +2999,13 @@ SEM_FN_NAME (fr30bf,jmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = * FLD (i_Ri); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3024,7 +3024,7 @@ SEM_FN_NAME (fr30bf,callr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3035,7 +3035,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3054,8 +3054,8 @@ SEM_FN_NAME (fr30bf,callrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3066,8 +3066,8 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3086,7 +3086,7 @@ SEM_FN_NAME (fr30bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3097,7 +3097,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3116,8 +3116,8 @@ SEM_FN_NAME (fr30bf,calld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3128,8 +3128,8 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3171,13 +3171,13 @@ SEM_FN_NAME (fr30bf,ret_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GET_H_DR (((UINT) 1)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3196,7 +3196,7 @@ SEM_FN_NAME (fr30bf,int) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3205,7 +3205,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3224,7 +3224,7 @@ SEM_FN_NAME (fr30bf,inte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3233,7 +3233,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3253,7 +3253,7 @@ SEM_FN_NAME (fr30bf,reti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (EQBI (GET_H_SBIT (), 0)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3278,9 +3278,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval); } -} while (0); +} } else { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3305,7 +3305,7 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval); } -} while (0); +} } abuf->written = written; @@ -3326,13 +3326,13 @@ SEM_FN_NAME (fr30bf,brad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = FLD (i_label9); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3373,9 +3373,9 @@ SEM_FN_NAME (fr30bf,bnod) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ do { } while (0); /*nop*/ -} while (0); +} return vpc; #undef FLD @@ -3410,7 +3410,7 @@ SEM_FN_NAME (fr30bf,beqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_zbit)) { { USI opval = FLD (i_label9); @@ -3419,7 +3419,7 @@ if (CPU (h_zbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3466,7 +3466,7 @@ SEM_FN_NAME (fr30bf,bned) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3475,7 +3475,7 @@ if (NOTBI (CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3522,7 +3522,7 @@ SEM_FN_NAME (fr30bf,bcd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_cbit)) { { USI opval = FLD (i_label9); @@ -3531,7 +3531,7 @@ if (CPU (h_cbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3578,7 +3578,7 @@ SEM_FN_NAME (fr30bf,bncd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); @@ -3587,7 +3587,7 @@ if (NOTBI (CPU (h_cbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3634,7 +3634,7 @@ SEM_FN_NAME (fr30bf,bnd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_nbit)) { { USI opval = FLD (i_label9); @@ -3643,7 +3643,7 @@ if (CPU (h_nbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3690,7 +3690,7 @@ SEM_FN_NAME (fr30bf,bpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3699,7 +3699,7 @@ if (NOTBI (CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3746,7 +3746,7 @@ SEM_FN_NAME (fr30bf,bvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_vbit)) { { USI opval = FLD (i_label9); @@ -3755,7 +3755,7 @@ if (CPU (h_vbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3802,7 +3802,7 @@ SEM_FN_NAME (fr30bf,bnvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); @@ -3811,7 +3811,7 @@ if (NOTBI (CPU (h_vbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3858,7 +3858,7 @@ SEM_FN_NAME (fr30bf,bltd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3867,7 +3867,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3914,7 +3914,7 @@ SEM_FN_NAME (fr30bf,bged) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); @@ -3923,7 +3923,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3970,7 +3970,7 @@ SEM_FN_NAME (fr30bf,bled) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3979,7 +3979,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4026,7 +4026,7 @@ SEM_FN_NAME (fr30bf,bgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4035,7 +4035,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4082,7 +4082,7 @@ SEM_FN_NAME (fr30bf,blsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -4091,7 +4091,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4138,7 +4138,7 @@ SEM_FN_NAME (fr30bf,bhid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4147,7 +4147,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4256,7 +4256,7 @@ SEM_FN_NAME (fr30bf,dmovr13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4267,7 +4267,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4284,7 +4284,7 @@ SEM_FN_NAME (fr30bf,dmovr13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMHI (current_cpu, pc, FLD (f_dir9), opval); @@ -4295,7 +4295,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4312,7 +4312,7 @@ SEM_FN_NAME (fr30bf,dmovr13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMQI (current_cpu, pc, FLD (f_dir8), opval); @@ -4323,7 +4323,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4340,7 +4340,7 @@ SEM_FN_NAME (fr30bf,dmovr15pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4351,7 +4351,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4431,7 +4431,7 @@ SEM_FN_NAME (fr30bf,dmov2r13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10)); SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4442,7 +4442,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4459,7 +4459,7 @@ SEM_FN_NAME (fr30bf,dmov2r13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9)); SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4470,7 +4470,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4487,7 +4487,7 @@ SEM_FN_NAME (fr30bf,dmov2r13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8)); SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4498,7 +4498,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4515,7 +4515,7 @@ SEM_FN_NAME (fr30bf,dmov2r15pd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -4526,7 +4526,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4838,9 +4838,9 @@ SEM_FN_NAME (fr30bf,ldm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 0)]) = opval; @@ -4853,10 +4853,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 1)]) = opval; @@ -4869,10 +4869,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 2)]) = opval; @@ -4885,10 +4885,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 3)]) = opval; @@ -4901,10 +4901,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 4)]) = opval; @@ -4917,10 +4917,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 5)]) = opval; @@ -4933,10 +4933,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 6)]) = opval; @@ -4949,10 +4949,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 128)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 7)]) = opval; @@ -4965,9 +4965,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; return vpc; @@ -4985,9 +4985,9 @@ SEM_FN_NAME (fr30bf,ldm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 8)]) = opval; @@ -5000,10 +5000,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 9)]) = opval; @@ -5016,10 +5016,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 10)]) = opval; @@ -5032,10 +5032,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 11)]) = opval; @@ -5048,10 +5048,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 12)]) = opval; @@ -5064,10 +5064,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 13)]) = opval; @@ -5080,10 +5080,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 14)]) = opval; @@ -5096,7 +5096,7 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 128)) { { @@ -5106,7 +5106,7 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -5124,9 +5124,9 @@ SEM_FN_NAME (fr30bf,stm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_st), 1)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5139,10 +5139,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5155,10 +5155,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5171,10 +5171,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5187,10 +5187,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5203,10 +5203,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5219,10 +5219,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5235,10 +5235,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5251,9 +5251,9 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; return vpc; @@ -5271,9 +5271,9 @@ SEM_FN_NAME (fr30bf,stm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_st), 1)) { -do { +{ SI tmp_save_r15; tmp_save_r15 = CPU (h_gr[((UINT) 15)]); { @@ -5288,10 +5288,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5304,10 +5304,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5320,10 +5320,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5336,10 +5336,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5352,10 +5352,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5368,10 +5368,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5384,10 +5384,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5400,9 +5400,9 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; return vpc; @@ -5420,7 +5420,7 @@ SEM_FN_NAME (fr30bf,enter) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4); { @@ -5438,7 +5438,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5455,7 +5455,7 @@ SEM_FN_NAME (fr30bf,leave) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5466,7 +5466,7 @@ do { CPU (h_gr[((UINT) 14)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5483,7 +5483,7 @@ SEM_FN_NAME (fr30bf,xchb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -5496,7 +5496,7 @@ do { SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD diff --git a/sim/fr30/sim-if.c b/sim/fr30/sim-if.c index 5df0f83..28b344d 100644 --- a/sim/fr30/sim-if.c +++ b/sim/fr30/sim-if.c @@ -143,8 +143,8 @@ sim_open (kind, callback, abfd, argv) /* Open a copy of the cpu descriptor table. */ { - CGEN_CPU_DESC cd = fr30_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach, - CGEN_ENDIAN_BIG); + CGEN_CPU_DESC cd = fr30_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, + CGEN_ENDIAN_BIG); for (i = 0; i < MAX_NR_PROCESSORS; ++i) { SIM_CPU *cpu = STATE_CPU (sd, i); diff --git a/sim/fr30/traps.c b/sim/fr30/traps.c index 599bca2..11f7a30 100644 --- a/sim/fr30/traps.c +++ b/sim/fr30/traps.c @@ -104,15 +104,15 @@ syscall_write_mem (host_callback *cb, struct cb_syscall *sc, static void setup_int (SIM_CPU *current_cpu, PCADDR pc) { - USI ssp = a_fr30_h_dr_get (current_cpu, H_DR_SSP); - USI ps = a_fr30_h_ps_get (current_cpu); + USI ssp = fr30bf_h_dr_get (current_cpu, H_DR_SSP); + USI ps = fr30bf_h_ps_get (current_cpu); ssp -= 4; SETMEMSI (current_cpu, pc, ssp, ps); ssp -= 4; SETMEMSI (current_cpu, pc, ssp, pc + 2); - a_fr30_h_dr_set (current_cpu, H_DR_SSP, ssp); - a_fr30_h_sbit_set (current_cpu, 0); + fr30bf_h_dr_set (current_cpu, H_DR_SSP, ssp); + fr30bf_h_sbit_set (current_cpu, 0); } /* Trap support. @@ -143,9 +143,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) We assume there's a branch there to some handler. */ USI new_pc; setup_int (current_cpu, pc); - a_fr30_h_ibit_set (current_cpu, 0); + fr30bf_h_ibit_set (current_cpu, 0); new_pc = GETMEMSI (current_cpu, pc, - a_fr30_h_dr_get (current_cpu, H_DR_TBR) + fr30bf_h_dr_get (current_cpu, H_DR_TBR) + 1024 - ((num + 1) * 4)); return new_pc; } @@ -158,10 +158,10 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) CB_SYSCALL s; CB_SYSCALL_INIT (&s); - s.func = a_fr30_h_gr_get (current_cpu, 0); - s.arg1 = a_fr30_h_gr_get (current_cpu, 4); - s.arg2 = a_fr30_h_gr_get (current_cpu, 5); - s.arg3 = a_fr30_h_gr_get (current_cpu, 6); + s.func = fr30bf_h_gr_get (current_cpu, 0); + s.arg1 = fr30bf_h_gr_get (current_cpu, 4); + s.arg2 = fr30bf_h_gr_get (current_cpu, 5); + s.arg3 = fr30bf_h_gr_get (current_cpu, 6); if (s.func == TARGET_SYS_exit) { @@ -173,9 +173,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) s.read_mem = syscall_read_mem; s.write_mem = syscall_write_mem; cb_syscall (cb, &s); - a_fr30_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */ - a_fr30_h_gr_set (current_cpu, 4, s.result); - a_fr30_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */ + fr30bf_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */ + fr30bf_h_gr_set (current_cpu, 4, s.result); + fr30bf_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */ break; } @@ -188,9 +188,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) { USI new_pc; setup_int (current_cpu, pc); - a_fr30_h_ibit_set (current_cpu, 0); + fr30bf_h_ibit_set (current_cpu, 0); new_pc = GETMEMSI (current_cpu, pc, - a_fr30_h_dr_get (current_cpu, H_DR_TBR) + fr30bf_h_dr_get (current_cpu, H_DR_TBR) + 1024 - ((num + 1) * 4)); return new_pc; } @@ -209,9 +209,9 @@ fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num) We assume there's a branch there to some handler. */ USI new_pc; setup_int (current_cpu, pc); - a_fr30_h_ilm_set (current_cpu, 4); + fr30bf_h_ilm_set (current_cpu, 4); new_pc = GETMEMSI (current_cpu, pc, - a_fr30_h_dr_get (current_cpu, H_DR_TBR) + fr30bf_h_dr_get (current_cpu, H_DR_TBR) + 1024 - ((9 + 1) * 4)); return new_pc; } diff --git a/sim/h8300/ChangeLog b/sim/h8300/ChangeLog index 0071781..f058ca9 100644 --- a/sim/h8300/ChangeLog +++ b/sim/h8300/ChangeLog @@ -1,3 +1,9 @@ +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * compile.c (POLL_QUIT_INTERVAL): Define. Used to tweak the + frequency at which the poll_quit callback is used. + (sim_resume): Use POLL_QUIT_INTERVAL instead of hard-coded value. + Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index 0e1fd9c..2ec759d 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -74,6 +74,10 @@ void sim_set_simcache_size PARAMS ((int)); #include "inst.h" +/* The rate at which to call the host's poll_quit callback. */ + +#define POLL_QUIT_INTERVAL 0x80000 + #define LOW_BYTE(x) ((x) & 0xff) #define HIGH_BYTE(x) (((x)>>8) & 0xff) #define P(X,Y) ((X<<8) | Y) @@ -1726,7 +1730,7 @@ sim_resume (sd, step, siggnal) if (--poll_count < 0) { - poll_count = 100; + poll_count = POLL_QUIT_INTERVAL; if ((*sim_callback->poll_quit) != NULL && (*sim_callback->poll_quit) (sim_callback)) sim_stop (sd); diff --git a/sim/i960/ChangeLog b/sim/i960/ChangeLog index 5a87da5..837233c 100644 --- a/sim/i960/ChangeLog +++ b/sim/i960/ChangeLog @@ -1,3 +1,51 @@ +Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com> + + * devices.c (device_io_read_buffer): New arg `sd'. + (device_io_write_buffer): New arg `sd'. + (device_error): Give proper arg spec. + +1999-04-14 Doug Evans <devans@casey.cygnus.com> + + * i960-desc.c,i960-desc.h: Rebuild. + +Sun Apr 11 00:25:17 1999 Jim Wilson <wilson@cygnus.com> + + * TODO: Document more toolchain problems. + * cpu.h, decode.c, model.c, sem-switch.c, sem.c: Rebuild. + +1999-04-10 Doug Evans <devans@casey.cygnus.com> + + * cpu.h,decode.c,sem-switch.c,sem.c: Rebuild. + +Fri Apr 9 19:30:05 1999 Jim Wilson <wilson@cygnus.com> + + * README, TODO: Clean up and update. + * sim-if.c: s/m32r/i960. s/sparc32/i960. + * decode.c, decode.h, i960-desc.c, i960-desc.h, i960-opc.h, model.c, + sem-switch.c, sem.c: Rebuild. + +1999-03-27 Doug Evans <devans@casey.cygnus.com> + + * decode.c: Rebuild. + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,model.c,i960-desc.c,i960-desc.h,i960-opc.h: Rebuild. + * i960-sim.h (a_i960_h_gr_get,a_i960_h_gr_set): Declare. + (a_i960_h_pc_get,a_i960_h_pc_set): Declare. + * i960.c (a_i960_h_gr_get,a_i960_h_gr_set): New functions. + (a_i960_h_pc_get,a_i960_h_pc_set): Ditto. + * sim-if.c (sim_open): Update call to i960_cgen_cpu_open. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,cpu.c,i960-desc.c,i960-desc.h: Rebuild. + * sim-if.c (sim_open): Update call to i960_cgen_cpu_open. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * i960-desc.c,i960-desc.h: Rebuild. + 1999-02-09 Doug Evans <devans@casey.cygnus.com> * Makefile.in (I960_OBJS): Add i960-desc.o. diff --git a/sim/i960/README b/sim/i960/README index f337558..6d38a40 100644 --- a/sim/i960/README +++ b/sim/i960/README @@ -1,9 +1,18 @@ This is the i960 simulator directory. -It is still work-in-progress. The current sources are reasonably +It is still a work in progress. The current sources are reasonably well tested and lots of features are in. However, there's lots more yet to come. +--- + +The simulator only supports the i960KA currently. Not all instructions +are supported yet, only those instructions needed by the gcc/g++ testsuites +have been added so far. There is no profiling support as yet. There is +no pipeline or timing support as yet. + +--- + There are lots of machine generated files in the source directory! They are only generated if you configure with --enable-cgen-maint, similar in behaviour to Makefile.in, configure under automake/autoconf. diff --git a/sim/i960/TODO b/sim/i960/TODO index 263daac..5e156b1 100644 --- a/sim/i960/TODO +++ b/sim/i960/TODO @@ -1,9 +1,64 @@ -- header file dependencies revisit -- hooks cleanup -- testsuites -- FIXME's -- memory accesses still test if profiling is on even in fast mode -- fill nop counting done even in fast mode -- have semantic code use G/SET_H_FOO if not default [incl fun-access] -- have G/SET_H_FOO macros call function if fun-access -- --> can always use G/S_H_FOO macros +See ??? comments here and in cgen, and in libgloss/i960. + +Simulator: + +Update sim/i960 directory from sim/m32r directory. sim/i960 dir was created +by copying the sim/m32r in September 1998, and is missing all sim/m32r updates +since then. + +Review, clean up, finish, etc simulator files that are not cgen generated. +This includes devices.c, i960-sim.h, mloop.in, sim-if.c, sim-main.h, +tconfig.in, and traps.c. + +Some functions do not show up in trace output. This occasionally happens +for main. + +Gdb core dumps if compile without -mka. Apparently a problem with recognizing +"core" machine type. + +Get profiling working. + +Add pipelining, execution unit, timing, etc info. + +Add support for other models, besides KA. + +Add support for newer architectures, e.g. v1.1 instructions. + +Compiler: + +Running gcc gives nm warning from collect about missing a.out file. +The output file is b.out, not a.out. Collect is probably looking for +the wrong file name. + +Use of -mca gives lots of linker warnings for ka/ca architecture conflicts, +but the two architectures are compatible. + +Need 96 bit long double support in fp-bit.c, otherwise any testcase using +long double arithmetic hits an abort and runtime. + +Compiler takes far too much time to compile PlumHall testcases at high +optimization levels. + +r2 seems to be an available call-clobbered registers, since it isn't used +until a call occurs, and is dead when the call returns. + +BSP: + +Libgloss does not check for syscall error returns, which means errno never +gets set. + +Libgloss does not use the syscall.h file. + +Binutils: + +Objdump -d fails on 64-bit host, specifically irix6. + +Gdb: + +Gdb sometimes prints messages about trace/breakpoint trap when hitting a +breakpoint. + +Frame, up, down and related commands don't work. + +Gdb fails when next'ing over a leaf function compiled with -mleaf-procedure. +Gdb fails when step'ing over a return from such a leaf function. diff --git a/sim/i960/arch.c b/sim/i960/arch.c index 5d3ab84..74833b0 100644 --- a/sim/i960/arch.c +++ b/sim/i960/arch.c @@ -36,129 +36,3 @@ const MACH *sim_machs[] = 0 }; -/* Get the value of h-pc. */ - -USI -a_i960_h_pc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ka_sa : - return i960base_h_pc_get (current_cpu); -#endif -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ca : - return i960base_h_pc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pc. */ - -void -a_i960_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ka_sa : - i960base_h_pc_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ca : - i960base_h_pc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-gr. */ - -SI -a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ka_sa : - return i960base_h_gr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ca : - return i960base_h_gr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-gr. */ - -void -a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ka_sa : - i960base_h_gr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ca : - i960base_h_gr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cc. */ - -SI -a_i960_h_cc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ka_sa : - return i960base_h_cc_get (current_cpu); -#endif -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ca : - return i960base_h_cc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cc. */ - -void -a_i960_h_cc_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ka_sa : - i960base_h_cc_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_I960BASE - case bfd_mach_i960_ca : - i960base_h_cc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - diff --git a/sim/i960/arch.h b/sim/i960/arch.h index 26dcfd6..fdfbf35 100644 --- a/sim/i960/arch.h +++ b/sim/i960/arch.h @@ -27,14 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #define TARGET_BIG_ENDIAN 1 -/* Cover fns for register access. */ -USI a_i960_h_pc_get (SIM_CPU *); -void a_i960_h_pc_set (SIM_CPU *, USI); -SI a_i960_h_gr_get (SIM_CPU *, UINT); -void a_i960_h_gr_set (SIM_CPU *, UINT, SI); -SI a_i960_h_cc_get (SIM_CPU *); -void a_i960_h_cc_set (SIM_CPU *, SI); - /* Enum declaration for model types. */ typedef enum model_type { MODEL_I960KA, MODEL_I960CA, MODEL_MAX diff --git a/sim/i960/cpu.c b/sim/i960/cpu.c index aec6a06..c41b643 100644 --- a/sim/i960/cpu.c +++ b/sim/i960/cpu.c @@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #define WANT_CPU_I960BASE #include "sim-main.h" +#include "cgen-ops.h" /* Get the value of h-pc. */ diff --git a/sim/i960/cpu.h b/sim/i960/cpu.h index 42532b0..9887906 100644 --- a/sim/i960/cpu.h +++ b/sim/i960/cpu.h @@ -154,6 +154,34 @@ union sem_fields { SI * i_dst; unsigned char out_dst; } fmt_not3; + struct { /* e.g. shlo $src1, $src2, $dst */ + SI * i_src1; + SI * i_src2; + SI * i_dst; + unsigned char in_src1; + unsigned char in_src2; + unsigned char out_dst; + } fmt_shlo; + struct { /* e.g. shlo $lit1, $src2, $dst */ + UINT f_src1; + SI * i_src2; + SI * i_dst; + unsigned char in_src2; + unsigned char out_dst; + } fmt_shlo1; + struct { /* e.g. shlo $src1, $lit2, $dst */ + UINT f_src2; + SI * i_src1; + SI * i_dst; + unsigned char in_src1; + unsigned char out_dst; + } fmt_shlo2; + struct { /* e.g. shlo $lit1, $lit2, $dst */ + UINT f_src1; + UINT f_src2; + SI * i_dst; + unsigned char out_dst; + } fmt_shlo3; struct { /* e.g. emul $src1, $src2, $dst */ UINT f_srcdst; SI * i_src1; @@ -162,7 +190,7 @@ union sem_fields { unsigned char in_src1; unsigned char in_src2; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_emul; struct { /* e.g. emul $lit1, $src2, $dst */ UINT f_srcdst; @@ -171,7 +199,7 @@ union sem_fields { SI * i_dst; unsigned char in_src2; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_emul1; struct { /* e.g. emul $src1, $lit2, $dst */ UINT f_srcdst; @@ -180,7 +208,7 @@ union sem_fields { SI * i_dst; unsigned char in_src1; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_emul2; struct { /* e.g. emul $lit1, $lit2, $dst */ UINT f_srcdst; @@ -188,67 +216,67 @@ union sem_fields { UINT f_src2; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_emul3; struct { /* e.g. movl $src1, $dst */ UINT f_src1; UINT f_srcdst; SI * i_src1; SI * i_dst; - unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_src1_1; unsigned char in_src1; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_movl; struct { /* e.g. movl $lit1, $dst */ UINT f_srcdst; UINT f_src1; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_movl1; struct { /* e.g. movt $src1, $dst */ UINT f_src1; UINT f_srcdst; SI * i_src1; SI * i_dst; - unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_src1_1; + unsigned char in_h_gr_add__VM_index_of_src1_2; unsigned char in_src1; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_movt; struct { /* e.g. movt $lit1, $dst */ UINT f_srcdst; UINT f_src1; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_movt1; struct { /* e.g. movq $src1, $dst */ UINT f_src1; UINT f_srcdst; SI * i_src1; SI * i_dst; - unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_src1_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_src1_1; + unsigned char in_h_gr_add__VM_index_of_src1_2; + unsigned char in_h_gr_add__VM_index_of_src1_3; unsigned char in_src1; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_movq; struct { /* e.g. movq $lit1, $dst */ UINT f_srcdst; UINT f_src1; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_movq1; struct { /* e.g. modpc $src1, $src2, $dst */ SI * i_src2; @@ -603,7 +631,7 @@ union sem_fields { UINT f_offset; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_offset; struct { /* e.g. ldl $offset($abase), $dst */ UINT f_srcdst; @@ -612,7 +640,7 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_indirect_offset; struct { /* e.g. ldl ($abase), $dst */ UINT f_srcdst; @@ -620,7 +648,7 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_indirect; struct { /* e.g. ldl ($abase)[$index*S$scale], $dst */ UINT f_srcdst; @@ -631,14 +659,14 @@ union sem_fields { unsigned char in_abase; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_indirect_index; struct { /* e.g. ldl $optdisp, $dst */ UINT f_srcdst; UINT f_optdisp; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_disp; struct { /* e.g. ldl $optdisp($abase), $dst */ UINT f_srcdst; @@ -647,7 +675,7 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_indirect_disp; struct { /* e.g. ldl $optdisp[$index*S$scale], $dst */ UINT f_srcdst; @@ -657,7 +685,7 @@ union sem_fields { SI * i_dst; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_index_disp; struct { /* e.g. ldl $optdisp($abase)[$index*S$scale], $dst */ UINT f_srcdst; @@ -669,15 +697,15 @@ union sem_fields { unsigned char in_abase; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; + unsigned char out_h_gr_add__VM_index_of_dst_1; } fmt_ldl_indirect_index_disp; struct { /* e.g. ldt $offset, $dst */ UINT f_srcdst; UINT f_offset; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_offset; struct { /* e.g. ldt $offset($abase), $dst */ UINT f_srcdst; @@ -686,8 +714,8 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_indirect_offset; struct { /* e.g. ldt ($abase), $dst */ UINT f_srcdst; @@ -695,8 +723,8 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_indirect; struct { /* e.g. ldt ($abase)[$index*S$scale], $dst */ UINT f_srcdst; @@ -707,16 +735,16 @@ union sem_fields { unsigned char in_abase; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_indirect_index; struct { /* e.g. ldt $optdisp, $dst */ UINT f_srcdst; UINT f_optdisp; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_disp; struct { /* e.g. ldt $optdisp($abase), $dst */ UINT f_srcdst; @@ -725,8 +753,8 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_indirect_disp; struct { /* e.g. ldt $optdisp[$index*S$scale], $dst */ UINT f_srcdst; @@ -736,8 +764,8 @@ union sem_fields { SI * i_dst; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_index_disp; struct { /* e.g. ldt $optdisp($abase)[$index*S$scale], $dst */ UINT f_srcdst; @@ -749,17 +777,17 @@ union sem_fields { unsigned char in_abase; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; } fmt_ldt_indirect_index_disp; struct { /* e.g. ldq $offset, $dst */ UINT f_srcdst; UINT f_offset; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_offset; struct { /* e.g. ldq $offset($abase), $dst */ UINT f_srcdst; @@ -768,9 +796,9 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_indirect_offset; struct { /* e.g. ldq ($abase), $dst */ UINT f_srcdst; @@ -778,9 +806,9 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_indirect; struct { /* e.g. ldq ($abase)[$index*S$scale], $dst */ UINT f_srcdst; @@ -791,18 +819,18 @@ union sem_fields { unsigned char in_abase; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_indirect_index; struct { /* e.g. ldq $optdisp, $dst */ UINT f_srcdst; UINT f_optdisp; SI * i_dst; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_disp; struct { /* e.g. ldq $optdisp($abase), $dst */ UINT f_srcdst; @@ -811,9 +839,9 @@ union sem_fields { SI * i_dst; unsigned char in_abase; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_indirect_disp; struct { /* e.g. ldq $optdisp[$index*S$scale], $dst */ UINT f_srcdst; @@ -823,9 +851,9 @@ union sem_fields { SI * i_dst; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_index_disp; struct { /* e.g. ldq $optdisp($abase)[$index*S$scale], $dst */ UINT f_srcdst; @@ -837,9 +865,9 @@ union sem_fields { unsigned char in_abase; unsigned char in_index; unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2; - unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; } fmt_ldq_indirect_index_disp; struct { /* e.g. st $st_src, $offset */ UINT f_offset; @@ -1016,7 +1044,7 @@ union sem_fields { UINT f_srcdst; UINT f_offset; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_st_src; } fmt_stl_offset; struct { /* e.g. stl $st_src, $offset($abase) */ @@ -1025,7 +1053,7 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_st_src; } fmt_stl_indirect_offset; struct { /* e.g. stl $st_src, ($abase) */ @@ -1033,7 +1061,7 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_st_src; } fmt_stl_indirect; struct { /* e.g. stl $st_src, ($abase)[$index*S$scale] */ @@ -1043,7 +1071,7 @@ union sem_fields { SI * i_index; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_index; unsigned char in_st_src; } fmt_stl_indirect_index; @@ -1051,7 +1079,7 @@ union sem_fields { UINT f_srcdst; UINT f_optdisp; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_st_src; } fmt_stl_disp; struct { /* e.g. stl $st_src, $optdisp($abase) */ @@ -1060,7 +1088,7 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_st_src; } fmt_stl_indirect_disp; struct { /* e.g. stl $st_src, $optdisp[$index*S$scale */ @@ -1069,7 +1097,7 @@ union sem_fields { UINT f_scale; SI * i_index; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_index; unsigned char in_st_src; } fmt_stl_index_disp; @@ -1081,7 +1109,7 @@ union sem_fields { SI * i_index; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; + unsigned char in_h_gr_add__VM_index_of_st_src_1; unsigned char in_index; unsigned char in_st_src; } fmt_stl_indirect_index_disp; @@ -1089,8 +1117,8 @@ union sem_fields { UINT f_srcdst; UINT f_offset; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_st_src; } fmt_stt_offset; struct { /* e.g. stt $st_src, $offset($abase) */ @@ -1099,8 +1127,8 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_st_src; } fmt_stt_indirect_offset; struct { /* e.g. stt $st_src, ($abase) */ @@ -1108,8 +1136,8 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_st_src; } fmt_stt_indirect; struct { /* e.g. stt $st_src, ($abase)[$index*S$scale] */ @@ -1119,8 +1147,8 @@ union sem_fields { SI * i_index; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_index; unsigned char in_st_src; } fmt_stt_indirect_index; @@ -1128,8 +1156,8 @@ union sem_fields { UINT f_srcdst; UINT f_optdisp; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_st_src; } fmt_stt_disp; struct { /* e.g. stt $st_src, $optdisp($abase) */ @@ -1138,8 +1166,8 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_st_src; } fmt_stt_indirect_disp; struct { /* e.g. stt $st_src, $optdisp[$index*S$scale */ @@ -1148,8 +1176,8 @@ union sem_fields { UINT f_scale; SI * i_index; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_index; unsigned char in_st_src; } fmt_stt_index_disp; @@ -1161,8 +1189,8 @@ union sem_fields { SI * i_index; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; unsigned char in_index; unsigned char in_st_src; } fmt_stt_indirect_index_disp; @@ -1170,9 +1198,9 @@ union sem_fields { UINT f_srcdst; UINT f_offset; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_st_src; } fmt_stq_offset; struct { /* e.g. stq $st_src, $offset($abase) */ @@ -1181,9 +1209,9 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_st_src; } fmt_stq_indirect_offset; struct { /* e.g. stq $st_src, ($abase) */ @@ -1191,9 +1219,9 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_st_src; } fmt_stq_indirect; struct { /* e.g. stq $st_src, ($abase)[$index*S$scale] */ @@ -1203,9 +1231,9 @@ union sem_fields { SI * i_index; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_index; unsigned char in_st_src; } fmt_stq_indirect_index; @@ -1213,9 +1241,9 @@ union sem_fields { UINT f_srcdst; UINT f_optdisp; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_st_src; } fmt_stq_disp; struct { /* e.g. stq $st_src, $optdisp($abase) */ @@ -1224,9 +1252,9 @@ union sem_fields { SI * i_abase; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_st_src; } fmt_stq_indirect_disp; struct { /* e.g. stq $st_src, $optdisp[$index*S$scale */ @@ -1235,9 +1263,9 @@ union sem_fields { UINT f_scale; SI * i_index; SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_index; unsigned char in_st_src; } fmt_stq_index_disp; @@ -1249,9 +1277,9 @@ union sem_fields { SI * i_index; SI * i_st_src; unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2; - unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; unsigned char in_index; unsigned char in_st_src; } fmt_stq_indirect_index_disp; diff --git a/sim/i960/decode.c b/sim/i960/decode.c index 2bb81ee..a3ac523 100644 --- a/sim/i960/decode.c +++ b/sim/i960/decode.c @@ -46,6 +46,11 @@ with this program; if not, write to the Free Software Foundation, Inc., #define FAST(fn) #endif +/* The INSN_ prefix is not here and is instead part of the `insn' argument + to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ +#define IDX(insn) CONCAT2 (I960BASE_,insn) +#define TYPE(insn) CONCAT2 (I960_,insn) + /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -53,11 +58,6 @@ with this program; if not, write to the Free Software Foundation, Inc., addition of instructions nor an SMP machine with different cpus). */ static IDESC i960base_insn_data[I960BASE_INSN_MAX]; -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (I960BASE_,insn) -#define TYPE(insn) CONCAT2 (I960_,insn) - /* Commas between elements are contained in the macros. Some of these are conditionally compiled out. */ @@ -129,10 +129,18 @@ static const struct insn_sem i960base_insn_sem[] = { TYPE (INSN_NOR1), IDX (INSN_NOR1), FULL (nor1) FAST (nor1) }, { TYPE (INSN_NOR2), IDX (INSN_NOR2), FULL (nor2) FAST (nor2) }, { TYPE (INSN_NOR3), IDX (INSN_NOR3), FULL (nor3) FAST (nor3) }, + { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) }, + { TYPE (INSN_XNOR1), IDX (INSN_XNOR1), FULL (xnor1) FAST (xnor1) }, + { TYPE (INSN_XNOR2), IDX (INSN_XNOR2), FULL (xnor2) FAST (xnor2) }, + { TYPE (INSN_XNOR3), IDX (INSN_XNOR3), FULL (xnor3) FAST (xnor3) }, { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) }, { TYPE (INSN_NOT1), IDX (INSN_NOT1), FULL (not1) FAST (not1) }, { TYPE (INSN_NOT2), IDX (INSN_NOT2), FULL (not2) FAST (not2) }, { TYPE (INSN_NOT3), IDX (INSN_NOT3), FULL (not3) FAST (not3) }, + { TYPE (INSN_ORNOT), IDX (INSN_ORNOT), FULL (ornot) FAST (ornot) }, + { TYPE (INSN_ORNOT1), IDX (INSN_ORNOT1), FULL (ornot1) FAST (ornot1) }, + { TYPE (INSN_ORNOT2), IDX (INSN_ORNOT2), FULL (ornot2) FAST (ornot2) }, + { TYPE (INSN_ORNOT3), IDX (INSN_ORNOT3), FULL (ornot3) FAST (ornot3) }, { TYPE (INSN_CLRBIT), IDX (INSN_CLRBIT), FULL (clrbit) FAST (clrbit) }, { TYPE (INSN_CLRBIT1), IDX (INSN_CLRBIT1), FULL (clrbit1) FAST (clrbit1) }, { TYPE (INSN_CLRBIT2), IDX (INSN_CLRBIT2), FULL (clrbit2) FAST (clrbit2) }, @@ -359,6 +367,9 @@ static const struct insn_sem i960base_insn_sem_invalid = VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }; +#undef FMT +#undef FULL +#undef FAST #undef IDX #undef TYPE @@ -420,80 +431,6 @@ i960base_init_idesc_table (SIM_CPU *cpu) CPU_IDESC (cpu) = table; } -/* Enum declaration for all instruction semantic formats. */ -typedef enum sfmt { - FMT_EMPTY, FMT_MULO, FMT_MULO1, FMT_MULO2 - , FMT_MULO3, FMT_NOTBIT, FMT_NOTBIT1, FMT_NOTBIT2 - , FMT_NOTBIT3, FMT_NOT, FMT_NOT1, FMT_NOT2 - , FMT_NOT3, FMT_EMUL, FMT_EMUL1, FMT_EMUL2 - , FMT_EMUL3, FMT_MOVL, FMT_MOVL1, FMT_MOVT - , FMT_MOVT1, FMT_MOVQ, FMT_MOVQ1, FMT_MODPC - , FMT_LDA_OFFSET, FMT_LDA_INDIRECT_OFFSET, FMT_LDA_INDIRECT, FMT_LDA_INDIRECT_INDEX - , FMT_LDA_DISP, FMT_LDA_INDIRECT_DISP, FMT_LDA_INDEX_DISP, FMT_LDA_INDIRECT_INDEX_DISP - , FMT_LD_OFFSET, FMT_LD_INDIRECT_OFFSET, FMT_LD_INDIRECT, FMT_LD_INDIRECT_INDEX - , FMT_LD_DISP, FMT_LD_INDIRECT_DISP, FMT_LD_INDEX_DISP, FMT_LD_INDIRECT_INDEX_DISP - , FMT_LDOB_OFFSET, FMT_LDOB_INDIRECT_OFFSET, FMT_LDOB_INDIRECT, FMT_LDOB_INDIRECT_INDEX - , FMT_LDOB_DISP, FMT_LDOB_INDIRECT_DISP, FMT_LDOB_INDEX_DISP, FMT_LDOB_INDIRECT_INDEX_DISP - , FMT_LDOS_OFFSET, FMT_LDOS_INDIRECT_OFFSET, FMT_LDOS_INDIRECT, FMT_LDOS_INDIRECT_INDEX - , FMT_LDOS_DISP, FMT_LDOS_INDIRECT_DISP, FMT_LDOS_INDEX_DISP, FMT_LDOS_INDIRECT_INDEX_DISP - , FMT_LDIB_OFFSET, FMT_LDIB_INDIRECT_OFFSET, FMT_LDIB_INDIRECT, FMT_LDIB_INDIRECT_INDEX - , FMT_LDIB_DISP, FMT_LDIB_INDIRECT_DISP, FMT_LDIB_INDEX_DISP, FMT_LDIB_INDIRECT_INDEX_DISP - , FMT_LDIS_OFFSET, FMT_LDIS_INDIRECT_OFFSET, FMT_LDIS_INDIRECT, FMT_LDIS_INDIRECT_INDEX - , FMT_LDIS_DISP, FMT_LDIS_INDIRECT_DISP, FMT_LDIS_INDEX_DISP, FMT_LDIS_INDIRECT_INDEX_DISP - , FMT_LDL_OFFSET, FMT_LDL_INDIRECT_OFFSET, FMT_LDL_INDIRECT, FMT_LDL_INDIRECT_INDEX - , FMT_LDL_DISP, FMT_LDL_INDIRECT_DISP, FMT_LDL_INDEX_DISP, FMT_LDL_INDIRECT_INDEX_DISP - , FMT_LDT_OFFSET, FMT_LDT_INDIRECT_OFFSET, FMT_LDT_INDIRECT, FMT_LDT_INDIRECT_INDEX - , FMT_LDT_DISP, FMT_LDT_INDIRECT_DISP, FMT_LDT_INDEX_DISP, FMT_LDT_INDIRECT_INDEX_DISP - , FMT_LDQ_OFFSET, FMT_LDQ_INDIRECT_OFFSET, FMT_LDQ_INDIRECT, FMT_LDQ_INDIRECT_INDEX - , FMT_LDQ_DISP, FMT_LDQ_INDIRECT_DISP, FMT_LDQ_INDEX_DISP, FMT_LDQ_INDIRECT_INDEX_DISP - , FMT_ST_OFFSET, FMT_ST_INDIRECT_OFFSET, FMT_ST_INDIRECT, FMT_ST_INDIRECT_INDEX - , FMT_ST_DISP, FMT_ST_INDIRECT_DISP, FMT_ST_INDEX_DISP, FMT_ST_INDIRECT_INDEX_DISP - , FMT_STOB_OFFSET, FMT_STOB_INDIRECT_OFFSET, FMT_STOB_INDIRECT, FMT_STOB_INDIRECT_INDEX - , FMT_STOB_DISP, FMT_STOB_INDIRECT_DISP, FMT_STOB_INDEX_DISP, FMT_STOB_INDIRECT_INDEX_DISP - , FMT_STOS_OFFSET, FMT_STOS_INDIRECT_OFFSET, FMT_STOS_INDIRECT, FMT_STOS_INDIRECT_INDEX - , FMT_STOS_DISP, FMT_STOS_INDIRECT_DISP, FMT_STOS_INDEX_DISP, FMT_STOS_INDIRECT_INDEX_DISP - , FMT_STL_OFFSET, FMT_STL_INDIRECT_OFFSET, FMT_STL_INDIRECT, FMT_STL_INDIRECT_INDEX - , FMT_STL_DISP, FMT_STL_INDIRECT_DISP, FMT_STL_INDEX_DISP, FMT_STL_INDIRECT_INDEX_DISP - , FMT_STT_OFFSET, FMT_STT_INDIRECT_OFFSET, FMT_STT_INDIRECT, FMT_STT_INDIRECT_INDEX - , FMT_STT_DISP, FMT_STT_INDIRECT_DISP, FMT_STT_INDEX_DISP, FMT_STT_INDIRECT_INDEX_DISP - , FMT_STQ_OFFSET, FMT_STQ_INDIRECT_OFFSET, FMT_STQ_INDIRECT, FMT_STQ_INDIRECT_INDEX - , FMT_STQ_DISP, FMT_STQ_INDIRECT_DISP, FMT_STQ_INDEX_DISP, FMT_STQ_INDIRECT_INDEX_DISP - , FMT_CMPOBE_REG, FMT_CMPOBE_LIT, FMT_CMPOBL_REG, FMT_CMPOBL_LIT - , FMT_BBC_REG, FMT_BBC_LIT, FMT_CMPI, FMT_CMPI1 - , FMT_CMPI2, FMT_CMPI3, FMT_CMPO, FMT_CMPO1 - , FMT_CMPO2, FMT_CMPO3, FMT_TESTNO_REG, FMT_BNO - , FMT_B, FMT_BX_INDIRECT_OFFSET, FMT_BX_INDIRECT, FMT_BX_INDIRECT_INDEX - , FMT_BX_DISP, FMT_BX_INDIRECT_DISP, FMT_CALLX_DISP, FMT_CALLX_INDIRECT - , FMT_CALLX_INDIRECT_OFFSET, FMT_RET, FMT_CALLS, FMT_FMARK - , FMT_FLUSHREG -} SFMT; - -/* The decoder uses this to record insns and direct extraction handling. */ - -typedef struct { - const IDESC *idesc; -#ifdef __GNUC__ - void *sfmt; -#else - enum sfmt sfmt; -#endif -} DECODE_DESC; - -/* Macro to go from decode phase to extraction phase. */ - -#ifdef __GNUC__ -#define GOTO_EXTRACT(id) goto *(id)->sfmt -#else -#define GOTO_EXTRACT(id) goto extract -#endif - -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) -#endif - /* Given an instruction, return a pointer to its IDESC entry. */ const IDESC * @@ -501,1409 +438,981 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_INT base_insn, ARGBUF *abuf) { - /* Result of decoder, used by extractor. */ - const DECODE_DESC *idecode; - - /* First decode the instruction. */ + /* Result of decoder. */ + I960BASE_INSN_TYPE itype; { -#define I(insn) & i960base_insn_data[CONCAT2 (I960BASE_,insn)] -#ifdef __GNUC__ -#define E(fmt) && case_ex_##fmt -#else -#define E(fmt) fmt -#endif - CGEN_INSN_INT insn = base_insn; - static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) }; - - { -#ifdef __GNUC__ - static const void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_48, && case_0_49, && case_0_50, && case_0_51, - && case_0_52, && case_0_53, && case_0_54, && case_0_55, - && default_0, && case_0_57, && case_0_58, && case_0_59, - && case_0_60, && case_0_61, && case_0_62, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_88, && case_0_89, && case_0_90, && default_0, - && case_0_92, && case_0_93, && case_0_94, && case_0_95, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && case_0_102, && case_0_103, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_112, && default_0, && default_0, && default_0, - && case_0_116, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_128, && default_0, && case_0_130, && default_0, - && case_0_132, && default_0, && case_0_134, && default_0, - && case_0_136, && default_0, && case_0_138, && default_0, - && case_0_140, && default_0, && default_0, && default_0, - && case_0_144, && default_0, && case_0_146, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_152, && default_0, && case_0_154, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_160, && default_0, && case_0_162, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_176, && default_0, && case_0_178, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_192, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_200, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - }; -#endif - static const DECODE_DESC insns[256] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_B), E (FMT_B) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_RET), E (FMT_RET) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BNO), E (FMT_BNO) }, { I (INSN_BG), E (FMT_BNO) }, - { I (INSN_BE), E (FMT_BNO) }, { I (INSN_BGE), E (FMT_BNO) }, - { I (INSN_BL), E (FMT_BNO) }, { I (INSN_BNE), E (FMT_BNO) }, - { I (INSN_BLE), E (FMT_BNO) }, { I (INSN_BO), E (FMT_BNO) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_TESTNO_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTG_REG), E (FMT_TESTNO_REG) }, - { I (INSN_TESTE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTGE_REG), E (FMT_TESTNO_REG) }, - { I (INSN_TESTL_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTNE_REG), E (FMT_TESTNO_REG) }, - { I (INSN_TESTLE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTO_REG), E (FMT_TESTNO_REG) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { 0 }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_MODAC), E (FMT_MODPC) }, { I (INSN_MODPC), E (FMT_MODPC) }, - { 0 }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val; - val = (((insn >> 24) & (255 << 0))); - DECODE_SWITCH (0, val) + CGEN_INSN_INT insn = base_insn; + + { + unsigned int val = (((insn >> 24) & (255 << 0))); + switch (val) + { + case 8 : itype = I960BASE_INSN_B; goto extract_fmt_b; + case 10 : itype = I960BASE_INSN_RET; goto extract_fmt_ret; + case 16 : itype = I960BASE_INSN_BNO; goto extract_fmt_bno; + case 17 : itype = I960BASE_INSN_BG; goto extract_fmt_bno; + case 18 : itype = I960BASE_INSN_BE; goto extract_fmt_bno; + case 19 : itype = I960BASE_INSN_BGE; goto extract_fmt_bno; + case 20 : itype = I960BASE_INSN_BL; goto extract_fmt_bno; + case 21 : itype = I960BASE_INSN_BNE; goto extract_fmt_bno; + case 22 : itype = I960BASE_INSN_BLE; goto extract_fmt_bno; + case 23 : itype = I960BASE_INSN_BO; goto extract_fmt_bno; + case 32 : itype = I960BASE_INSN_TESTNO_REG; goto extract_fmt_testno_reg; + case 33 : itype = I960BASE_INSN_TESTG_REG; goto extract_fmt_testno_reg; + case 34 : itype = I960BASE_INSN_TESTE_REG; goto extract_fmt_testno_reg; + case 35 : itype = I960BASE_INSN_TESTGE_REG; goto extract_fmt_testno_reg; + case 36 : itype = I960BASE_INSN_TESTL_REG; goto extract_fmt_testno_reg; + case 37 : itype = I960BASE_INSN_TESTNE_REG; goto extract_fmt_testno_reg; + case 38 : itype = I960BASE_INSN_TESTLE_REG; goto extract_fmt_testno_reg; + case 39 : itype = I960BASE_INSN_TESTO_REG; goto extract_fmt_testno_reg; + case 48 : { - CASE (0, 48) : + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_BBC_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BBC_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_BBC_REG; goto extract_fmt_bbc_reg; + case 4 : itype = I960BASE_INSN_BBC_LIT; goto extract_fmt_bbc_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 49) : + } + case 49 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPOBG_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPOBG_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPOBG_REG; goto extract_fmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBG_LIT; goto extract_fmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 50) : + } + case 50 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPOBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPOBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPOBE_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPOBE_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 51) : + } + case 51 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPOBGE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPOBGE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPOBGE_REG; goto extract_fmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBGE_LIT; goto extract_fmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 52) : + } + case 52 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPOBL_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPOBL_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPOBL_REG; goto extract_fmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBL_LIT; goto extract_fmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 53) : + } + case 53 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPOBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPOBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPOBNE_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPOBNE_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 54) : + } + case 54 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPOBLE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPOBLE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPOBLE_REG; goto extract_fmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBLE_LIT; goto extract_fmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 55) : + } + case 55 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_BBS_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BBS_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_BBS_REG; goto extract_fmt_bbc_reg; + case 4 : itype = I960BASE_INSN_BBS_LIT; goto extract_fmt_bbc_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 57) : + } + case 57 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPIBG_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPIBG_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPIBG_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBG_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 58) : + } + case 58 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPIBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPIBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPIBE_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBE_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 59) : + } + case 59 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPIBGE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPIBGE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPIBGE_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBGE_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 60) : + } + case 60 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPIBL_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPIBL_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPIBL_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBL_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 61) : + } + case 61 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPIBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPIBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPIBNE_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBNE_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 62) : + } + case 62 : + { + unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val) { - static const DECODE_DESC insns[8] = { - { I (INSN_CMPIBLE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPIBLE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPIBLE_REG; goto extract_fmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBLE_LIT; goto extract_fmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 88) : + } + case 88 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { -#ifdef __GNUC__ - static const void *labels_0_88[16] = { - && case_0_88_0, && case_0_88_1, && case_0_88_2, && case_0_88_3, - && case_0_88_4, && case_0_88_5, && case_0_88_6, && case_0_88_7, - && default_0_88, && default_0_88, && default_0_88, && default_0_88, - && default_0_88, && default_0_88, && default_0_88, && default_0_88, - }; -#endif - static const DECODE_DESC insns[16] = { - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val; - val = (((insn >> 10) & (15 << 0))); - DECODE_SWITCH (0_88, val) + case 0 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOTBIT; goto extract_fmt_notbit; + case 2 : itype = I960BASE_INSN_AND; goto extract_fmt_mulo; + case 4 : itype = I960BASE_INSN_ANDNOT; goto extract_fmt_mulo; + case 6 : itype = I960BASE_INSN_SETBIT; goto extract_fmt_notbit; + case 8 : itype = I960BASE_INSN_NOTAND; goto extract_fmt_mulo; + case 12 : itype = I960BASE_INSN_XOR; goto extract_fmt_mulo; + case 14 : itype = I960BASE_INSN_OR; goto extract_fmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 1 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOR; goto extract_fmt_mulo; + case 2 : itype = I960BASE_INSN_XNOR; goto extract_fmt_mulo; + case 4 : itype = I960BASE_INSN_NOT; goto extract_fmt_not; + case 6 : itype = I960BASE_INSN_ORNOT; goto extract_fmt_mulo; + case 8 : itype = I960BASE_INSN_CLRBIT; goto extract_fmt_notbit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 2 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOTBIT1; goto extract_fmt_notbit1; + case 2 : itype = I960BASE_INSN_AND1; goto extract_fmt_mulo1; + case 4 : itype = I960BASE_INSN_ANDNOT1; goto extract_fmt_mulo1; + case 6 : itype = I960BASE_INSN_SETBIT1; goto extract_fmt_notbit1; + case 8 : itype = I960BASE_INSN_NOTAND1; goto extract_fmt_mulo1; + case 12 : itype = I960BASE_INSN_XOR1; goto extract_fmt_mulo1; + case 14 : itype = I960BASE_INSN_OR1; goto extract_fmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 3 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOR1; goto extract_fmt_mulo1; + case 2 : itype = I960BASE_INSN_XNOR1; goto extract_fmt_mulo1; + case 4 : itype = I960BASE_INSN_NOT1; goto extract_fmt_not1; + case 6 : itype = I960BASE_INSN_ORNOT1; goto extract_fmt_mulo1; + case 8 : itype = I960BASE_INSN_CLRBIT1; goto extract_fmt_notbit1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 4 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOTBIT2; goto extract_fmt_notbit2; + case 2 : itype = I960BASE_INSN_AND2; goto extract_fmt_mulo2; + case 4 : itype = I960BASE_INSN_ANDNOT2; goto extract_fmt_mulo2; + case 6 : itype = I960BASE_INSN_SETBIT2; goto extract_fmt_notbit2; + case 8 : itype = I960BASE_INSN_NOTAND2; goto extract_fmt_mulo2; + case 12 : itype = I960BASE_INSN_XOR2; goto extract_fmt_mulo2; + case 14 : itype = I960BASE_INSN_OR2; goto extract_fmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 5 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOR2; goto extract_fmt_mulo2; + case 2 : itype = I960BASE_INSN_XNOR2; goto extract_fmt_mulo2; + case 4 : itype = I960BASE_INSN_NOT2; goto extract_fmt_not2; + case 6 : itype = I960BASE_INSN_ORNOT2; goto extract_fmt_mulo2; + case 8 : itype = I960BASE_INSN_CLRBIT2; goto extract_fmt_notbit2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 6 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_NOTBIT3; goto extract_fmt_notbit3; + case 2 : itype = I960BASE_INSN_AND3; goto extract_fmt_mulo3; + case 4 : itype = I960BASE_INSN_ANDNOT3; goto extract_fmt_mulo3; + case 6 : itype = I960BASE_INSN_SETBIT3; goto extract_fmt_notbit3; + case 8 : itype = I960BASE_INSN_NOTAND3; goto extract_fmt_mulo3; + case 12 : itype = I960BASE_INSN_XOR3; goto extract_fmt_mulo3; + case 14 : itype = I960BASE_INSN_OR3; goto extract_fmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 7 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) { - CASE (0_88, 0) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOTBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_AND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ANDNOT), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SETBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOTAND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_XOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_OR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 1) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOT), E (FMT_NOT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CLRBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 2) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOTBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_AND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ANDNOT1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SETBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOTAND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_XOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_OR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 3) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOT1), E (FMT_NOT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CLRBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 4) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOTBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_AND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ANDNOT2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SETBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOTAND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_XOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_OR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 5) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOT2), E (FMT_NOT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CLRBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 6) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOTBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_AND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ANDNOT3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SETBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOTAND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_XOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_OR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_88, 7) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_NOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_NOT3), E (FMT_NOT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CLRBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_88) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_NOR3; goto extract_fmt_mulo3; + case 2 : itype = I960BASE_INSN_XNOR3; goto extract_fmt_mulo3; + case 4 : itype = I960BASE_INSN_NOT3; goto extract_fmt_not3; + case 6 : itype = I960BASE_INSN_ORNOT3; goto extract_fmt_mulo3; + case 8 : itype = I960BASE_INSN_CLRBIT3; goto extract_fmt_notbit3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - ENDSWITCH (0_88) + } + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 89) : + } + case 89 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { -#ifdef __GNUC__ - static const void *labels_0_89[16] = { - && case_0_89_0, && case_0_89_1, && case_0_89_2, && case_0_89_3, - && case_0_89_4, && case_0_89_5, && case_0_89_6, && case_0_89_7, - && default_0_89, && default_0_89, && default_0_89, && default_0_89, - && default_0_89, && default_0_89, && default_0_89, && default_0_89, - }; -#endif - static const DECODE_DESC insns[16] = { - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val; - val = (((insn >> 10) & (15 << 0))); - DECODE_SWITCH (0_89, val) + case 0 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_ADDO; goto extract_fmt_mulo; + case 4 : itype = I960BASE_INSN_SUBO; goto extract_fmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 1 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_SHRO; goto extract_fmt_shlo; + case 6 : itype = I960BASE_INSN_SHRI; goto extract_fmt_shlo; + case 8 : itype = I960BASE_INSN_SHLO; goto extract_fmt_shlo; + case 12 : itype = I960BASE_INSN_SHLI; goto extract_fmt_shlo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 2 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_ADDO1; goto extract_fmt_mulo1; + case 4 : itype = I960BASE_INSN_SUBO1; goto extract_fmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 3 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_SHRO1; goto extract_fmt_shlo1; + case 6 : itype = I960BASE_INSN_SHRI1; goto extract_fmt_shlo1; + case 8 : itype = I960BASE_INSN_SHLO1; goto extract_fmt_shlo1; + case 12 : itype = I960BASE_INSN_SHLI1; goto extract_fmt_shlo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 4 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_ADDO2; goto extract_fmt_mulo2; + case 4 : itype = I960BASE_INSN_SUBO2; goto extract_fmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 5 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_SHRO2; goto extract_fmt_shlo2; + case 6 : itype = I960BASE_INSN_SHRI2; goto extract_fmt_shlo2; + case 8 : itype = I960BASE_INSN_SHLO2; goto extract_fmt_shlo2; + case 12 : itype = I960BASE_INSN_SHLI2; goto extract_fmt_shlo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 6 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_ADDO3; goto extract_fmt_mulo3; + case 4 : itype = I960BASE_INSN_SUBO3; goto extract_fmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 7 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) { - CASE (0_89, 0) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_ADDO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SUBO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 1) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_SHRO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHRI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 2) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_ADDO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SUBO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 3) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_SHRO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHRI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 4) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_ADDO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SUBO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 5) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_SHRO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHRI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 6) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_ADDO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SUBO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_89, 7) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_SHRO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHRI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SHLI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_89) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_SHRO3; goto extract_fmt_shlo3; + case 6 : itype = I960BASE_INSN_SHRI3; goto extract_fmt_shlo3; + case 8 : itype = I960BASE_INSN_SHLO3; goto extract_fmt_shlo3; + case 12 : itype = I960BASE_INSN_SHLI3; goto extract_fmt_shlo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - ENDSWITCH (0_89) + } + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 90) : + } + case 90 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { -#ifdef __GNUC__ - static const void *labels_0_90[16] = { - && default_0_90, && default_0_90, && default_0_90, && default_0_90, - && default_0_90, && default_0_90, && default_0_90, && default_0_90, - && case_0_90_8, && default_0_90, && case_0_90_10, && default_0_90, - && case_0_90_12, && default_0_90, && case_0_90_14, && default_0_90, - }; -#endif - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val; - val = (((insn >> 10) & (15 << 0))); - DECODE_SWITCH (0_90, val) + case 8 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_CMPO; goto extract_fmt_cmpo; + case 2 : itype = I960BASE_INSN_CMPI; goto extract_fmt_cmpi; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 10 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_CMPO1; goto extract_fmt_cmpo1; + case 2 : itype = I960BASE_INSN_CMPI1; goto extract_fmt_cmpi1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 12 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_CMPO2; goto extract_fmt_cmpo2; + case 2 : itype = I960BASE_INSN_CMPI2; goto extract_fmt_cmpi2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 14 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) { - CASE (0_90, 8) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_CMPO), E (FMT_CMPO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_90, 10) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_CMPO1), E (FMT_CMPO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPI1), E (FMT_CMPI1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_90, 12) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_CMPO2), E (FMT_CMPO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPI2), E (FMT_CMPI2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_90, 14) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_CMPO3), E (FMT_CMPO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPI3), E (FMT_CMPI3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_90) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_CMPO3; goto extract_fmt_cmpo3; + case 2 : itype = I960BASE_INSN_CMPI3; goto extract_fmt_cmpi3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - ENDSWITCH (0_90) + } + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 92) : + } + case 92 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV), E (FMT_NOT2) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV1), E (FMT_NOT3) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 5 : itype = I960BASE_INSN_MOV; goto extract_fmt_not2; + case 7 : itype = I960BASE_INSN_MOV1; goto extract_fmt_not3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 93) : + } + case 93 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL), E (FMT_MOVL) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL1), E (FMT_MOVL1) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 5 : itype = I960BASE_INSN_MOVL; goto extract_fmt_movl; + case 7 : itype = I960BASE_INSN_MOVL1; goto extract_fmt_movl1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 94) : + } + case 94 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT), E (FMT_MOVT) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT1), E (FMT_MOVT1) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 5 : itype = I960BASE_INSN_MOVT; goto extract_fmt_movt; + case 7 : itype = I960BASE_INSN_MOVT1; goto extract_fmt_movt1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 95) : + } + case 95 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ), E (FMT_MOVQ) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ1), E (FMT_MOVQ1) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 5 : itype = I960BASE_INSN_MOVQ; goto extract_fmt_movq; + case 7 : itype = I960BASE_INSN_MOVQ1; goto extract_fmt_movq1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 102) : + } + case 100 : itype = I960BASE_INSN_MODAC; goto extract_fmt_modpc; + case 101 : itype = I960BASE_INSN_MODPC; goto extract_fmt_modpc; + case 102 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { -#ifdef __GNUC__ - static const void *labels_0_102[16] = { - && default_0_102, && default_0_102, && default_0_102, && default_0_102, - && default_0_102, && default_0_102, && default_0_102, && default_0_102, - && default_0_102, && default_0_102, && default_0_102, && default_0_102, - && default_0_102, && default_0_102, && default_0_102, && case_0_102_15, - }; -#endif - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CALLS), E (FMT_CALLS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - }; - unsigned int val; - val = (((insn >> 10) & (15 << 0))); - DECODE_SWITCH (0_102, val) + case 12 : itype = I960BASE_INSN_CALLS; goto extract_fmt_calls; + case 15 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) { - CASE (0_102, 15) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_FMARK), E (FMT_FMARK) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_FLUSHREG), E (FMT_FLUSHREG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_102) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 8 : itype = I960BASE_INSN_FMARK; goto extract_fmt_fmark; + case 10 : itype = I960BASE_INSN_FLUSHREG; goto extract_fmt_flushreg; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - ENDSWITCH (0_102) + } + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 103) : + } + case 103 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_EMUL), E (FMT_EMUL) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_EMUL1), E (FMT_EMUL1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_EMUL2), E (FMT_EMUL2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_EMUL3), E (FMT_EMUL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_EMUL; goto extract_fmt_emul; + case 2 : itype = I960BASE_INSN_EMUL1; goto extract_fmt_emul1; + case 4 : itype = I960BASE_INSN_EMUL2; goto extract_fmt_emul2; + case 6 : itype = I960BASE_INSN_EMUL3; goto extract_fmt_emul3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 112) : + } + case 112 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { -#ifdef __GNUC__ - static const void *labels_0_112[16] = { - && default_0_112, && case_0_112_1, && default_0_112, && case_0_112_3, - && default_0_112, && case_0_112_5, && default_0_112, && case_0_112_7, - && default_0_112, && default_0_112, && default_0_112, && default_0_112, - && default_0_112, && default_0_112, && default_0_112, && default_0_112, - }; -#endif - static const DECODE_DESC insns[16] = { - { I (INSN_MULO), E (FMT_MULO) }, { 0 }, - { I (INSN_MULO1), E (FMT_MULO1) }, { 0 }, - { I (INSN_MULO2), E (FMT_MULO2) }, { 0 }, - { I (INSN_MULO3), E (FMT_MULO3) }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val; - val = (((insn >> 10) & (15 << 0))); - DECODE_SWITCH (0_112, val) + case 0 : itype = I960BASE_INSN_MULO; goto extract_fmt_mulo; + case 1 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_REMO; goto extract_fmt_mulo; + case 6 : itype = I960BASE_INSN_DIVO; goto extract_fmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 2 : itype = I960BASE_INSN_MULO1; goto extract_fmt_mulo1; + case 3 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_REMO1; goto extract_fmt_mulo1; + case 6 : itype = I960BASE_INSN_DIVO1; goto extract_fmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 4 : itype = I960BASE_INSN_MULO2; goto extract_fmt_mulo2; + case 5 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) { - CASE (0_112, 1) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_112, 3) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_112, 5) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_112, 7) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_112) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_REMO2; goto extract_fmt_mulo2; + case 6 : itype = I960BASE_INSN_DIVO2; goto extract_fmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - ENDSWITCH (0_112) + } + case 6 : itype = I960BASE_INSN_MULO3; goto extract_fmt_mulo3; + case 7 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_REMO3; goto extract_fmt_mulo3; + case 6 : itype = I960BASE_INSN_DIVO3; goto extract_fmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 116) : + } + case 116 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { -#ifdef __GNUC__ - static const void *labels_0_116[16] = { - && default_0_116, && case_0_116_1, && default_0_116, && case_0_116_3, - && default_0_116, && case_0_116_5, && default_0_116, && case_0_116_7, - && default_0_116, && default_0_116, && default_0_116, && default_0_116, - && default_0_116, && default_0_116, && default_0_116, && default_0_116, - }; -#endif - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val; - val = (((insn >> 10) & (15 << 0))); - DECODE_SWITCH (0_116, val) + case 1 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_REMI; goto extract_fmt_mulo; + case 6 : itype = I960BASE_INSN_DIVI; goto extract_fmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 3 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_REMI1; goto extract_fmt_mulo1; + case 6 : itype = I960BASE_INSN_DIVI1; goto extract_fmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + case 5 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) { - CASE (0_116, 1) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_116, 3) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_116, 5) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_116, 7) : - { - static const DECODE_DESC insns[16] = { - { I (INSN_REMI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIVI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 6) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_116) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = I960BASE_INSN_REMI2; goto extract_fmt_mulo2; + case 6 : itype = I960BASE_INSN_DIVI2; goto extract_fmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - ENDSWITCH (0_116) + } + case 7 : + { + unsigned int val = (((insn >> 6) & (15 << 0))); + switch (val) + { + case 0 : itype = I960BASE_INSN_REMI3; goto extract_fmt_mulo3; + case 6 : itype = I960BASE_INSN_DIVI3; goto extract_fmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } + } + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 128) : + } + case 128 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, - { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, - { I (INSN_LDOB_INDIRECT), E (FMT_LDOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOB_INDIRECT_INDEX), E (FMT_LDOB_INDIRECT_INDEX) }, - { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, - { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, - { I (INSN_LDOB_DISP), E (FMT_LDOB_DISP) }, { I (INSN_LDOB_INDIRECT_DISP), E (FMT_LDOB_INDIRECT_DISP) }, - { I (INSN_LDOB_INDEX_DISP), E (FMT_LDOB_INDEX_DISP) }, { I (INSN_LDOB_INDIRECT_INDEX_DISP), E (FMT_LDOB_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDOB_OFFSET; goto extract_fmt_ldob_offset; + case 4 : itype = I960BASE_INSN_LDOB_INDIRECT; goto extract_fmt_ldob_indirect; + case 7 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX; goto extract_fmt_ldob_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDOB_INDIRECT_OFFSET; goto extract_fmt_ldob_indirect_offset; + case 12 : itype = I960BASE_INSN_LDOB_DISP; goto extract_fmt_ldob_disp; + case 13 : itype = I960BASE_INSN_LDOB_INDIRECT_DISP; goto extract_fmt_ldob_indirect_disp; + case 14 : itype = I960BASE_INSN_LDOB_INDEX_DISP; goto extract_fmt_ldob_index_disp; + case 15 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP; goto extract_fmt_ldob_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 130) : + } + case 130 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, - { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, - { I (INSN_STOB_INDIRECT), E (FMT_STOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOB_INDIRECT_INDEX), E (FMT_STOB_INDIRECT_INDEX) }, - { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, - { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, - { I (INSN_STOB_DISP), E (FMT_STOB_DISP) }, { I (INSN_STOB_INDIRECT_DISP), E (FMT_STOB_INDIRECT_DISP) }, - { I (INSN_STOB_INDEX_DISP), E (FMT_STOB_INDEX_DISP) }, { I (INSN_STOB_INDIRECT_INDEX_DISP), E (FMT_STOB_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_STOB_OFFSET; goto extract_fmt_stob_offset; + case 4 : itype = I960BASE_INSN_STOB_INDIRECT; goto extract_fmt_stob_indirect; + case 7 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX; goto extract_fmt_stob_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_STOB_INDIRECT_OFFSET; goto extract_fmt_stob_indirect_offset; + case 12 : itype = I960BASE_INSN_STOB_DISP; goto extract_fmt_stob_disp; + case 13 : itype = I960BASE_INSN_STOB_INDIRECT_DISP; goto extract_fmt_stob_indirect_disp; + case 14 : itype = I960BASE_INSN_STOB_INDEX_DISP; goto extract_fmt_stob_index_disp; + case 15 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX_DISP; goto extract_fmt_stob_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 132) : + } + case 132 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BX_INDIRECT), E (FMT_BX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_BX_INDIRECT_INDEX), E (FMT_BX_INDIRECT_INDEX) }, - { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, - { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, - { I (INSN_BX_DISP), E (FMT_BX_DISP) }, { I (INSN_BX_INDIRECT_DISP), E (FMT_BX_INDIRECT_DISP) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 4 : itype = I960BASE_INSN_BX_INDIRECT; goto extract_fmt_bx_indirect; + case 7 : itype = I960BASE_INSN_BX_INDIRECT_INDEX; goto extract_fmt_bx_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_BX_INDIRECT_OFFSET; goto extract_fmt_bx_indirect_offset; + case 12 : itype = I960BASE_INSN_BX_DISP; goto extract_fmt_bx_disp; + case 13 : itype = I960BASE_INSN_BX_INDIRECT_DISP; goto extract_fmt_bx_indirect_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 134) : + } + case 134 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CALLX_INDIRECT), E (FMT_CALLX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, - { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, - { I (INSN_CALLX_DISP), E (FMT_CALLX_DISP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 4 : itype = I960BASE_INSN_CALLX_INDIRECT; goto extract_fmt_callx_indirect; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_CALLX_INDIRECT_OFFSET; goto extract_fmt_callx_indirect_offset; + case 12 : itype = I960BASE_INSN_CALLX_DISP; goto extract_fmt_callx_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 136) : + } + case 136 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, - { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, - { I (INSN_LDOS_INDIRECT), E (FMT_LDOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOS_INDIRECT_INDEX), E (FMT_LDOS_INDIRECT_INDEX) }, - { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, - { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, - { I (INSN_LDOS_DISP), E (FMT_LDOS_DISP) }, { I (INSN_LDOS_INDIRECT_DISP), E (FMT_LDOS_INDIRECT_DISP) }, - { I (INSN_LDOS_INDEX_DISP), E (FMT_LDOS_INDEX_DISP) }, { I (INSN_LDOS_INDIRECT_INDEX_DISP), E (FMT_LDOS_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDOS_OFFSET; goto extract_fmt_ldos_offset; + case 4 : itype = I960BASE_INSN_LDOS_INDIRECT; goto extract_fmt_ldos_indirect; + case 7 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX; goto extract_fmt_ldos_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDOS_INDIRECT_OFFSET; goto extract_fmt_ldos_indirect_offset; + case 12 : itype = I960BASE_INSN_LDOS_DISP; goto extract_fmt_ldos_disp; + case 13 : itype = I960BASE_INSN_LDOS_INDIRECT_DISP; goto extract_fmt_ldos_indirect_disp; + case 14 : itype = I960BASE_INSN_LDOS_INDEX_DISP; goto extract_fmt_ldos_index_disp; + case 15 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP; goto extract_fmt_ldos_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 138) : + } + case 138 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, - { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, - { I (INSN_STOS_INDIRECT), E (FMT_STOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOS_INDIRECT_INDEX), E (FMT_STOS_INDIRECT_INDEX) }, - { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, - { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, - { I (INSN_STOS_DISP), E (FMT_STOS_DISP) }, { I (INSN_STOS_INDIRECT_DISP), E (FMT_STOS_INDIRECT_DISP) }, - { I (INSN_STOS_INDEX_DISP), E (FMT_STOS_INDEX_DISP) }, { I (INSN_STOS_INDIRECT_INDEX_DISP), E (FMT_STOS_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_STOS_OFFSET; goto extract_fmt_stos_offset; + case 4 : itype = I960BASE_INSN_STOS_INDIRECT; goto extract_fmt_stos_indirect; + case 7 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX; goto extract_fmt_stos_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_STOS_INDIRECT_OFFSET; goto extract_fmt_stos_indirect_offset; + case 12 : itype = I960BASE_INSN_STOS_DISP; goto extract_fmt_stos_disp; + case 13 : itype = I960BASE_INSN_STOS_INDIRECT_DISP; goto extract_fmt_stos_indirect_disp; + case 14 : itype = I960BASE_INSN_STOS_INDEX_DISP; goto extract_fmt_stos_index_disp; + case 15 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX_DISP; goto extract_fmt_stos_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 140) : + } + case 140 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, - { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, - { I (INSN_LDA_INDIRECT), E (FMT_LDA_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDA_INDIRECT_INDEX), E (FMT_LDA_INDIRECT_INDEX) }, - { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, - { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, - { I (INSN_LDA_DISP), E (FMT_LDA_DISP) }, { I (INSN_LDA_INDIRECT_DISP), E (FMT_LDA_INDIRECT_DISP) }, - { I (INSN_LDA_INDEX_DISP), E (FMT_LDA_INDEX_DISP) }, { I (INSN_LDA_INDIRECT_INDEX_DISP), E (FMT_LDA_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDA_OFFSET; goto extract_fmt_lda_offset; + case 4 : itype = I960BASE_INSN_LDA_INDIRECT; goto extract_fmt_lda_indirect; + case 7 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX; goto extract_fmt_lda_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDA_INDIRECT_OFFSET; goto extract_fmt_lda_indirect_offset; + case 12 : itype = I960BASE_INSN_LDA_DISP; goto extract_fmt_lda_disp; + case 13 : itype = I960BASE_INSN_LDA_INDIRECT_DISP; goto extract_fmt_lda_indirect_disp; + case 14 : itype = I960BASE_INSN_LDA_INDEX_DISP; goto extract_fmt_lda_index_disp; + case 15 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX_DISP; goto extract_fmt_lda_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 144) : + } + case 144 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, - { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, - { I (INSN_LD_INDIRECT), E (FMT_LD_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LD_INDIRECT_INDEX), E (FMT_LD_INDIRECT_INDEX) }, - { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, - { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, - { I (INSN_LD_DISP), E (FMT_LD_DISP) }, { I (INSN_LD_INDIRECT_DISP), E (FMT_LD_INDIRECT_DISP) }, - { I (INSN_LD_INDEX_DISP), E (FMT_LD_INDEX_DISP) }, { I (INSN_LD_INDIRECT_INDEX_DISP), E (FMT_LD_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LD_OFFSET; goto extract_fmt_ld_offset; + case 4 : itype = I960BASE_INSN_LD_INDIRECT; goto extract_fmt_ld_indirect; + case 7 : itype = I960BASE_INSN_LD_INDIRECT_INDEX; goto extract_fmt_ld_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LD_INDIRECT_OFFSET; goto extract_fmt_ld_indirect_offset; + case 12 : itype = I960BASE_INSN_LD_DISP; goto extract_fmt_ld_disp; + case 13 : itype = I960BASE_INSN_LD_INDIRECT_DISP; goto extract_fmt_ld_indirect_disp; + case 14 : itype = I960BASE_INSN_LD_INDEX_DISP; goto extract_fmt_ld_index_disp; + case 15 : itype = I960BASE_INSN_LD_INDIRECT_INDEX_DISP; goto extract_fmt_ld_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 146) : + } + case 146 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, - { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, - { I (INSN_ST_INDIRECT), E (FMT_ST_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_ST_INDIRECT_INDEX), E (FMT_ST_INDIRECT_INDEX) }, - { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, - { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, - { I (INSN_ST_DISP), E (FMT_ST_DISP) }, { I (INSN_ST_INDIRECT_DISP), E (FMT_ST_INDIRECT_DISP) }, - { I (INSN_ST_INDEX_DISP), E (FMT_ST_INDEX_DISP) }, { I (INSN_ST_INDIRECT_INDEX_DISP), E (FMT_ST_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_ST_OFFSET; goto extract_fmt_st_offset; + case 4 : itype = I960BASE_INSN_ST_INDIRECT; goto extract_fmt_st_indirect; + case 7 : itype = I960BASE_INSN_ST_INDIRECT_INDEX; goto extract_fmt_st_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_ST_INDIRECT_OFFSET; goto extract_fmt_st_indirect_offset; + case 12 : itype = I960BASE_INSN_ST_DISP; goto extract_fmt_st_disp; + case 13 : itype = I960BASE_INSN_ST_INDIRECT_DISP; goto extract_fmt_st_indirect_disp; + case 14 : itype = I960BASE_INSN_ST_INDEX_DISP; goto extract_fmt_st_index_disp; + case 15 : itype = I960BASE_INSN_ST_INDIRECT_INDEX_DISP; goto extract_fmt_st_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 152) : + } + case 152 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, - { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, - { I (INSN_LDL_INDIRECT), E (FMT_LDL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDL_INDIRECT_INDEX), E (FMT_LDL_INDIRECT_INDEX) }, - { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, - { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, - { I (INSN_LDL_DISP), E (FMT_LDL_DISP) }, { I (INSN_LDL_INDIRECT_DISP), E (FMT_LDL_INDIRECT_DISP) }, - { I (INSN_LDL_INDEX_DISP), E (FMT_LDL_INDEX_DISP) }, { I (INSN_LDL_INDIRECT_INDEX_DISP), E (FMT_LDL_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDL_OFFSET; goto extract_fmt_ldl_offset; + case 4 : itype = I960BASE_INSN_LDL_INDIRECT; goto extract_fmt_ldl_indirect; + case 7 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX; goto extract_fmt_ldl_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDL_INDIRECT_OFFSET; goto extract_fmt_ldl_indirect_offset; + case 12 : itype = I960BASE_INSN_LDL_DISP; goto extract_fmt_ldl_disp; + case 13 : itype = I960BASE_INSN_LDL_INDIRECT_DISP; goto extract_fmt_ldl_indirect_disp; + case 14 : itype = I960BASE_INSN_LDL_INDEX_DISP; goto extract_fmt_ldl_index_disp; + case 15 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX_DISP; goto extract_fmt_ldl_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 154) : + } + case 154 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, - { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, - { I (INSN_STL_INDIRECT), E (FMT_STL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STL_INDIRECT_INDEX), E (FMT_STL_INDIRECT_INDEX) }, - { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, - { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, - { I (INSN_STL_DISP), E (FMT_STL_DISP) }, { I (INSN_STL_INDIRECT_DISP), E (FMT_STL_INDIRECT_DISP) }, - { I (INSN_STL_INDEX_DISP), E (FMT_STL_INDEX_DISP) }, { I (INSN_STL_INDIRECT_INDEX_DISP), E (FMT_STL_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_STL_OFFSET; goto extract_fmt_stl_offset; + case 4 : itype = I960BASE_INSN_STL_INDIRECT; goto extract_fmt_stl_indirect; + case 7 : itype = I960BASE_INSN_STL_INDIRECT_INDEX; goto extract_fmt_stl_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_STL_INDIRECT_OFFSET; goto extract_fmt_stl_indirect_offset; + case 12 : itype = I960BASE_INSN_STL_DISP; goto extract_fmt_stl_disp; + case 13 : itype = I960BASE_INSN_STL_INDIRECT_DISP; goto extract_fmt_stl_indirect_disp; + case 14 : itype = I960BASE_INSN_STL_INDEX_DISP; goto extract_fmt_stl_index_disp; + case 15 : itype = I960BASE_INSN_STL_INDIRECT_INDEX_DISP; goto extract_fmt_stl_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 160) : + } + case 160 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, - { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, - { I (INSN_LDT_INDIRECT), E (FMT_LDT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDT_INDIRECT_INDEX), E (FMT_LDT_INDIRECT_INDEX) }, - { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, - { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, - { I (INSN_LDT_DISP), E (FMT_LDT_DISP) }, { I (INSN_LDT_INDIRECT_DISP), E (FMT_LDT_INDIRECT_DISP) }, - { I (INSN_LDT_INDEX_DISP), E (FMT_LDT_INDEX_DISP) }, { I (INSN_LDT_INDIRECT_INDEX_DISP), E (FMT_LDT_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDT_OFFSET; goto extract_fmt_ldt_offset; + case 4 : itype = I960BASE_INSN_LDT_INDIRECT; goto extract_fmt_ldt_indirect; + case 7 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX; goto extract_fmt_ldt_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDT_INDIRECT_OFFSET; goto extract_fmt_ldt_indirect_offset; + case 12 : itype = I960BASE_INSN_LDT_DISP; goto extract_fmt_ldt_disp; + case 13 : itype = I960BASE_INSN_LDT_INDIRECT_DISP; goto extract_fmt_ldt_indirect_disp; + case 14 : itype = I960BASE_INSN_LDT_INDEX_DISP; goto extract_fmt_ldt_index_disp; + case 15 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX_DISP; goto extract_fmt_ldt_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 162) : + } + case 162 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, - { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, - { I (INSN_STT_INDIRECT), E (FMT_STT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STT_INDIRECT_INDEX), E (FMT_STT_INDIRECT_INDEX) }, - { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, - { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, - { I (INSN_STT_DISP), E (FMT_STT_DISP) }, { I (INSN_STT_INDIRECT_DISP), E (FMT_STT_INDIRECT_DISP) }, - { I (INSN_STT_INDEX_DISP), E (FMT_STT_INDEX_DISP) }, { I (INSN_STT_INDIRECT_INDEX_DISP), E (FMT_STT_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_STT_OFFSET; goto extract_fmt_stt_offset; + case 4 : itype = I960BASE_INSN_STT_INDIRECT; goto extract_fmt_stt_indirect; + case 7 : itype = I960BASE_INSN_STT_INDIRECT_INDEX; goto extract_fmt_stt_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_STT_INDIRECT_OFFSET; goto extract_fmt_stt_indirect_offset; + case 12 : itype = I960BASE_INSN_STT_DISP; goto extract_fmt_stt_disp; + case 13 : itype = I960BASE_INSN_STT_INDIRECT_DISP; goto extract_fmt_stt_indirect_disp; + case 14 : itype = I960BASE_INSN_STT_INDEX_DISP; goto extract_fmt_stt_index_disp; + case 15 : itype = I960BASE_INSN_STT_INDIRECT_INDEX_DISP; goto extract_fmt_stt_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 176) : + } + case 176 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, - { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, - { I (INSN_LDQ_INDIRECT), E (FMT_LDQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDQ_INDIRECT_INDEX), E (FMT_LDQ_INDIRECT_INDEX) }, - { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, - { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, - { I (INSN_LDQ_DISP), E (FMT_LDQ_DISP) }, { I (INSN_LDQ_INDIRECT_DISP), E (FMT_LDQ_INDIRECT_DISP) }, - { I (INSN_LDQ_INDEX_DISP), E (FMT_LDQ_INDEX_DISP) }, { I (INSN_LDQ_INDIRECT_INDEX_DISP), E (FMT_LDQ_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDQ_OFFSET; goto extract_fmt_ldq_offset; + case 4 : itype = I960BASE_INSN_LDQ_INDIRECT; goto extract_fmt_ldq_indirect; + case 7 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX; goto extract_fmt_ldq_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDQ_INDIRECT_OFFSET; goto extract_fmt_ldq_indirect_offset; + case 12 : itype = I960BASE_INSN_LDQ_DISP; goto extract_fmt_ldq_disp; + case 13 : itype = I960BASE_INSN_LDQ_INDIRECT_DISP; goto extract_fmt_ldq_indirect_disp; + case 14 : itype = I960BASE_INSN_LDQ_INDEX_DISP; goto extract_fmt_ldq_index_disp; + case 15 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP; goto extract_fmt_ldq_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 178) : + } + case 178 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, - { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, - { I (INSN_STQ_INDIRECT), E (FMT_STQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STQ_INDIRECT_INDEX), E (FMT_STQ_INDIRECT_INDEX) }, - { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, - { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, - { I (INSN_STQ_DISP), E (FMT_STQ_DISP) }, { I (INSN_STQ_INDIRECT_DISP), E (FMT_STQ_INDIRECT_DISP) }, - { I (INSN_STQ_INDEX_DISP), E (FMT_STQ_INDEX_DISP) }, { I (INSN_STQ_INDIRECT_INDEX_DISP), E (FMT_STQ_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_STQ_OFFSET; goto extract_fmt_stq_offset; + case 4 : itype = I960BASE_INSN_STQ_INDIRECT; goto extract_fmt_stq_indirect; + case 7 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX; goto extract_fmt_stq_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_STQ_INDIRECT_OFFSET; goto extract_fmt_stq_indirect_offset; + case 12 : itype = I960BASE_INSN_STQ_DISP; goto extract_fmt_stq_disp; + case 13 : itype = I960BASE_INSN_STQ_INDIRECT_DISP; goto extract_fmt_stq_indirect_disp; + case 14 : itype = I960BASE_INSN_STQ_INDEX_DISP; goto extract_fmt_stq_index_disp; + case 15 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX_DISP; goto extract_fmt_stq_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 192) : + } + case 192 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, - { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, - { I (INSN_LDIB_INDIRECT), E (FMT_LDIB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIB_INDIRECT_INDEX), E (FMT_LDIB_INDIRECT_INDEX) }, - { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, - { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, - { I (INSN_LDIB_DISP), E (FMT_LDIB_DISP) }, { I (INSN_LDIB_INDIRECT_DISP), E (FMT_LDIB_INDIRECT_DISP) }, - { I (INSN_LDIB_INDEX_DISP), E (FMT_LDIB_INDEX_DISP) }, { I (INSN_LDIB_INDIRECT_INDEX_DISP), E (FMT_LDIB_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDIB_OFFSET; goto extract_fmt_ldib_offset; + case 4 : itype = I960BASE_INSN_LDIB_INDIRECT; goto extract_fmt_ldib_indirect; + case 7 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX; goto extract_fmt_ldib_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDIB_INDIRECT_OFFSET; goto extract_fmt_ldib_indirect_offset; + case 12 : itype = I960BASE_INSN_LDIB_DISP; goto extract_fmt_ldib_disp; + case 13 : itype = I960BASE_INSN_LDIB_INDIRECT_DISP; goto extract_fmt_ldib_indirect_disp; + case 14 : itype = I960BASE_INSN_LDIB_INDEX_DISP; goto extract_fmt_ldib_index_disp; + case 15 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP; goto extract_fmt_ldib_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 200) : + } + case 200 : + { + unsigned int val = (((insn >> 10) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, - { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, - { I (INSN_LDIS_INDIRECT), E (FMT_LDIS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIS_INDIRECT_INDEX), E (FMT_LDIS_INDIRECT_INDEX) }, - { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, - { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, - { I (INSN_LDIS_DISP), E (FMT_LDIS_DISP) }, { I (INSN_LDIS_INDIRECT_DISP), E (FMT_LDIS_INDIRECT_DISP) }, - { I (INSN_LDIS_INDEX_DISP), E (FMT_LDIS_INDEX_DISP) }, { I (INSN_LDIS_INDIRECT_INDEX_DISP), E (FMT_LDIS_INDIRECT_INDEX_DISP) }, - }; - unsigned int val = (((insn >> 10) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : /* fall through */ + case 1 : /* fall through */ + case 2 : /* fall through */ + case 3 : itype = I960BASE_INSN_LDIS_OFFSET; goto extract_fmt_ldis_offset; + case 4 : itype = I960BASE_INSN_LDIS_INDIRECT; goto extract_fmt_ldis_indirect; + case 7 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX; goto extract_fmt_ldis_indirect_index; + case 8 : /* fall through */ + case 9 : /* fall through */ + case 10 : /* fall through */ + case 11 : itype = I960BASE_INSN_LDIS_INDIRECT_OFFSET; goto extract_fmt_ldis_indirect_offset; + case 12 : itype = I960BASE_INSN_LDIS_DISP; goto extract_fmt_ldis_disp; + case 13 : itype = I960BASE_INSN_LDIS_INDIRECT_DISP; goto extract_fmt_ldis_indirect_disp; + case 14 : itype = I960BASE_INSN_LDIS_INDEX_DISP; goto extract_fmt_ldis_index_disp; + case 15 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP; goto extract_fmt_ldis_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; } - DEFAULT (0) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); } - ENDSWITCH (0) + default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + } } -#undef I -#undef E } /* The instruction has been decoded, now extract the fields. */ - extract: - { -#ifndef __GNUC__ - switch (idecode->sfmt) -#endif - { - - CASE (ex, FMT_EMPTY) : + extract_fmt_empty: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_empty.f EXTRACT_IFMT_EMPTY_VARS /* */ @@ -1914,11 +1423,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULO) : + extract_fmt_mulo: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulo.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -1941,11 +1451,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULO1) : + extract_fmt_mulo1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulo1.f EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -1967,11 +1478,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULO2) : + extract_fmt_mulo2: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulo2.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -1993,11 +1505,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULO3) : + extract_fmt_mulo3: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulo3.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2018,11 +1531,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOTBIT) : + extract_fmt_notbit: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_notbit.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2045,11 +1559,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOTBIT1) : + extract_fmt_notbit1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_notbit1.f EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2071,11 +1586,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOTBIT2) : + extract_fmt_notbit2: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_notbit2.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2097,11 +1613,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOTBIT3) : + extract_fmt_notbit3: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_notbit3.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2122,11 +1639,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOT) : + extract_fmt_not: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_not.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2147,11 +1665,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOT1) : + extract_fmt_not1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_not1.f EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2171,11 +1690,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOT2) : + extract_fmt_not2: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_not2.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2196,11 +1716,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOT3) : + extract_fmt_not3: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_not3.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2220,11 +1741,120 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; + } + + extract_fmt_shlo: + { + const IDESC *idesc = &i960base_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.fmt_shlo.f + EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ + + EXTRACT_IFMT_MULO_CODE + + /* Record the fields for the semantic handler. */ + FLD (i_src1) = & CPU (h_gr)[f_src1]; + FLD (i_src2) = & CPU (h_gr)[f_src2]; + FLD (i_dst) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_src1; + FLD (in_src2) = f_src2; + FLD (out_dst) = f_srcdst; + } +#endif +#undef FLD + return idesc; + } + + extract_fmt_shlo1: + { + const IDESC *idesc = &i960base_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.fmt_shlo1.f + EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ + + EXTRACT_IFMT_MULO1_CODE + + /* Record the fields for the semantic handler. */ + FLD (f_src1) = f_src1; + FLD (i_src2) = & CPU (h_gr)[f_src2]; + FLD (i_dst) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src2) = f_src2; + FLD (out_dst) = f_srcdst; + } +#endif +#undef FLD + return idesc; } - CASE (ex, FMT_EMUL) : + extract_fmt_shlo2: { + const IDESC *idesc = &i960base_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.fmt_shlo2.f + EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ + + EXTRACT_IFMT_MULO2_CODE + + /* Record the fields for the semantic handler. */ + FLD (f_src2) = f_src2; + FLD (i_src1) = & CPU (h_gr)[f_src1]; + FLD (i_dst) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_src1) = f_src1; + FLD (out_dst) = f_srcdst; + } +#endif +#undef FLD + return idesc; + } + + extract_fmt_shlo3: + { + const IDESC *idesc = &i960base_insn_data[itype]; + CGEN_INSN_INT insn = base_insn; +#define FLD(f) abuf->fields.fmt_shlo3.f + EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ + + EXTRACT_IFMT_MULO3_CODE + + /* Record the fields for the semantic handler. */ + FLD (f_src1) = f_src1; + FLD (f_src2) = f_src2; + FLD (i_dst) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_dst) = f_srcdst; + } +#endif +#undef FLD + return idesc; + } + + extract_fmt_emul: + { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_emul.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2245,15 +1875,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_src1) = f_src1; FLD (in_src2) = f_src2; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EMUL1) : + extract_fmt_emul1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_emul1.f EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2273,15 +1904,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_src2) = f_src2; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EMUL2) : + extract_fmt_emul2: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_emul2.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2301,15 +1933,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_src1) = f_src1; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EMUL3) : + extract_fmt_emul3: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_emul3.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2328,15 +1961,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVL) : + extract_fmt_movl: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movl.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2354,18 +1988,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1)); + FLD (in_h_gr_add__VM_index_of_src1_1) = ((FLD (f_src1)) + (1)); FLD (in_src1) = f_src1; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVL1) : + extract_fmt_movl1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movl1.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2383,15 +2018,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVT) : + extract_fmt_movt: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movt.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2409,20 +2045,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1)); - FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2)); + FLD (in_h_gr_add__VM_index_of_src1_1) = ((FLD (f_src1)) + (1)); + FLD (in_h_gr_add__VM_index_of_src1_2) = ((FLD (f_src1)) + (2)); FLD (in_src1) = f_src1; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVT1) : + extract_fmt_movt1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movt1.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2440,16 +2077,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVQ) : + extract_fmt_movq: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movq.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2467,22 +2105,23 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1)); - FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2)); - FLD (in_h_gr_add__VM_index_of_src1_const__WI_3) = ((FLD (f_src1)) + (3)); + FLD (in_h_gr_add__VM_index_of_src1_1) = ((FLD (f_src1)) + (1)); + FLD (in_h_gr_add__VM_index_of_src1_2) = ((FLD (f_src1)) + (2)); + FLD (in_h_gr_add__VM_index_of_src1_3) = ((FLD (f_src1)) + (3)); FLD (in_src1) = f_src1; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVQ1) : + extract_fmt_movq1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movq1.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2500,17 +2139,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MODPC) : + extract_fmt_modpc: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_modpc.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -2531,11 +2171,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_OFFSET) : + extract_fmt_lda_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -2555,11 +2196,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_INDIRECT_OFFSET) : + extract_fmt_lda_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -2581,11 +2223,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_INDIRECT) : + extract_fmt_lda_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2606,11 +2249,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_INDIRECT_INDEX) : + extract_fmt_lda_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2634,11 +2278,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_DISP) : + extract_fmt_lda_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2658,11 +2303,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_INDIRECT_DISP) : + extract_fmt_lda_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2684,11 +2330,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_INDEX_DISP) : + extract_fmt_lda_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2711,11 +2358,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDA_INDIRECT_INDEX_DISP) : + extract_fmt_lda_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2740,11 +2388,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_OFFSET) : + extract_fmt_ld_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -2764,11 +2413,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_INDIRECT_OFFSET) : + extract_fmt_ld_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -2790,11 +2440,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_INDIRECT) : + extract_fmt_ld_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2815,11 +2466,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_INDIRECT_INDEX) : + extract_fmt_ld_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2843,11 +2495,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_DISP) : + extract_fmt_ld_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2867,11 +2520,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_INDIRECT_DISP) : + extract_fmt_ld_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2893,11 +2547,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_INDEX_DISP) : + extract_fmt_ld_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2920,11 +2575,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_INDIRECT_INDEX_DISP) : + extract_fmt_ld_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -2949,11 +2605,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_OFFSET) : + extract_fmt_ldob_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -2973,11 +2630,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_INDIRECT_OFFSET) : + extract_fmt_ldob_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -2999,11 +2657,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_INDIRECT) : + extract_fmt_ldob_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3024,11 +2683,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_INDIRECT_INDEX) : + extract_fmt_ldob_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3052,11 +2712,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_DISP) : + extract_fmt_ldob_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3076,11 +2737,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_INDIRECT_DISP) : + extract_fmt_ldob_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3102,11 +2764,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_INDEX_DISP) : + extract_fmt_ldob_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3129,11 +2792,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOB_INDIRECT_INDEX_DISP) : + extract_fmt_ldob_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3158,11 +2822,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_OFFSET) : + extract_fmt_ldos_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3182,11 +2847,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_INDIRECT_OFFSET) : + extract_fmt_ldos_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3208,11 +2874,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_INDIRECT) : + extract_fmt_ldos_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3233,11 +2900,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_INDIRECT_INDEX) : + extract_fmt_ldos_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3261,11 +2929,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_DISP) : + extract_fmt_ldos_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3285,11 +2954,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_INDIRECT_DISP) : + extract_fmt_ldos_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3311,11 +2981,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_INDEX_DISP) : + extract_fmt_ldos_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3338,11 +3009,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDOS_INDIRECT_INDEX_DISP) : + extract_fmt_ldos_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3367,11 +3039,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_OFFSET) : + extract_fmt_ldib_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3391,11 +3064,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_INDIRECT_OFFSET) : + extract_fmt_ldib_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3417,11 +3091,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_INDIRECT) : + extract_fmt_ldib_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3442,11 +3117,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_INDIRECT_INDEX) : + extract_fmt_ldib_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3470,11 +3146,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_DISP) : + extract_fmt_ldib_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3494,11 +3171,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_INDIRECT_DISP) : + extract_fmt_ldib_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3520,11 +3198,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_INDEX_DISP) : + extract_fmt_ldib_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3547,11 +3226,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIB_INDIRECT_INDEX_DISP) : + extract_fmt_ldib_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3576,11 +3256,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_OFFSET) : + extract_fmt_ldis_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3600,11 +3281,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_INDIRECT_OFFSET) : + extract_fmt_ldis_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3626,11 +3308,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_INDIRECT) : + extract_fmt_ldis_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3651,11 +3334,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_INDIRECT_INDEX) : + extract_fmt_ldis_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3679,11 +3363,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_DISP) : + extract_fmt_ldis_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3703,11 +3388,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_INDIRECT_DISP) : + extract_fmt_ldis_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3729,11 +3415,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_INDEX_DISP) : + extract_fmt_ldis_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3756,11 +3443,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDIS_INDIRECT_INDEX_DISP) : + extract_fmt_ldis_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3785,11 +3473,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_OFFSET) : + extract_fmt_ldl_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3807,15 +3496,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_INDIRECT_OFFSET) : + extract_fmt_ldl_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -3835,15 +3525,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_INDIRECT) : + extract_fmt_ldl_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3862,15 +3553,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_INDIRECT_INDEX) : + extract_fmt_ldl_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3892,15 +3584,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_DISP) : + extract_fmt_ldl_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3918,15 +3611,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_INDIRECT_DISP) : + extract_fmt_ldl_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3946,15 +3640,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_INDEX_DISP) : + extract_fmt_ldl_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -3975,15 +3670,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDL_INDIRECT_INDEX_DISP) : + extract_fmt_ldl_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4006,15 +3702,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_OFFSET) : + extract_fmt_ldt_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4032,16 +3729,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_INDIRECT_OFFSET) : + extract_fmt_ldt_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4061,16 +3759,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_INDIRECT) : + extract_fmt_ldt_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4089,16 +3788,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_INDIRECT_INDEX) : + extract_fmt_ldt_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4120,16 +3820,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_DISP) : + extract_fmt_ldt_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4147,16 +3848,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_INDIRECT_DISP) : + extract_fmt_ldt_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4176,16 +3878,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_INDEX_DISP) : + extract_fmt_ldt_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4206,16 +3909,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDT_INDIRECT_INDEX_DISP) : + extract_fmt_ldt_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4238,16 +3942,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_OFFSET) : + extract_fmt_ldq_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4265,17 +3970,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_INDIRECT_OFFSET) : + extract_fmt_ldq_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4295,17 +4001,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_INDIRECT) : + extract_fmt_ldq_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4324,17 +4031,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_INDIRECT_INDEX) : + extract_fmt_ldq_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4356,17 +4064,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_DISP) : + extract_fmt_ldq_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4384,17 +4093,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_INDIRECT_DISP) : + extract_fmt_ldq_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4414,17 +4124,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_INDEX_DISP) : + extract_fmt_ldq_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4445,17 +4156,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDQ_INDIRECT_INDEX_DISP) : + extract_fmt_ldq_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4478,17 +4190,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_OFFSET) : + extract_fmt_st_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4508,11 +4221,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_INDIRECT_OFFSET) : + extract_fmt_st_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_indirect_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4534,11 +4248,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_INDIRECT) : + extract_fmt_st_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_indirect.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4559,11 +4274,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_INDIRECT_INDEX) : + extract_fmt_st_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_indirect_index.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4587,11 +4303,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_DISP) : + extract_fmt_st_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4611,11 +4328,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_INDIRECT_DISP) : + extract_fmt_st_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_indirect_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4637,11 +4355,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_INDEX_DISP) : + extract_fmt_st_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4664,11 +4383,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_INDIRECT_INDEX_DISP) : + extract_fmt_st_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4693,11 +4413,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_OFFSET) : + extract_fmt_stob_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4717,11 +4438,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_INDIRECT_OFFSET) : + extract_fmt_stob_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_indirect_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4743,11 +4465,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_INDIRECT) : + extract_fmt_stob_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_indirect.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4768,11 +4491,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_INDIRECT_INDEX) : + extract_fmt_stob_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_indirect_index.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4796,11 +4520,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_DISP) : + extract_fmt_stob_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4820,11 +4545,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_INDIRECT_DISP) : + extract_fmt_stob_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_indirect_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4846,11 +4572,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_INDEX_DISP) : + extract_fmt_stob_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4873,11 +4600,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOB_INDIRECT_INDEX_DISP) : + extract_fmt_stob_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4902,11 +4630,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_OFFSET) : + extract_fmt_stos_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4926,11 +4655,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_INDIRECT_OFFSET) : + extract_fmt_stos_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_indirect_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -4952,11 +4682,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_INDIRECT) : + extract_fmt_stos_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_indirect.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -4977,11 +4708,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_INDIRECT_INDEX) : + extract_fmt_stos_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_indirect_index.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5005,11 +4737,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_DISP) : + extract_fmt_stos_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5029,11 +4762,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_INDIRECT_DISP) : + extract_fmt_stos_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_indirect_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5055,11 +4789,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_INDEX_DISP) : + extract_fmt_stos_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5082,11 +4817,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STOS_INDIRECT_INDEX_DISP) : + extract_fmt_stos_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5111,11 +4847,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_OFFSET) : + extract_fmt_stl_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -5132,16 +4869,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_INDIRECT_OFFSET) : + extract_fmt_stl_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_indirect_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -5160,16 +4898,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_INDIRECT) : + extract_fmt_stl_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_indirect.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5187,16 +4926,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_INDIRECT_INDEX) : + extract_fmt_stl_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_indirect_index.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5216,17 +4956,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_DISP) : + extract_fmt_stl_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5243,16 +4984,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_INDIRECT_DISP) : + extract_fmt_stl_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_indirect_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5271,16 +5013,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_INDEX_DISP) : + extract_fmt_stl_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5299,17 +5042,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STL_INDIRECT_INDEX_DISP) : + extract_fmt_stl_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5330,17 +5074,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_OFFSET) : + extract_fmt_stt_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -5357,17 +5102,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_INDIRECT_OFFSET) : + extract_fmt_stt_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_indirect_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -5386,17 +5132,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_INDIRECT) : + extract_fmt_stt_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_indirect.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5414,17 +5161,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_INDIRECT_INDEX) : + extract_fmt_stt_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_indirect_index.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5444,18 +5192,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_DISP) : + extract_fmt_stt_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5472,17 +5221,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_INDIRECT_DISP) : + extract_fmt_stt_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_indirect_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5501,17 +5251,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_INDEX_DISP) : + extract_fmt_stt_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5530,18 +5281,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STT_INDIRECT_INDEX_DISP) : + extract_fmt_stt_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5562,18 +5314,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_OFFSET) : + extract_fmt_stq_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -5590,18 +5343,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_INDIRECT_OFFSET) : + extract_fmt_stq_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_indirect_offset.f EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -5620,18 +5374,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_INDIRECT) : + extract_fmt_stq_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_indirect.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5649,18 +5404,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_INDIRECT_INDEX) : + extract_fmt_stq_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_indirect_index.f EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5680,19 +5436,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_DISP) : + extract_fmt_stq_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5709,18 +5466,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_INDIRECT_DISP) : + extract_fmt_stq_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_indirect_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5739,18 +5497,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_INDEX_DISP) : + extract_fmt_stq_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5769,19 +5528,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STQ_INDIRECT_INDEX_DISP) : + extract_fmt_stq_indirect_index_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -5802,19 +5562,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3)); FLD (in_index) = f_index; FLD (in_st_src) = f_srcdst; } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPOBE_REG) : + extract_fmt_cmpobe_reg: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -5837,11 +5598,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPOBE_LIT) : + extract_fmt_cmpobe_lit: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -5863,11 +5625,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPOBL_REG) : + extract_fmt_cmpobl_reg: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -5890,11 +5653,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPOBL_LIT) : + extract_fmt_cmpobl_lit: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -5916,11 +5680,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BBC_REG) : + extract_fmt_bbc_reg: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -5943,11 +5708,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BBC_LIT) : + extract_fmt_bbc_lit: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -5969,11 +5735,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI) : + extract_fmt_cmpi: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpi.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -5994,11 +5761,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI1) : + extract_fmt_cmpi1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpi1.f EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6018,11 +5786,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI2) : + extract_fmt_cmpi2: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpi2.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6042,11 +5811,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI3) : + extract_fmt_cmpi3: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpi3.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6065,11 +5835,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPO) : + extract_fmt_cmpo: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpo.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6090,11 +5861,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPO1) : + extract_fmt_cmpo1: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpo1.f EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6114,11 +5886,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPO2) : + extract_fmt_cmpo2: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpo2.f EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6138,11 +5911,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPO3) : + extract_fmt_cmpo3: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpo3.f EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6161,11 +5935,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_TESTNO_REG) : + extract_fmt_testno_reg: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_testno_reg.f EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ @@ -6184,11 +5959,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BNO) : + extract_fmt_bno: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bno.f EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ @@ -6207,11 +5983,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_B) : + extract_fmt_b: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_b.f EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ @@ -6230,11 +6007,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BX_INDIRECT_OFFSET) : + extract_fmt_bx_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -6255,11 +6033,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BX_INDIRECT) : + extract_fmt_bx_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -6279,11 +6058,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BX_INDIRECT_INDEX) : + extract_fmt_bx_indirect_index: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -6306,11 +6086,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BX_DISP) : + extract_fmt_bx_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -6329,11 +6110,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BX_INDIRECT_DISP) : + extract_fmt_bx_indirect_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -6354,11 +6136,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALLX_DISP) : + extract_fmt_callx_disp: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -6411,11 +6194,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALLX_INDIRECT) : + extract_fmt_callx_indirect: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ @@ -6469,11 +6253,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALLX_INDIRECT_OFFSET) : + extract_fmt_callx_indirect_offset: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ @@ -6528,11 +6313,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RET) : + extract_fmt_ret: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_ret.f EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ @@ -6570,11 +6356,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALLS) : + extract_fmt_calls: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_calls.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6594,11 +6381,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_FMARK) : + extract_fmt_fmark: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_fmark.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6616,11 +6404,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_FLUSHREG) : + extract_fmt_flushreg: { + const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_flushreg.f EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ @@ -6631,14 +6420,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_flushreg", (char *) 0)); #undef FLD - BREAK (ex); - } - - - } - ENDSWITCH (ex) - + return idesc; } - return idecode->idesc; } diff --git a/sim/i960/decode.h b/sim/i960/decode.h index 6137217..80fbde6 100644 --- a/sim/i960/decode.h +++ b/sim/i960/decode.h @@ -48,8 +48,10 @@ typedef enum i960base_insn_type { , I960BASE_INSN_NOTAND2, I960BASE_INSN_NOTAND3, I960BASE_INSN_XOR, I960BASE_INSN_XOR1 , I960BASE_INSN_XOR2, I960BASE_INSN_XOR3, I960BASE_INSN_OR, I960BASE_INSN_OR1 , I960BASE_INSN_OR2, I960BASE_INSN_OR3, I960BASE_INSN_NOR, I960BASE_INSN_NOR1 - , I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1 - , I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1 + , I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_XNOR, I960BASE_INSN_XNOR1 + , I960BASE_INSN_XNOR2, I960BASE_INSN_XNOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1 + , I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_ORNOT, I960BASE_INSN_ORNOT1 + , I960BASE_INSN_ORNOT2, I960BASE_INSN_ORNOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1 , I960BASE_INSN_CLRBIT2, I960BASE_INSN_CLRBIT3, I960BASE_INSN_SHLO, I960BASE_INSN_SHLO1 , I960BASE_INSN_SHLO2, I960BASE_INSN_SHLO3, I960BASE_INSN_SHRO, I960BASE_INSN_SHRO1 , I960BASE_INSN_SHRO2, I960BASE_INSN_SHRO3, I960BASE_INSN_SHLI, I960BASE_INSN_SHLI1 @@ -192,10 +194,18 @@ SEM (nor) SEM (nor1) SEM (nor2) SEM (nor3) +SEM (xnor) +SEM (xnor1) +SEM (xnor2) +SEM (xnor3) SEM (not) SEM (not1) SEM (not2) SEM (not3) +SEM (ornot) +SEM (ornot1) +SEM (ornot2) +SEM (ornot3) SEM (clrbit) SEM (clrbit1) SEM (clrbit2) diff --git a/sim/i960/devices.c b/sim/i960/devices.c index d34e672..0a47569 100644 --- a/sim/i960/devices.c +++ b/sim/i960/devices.c @@ -32,10 +32,8 @@ device i960_devices; int device_io_read_buffer (device *me, void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) return nr_bytes; @@ -70,10 +68,8 @@ device_io_read_buffer (device *me, void *source, int space, int device_io_write_buffer (device *me, const void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - #if WITH_SCACHE /* MSPR support is deprecated but is kept in for upward compatibility with existing overlay support. */ @@ -105,4 +101,7 @@ device_io_write_buffer (device *me, const void *source, int space, return nr_bytes; } -void device_error () {} +void +device_error (device *me, char *message, ...) +{ +} diff --git a/sim/i960/i960-desc.c b/sim/i960/i960-desc.c index 6ea8fdc..8c1ca64 100644 --- a/sim/i960/i960-desc.c +++ b/sim/i960/i960-desc.c @@ -25,6 +25,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sysdep.h" #include <ctype.h> #include <stdio.h> +#include <stdarg.h> #include "ansidecl.h" #include "bfd.h" #include "symcat.h" @@ -50,15 +51,22 @@ static const CGEN_ATTR_ENTRY MACH_attr[] = { 0, 0 } }; +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "i960", ISA_I960 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] = { { "MACH", & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, { "RESERVED", &bool_attr[0], &bool_attr[0] }, { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; @@ -66,10 +74,7 @@ const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] = { { "MACH", & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, - { "SIGNED", &bool_attr[0], &bool_attr[0] }, { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, - { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] }, { "PC", &bool_attr[0], &bool_attr[0] }, { "PROFILE", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } @@ -79,10 +84,10 @@ const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] = { { "MACH", & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNSIGNED", &bool_attr[0], &bool_attr[0] }, { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, { "RELAX", &bool_attr[0], &bool_attr[0] }, { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, @@ -105,7 +110,22 @@ const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] = { 0, 0, 0 } }; -CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = +/* Instruction set variants. */ + +static const CGEN_ISA i960_cgen_isa_table[] = { + { "i960", 32, 32, 32, 64, }, + { 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH i960_cgen_mach_table[] = { + { "i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA }, + { "i960:ca", "i960:ca", MACH_I960_CA }, + { 0 } +}; + +static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = { { "fp", 31 }, { "sp", 1 }, @@ -143,18 +163,18 @@ CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = { "g15", 31 } }; -CGEN_KEYWORD i960_cgen_opval_h_gr = +CGEN_KEYWORD i960_cgen_opval_h_gr = { & i960_cgen_opval_h_gr_entries[0], 34 }; -CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] = +static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] = { { "cc", 0 } }; -CGEN_KEYWORD i960_cgen_opval_h_cc = +CGEN_KEYWORD i960_cgen_opval_h_cc = { & i960_cgen_opval_h_cc_entries[0], 1 @@ -164,57 +184,55 @@ CGEN_KEYWORD i960_cgen_opval_h_cc = /* The hardware table. */ -#define A(a) (1 << (CONCAT2 (CGEN_HW_,a) - CGEN_ATTR_BOOL_OFFSET)) -#define HW_ENT(n) i960_cgen_hw_table[n] +#define A(a) (1 << CONCAT2 (CGEN_HW_,a)) const CGEN_HW_ENTRY i960_cgen_hw_table[] = { - { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, - { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, - { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } }, { 0 } }; -/* don't undef HW_ENT, used later */ #undef A /* The instruction field table. */ -#define A(a) (1 << (CONCAT2 (CGEN_IFLD_,a) - CGEN_ATTR_BOOL_OFFSET)) +#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a)) const CGEN_IFLD i960_cgen_ifld_table[] = { - { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } }, - { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, - { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, - { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, + { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, { (1<<MACH_BASE) } } }, + { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } } }, + { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } }, + { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE) } } }, + { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, { (1<<MACH_BASE) } } }, + { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, + { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } } }, + { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } }, + { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } }, + { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, { (1<<MACH_BASE) } } }, + { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } } }, + { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } }, + { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, { (1<<MACH_BASE) } } }, + { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } } }, + { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } } }, + { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } } }, + { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } } }, { 0 } }; @@ -222,67 +240,68 @@ const CGEN_IFLD i960_cgen_ifld_table[] = /* The operand table. */ -#define A(a) (1 << (CONCAT2 (CGEN_OPERAND_,a) - CGEN_ATTR_BOOL_OFFSET)) +#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a)) #define OPERAND(op) CONCAT2 (I960_OPERAND_,op) -const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] = +const CGEN_OPERAND i960_cgen_operand_table[] = { /* pc: program counter */ - { "pc", & HW_ENT (HW_H_PC), 0, 0, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { "pc", I960_OPERAND_PC, HW_H_PC, 0, 0, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* src1: source register 1 */ - { "src1", & HW_ENT (HW_H_GR), 27, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "src1", I960_OPERAND_SRC1, HW_H_GR, 27, 5, + { 0, { (1<<MACH_BASE) } } }, /* src2: source register 2 */ - { "src2", & HW_ENT (HW_H_GR), 13, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "src2", I960_OPERAND_SRC2, HW_H_GR, 13, 5, + { 0, { (1<<MACH_BASE) } } }, /* dst: source/dest register */ - { "dst", & HW_ENT (HW_H_GR), 8, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "dst", I960_OPERAND_DST, HW_H_GR, 8, 5, + { 0, { (1<<MACH_BASE) } } }, /* lit1: literal 1 */ - { "lit1", & HW_ENT (HW_H_UINT), 27, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "lit1", I960_OPERAND_LIT1, HW_H_UINT, 27, 5, + { 0, { (1<<MACH_BASE) } } }, /* lit2: literal 2 */ - { "lit2", & HW_ENT (HW_H_UINT), 13, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "lit2", I960_OPERAND_LIT2, HW_H_UINT, 13, 5, + { 0, { (1<<MACH_BASE) } } }, /* st_src: store src */ - { "st_src", & HW_ENT (HW_H_GR), 8, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "st_src", I960_OPERAND_ST_SRC, HW_H_GR, 8, 5, + { 0, { (1<<MACH_BASE) } } }, /* abase: abase */ - { "abase", & HW_ENT (HW_H_GR), 13, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "abase", I960_OPERAND_ABASE, HW_H_GR, 13, 5, + { 0, { (1<<MACH_BASE) } } }, /* offset: offset */ - { "offset", & HW_ENT (HW_H_UINT), 20, 12, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "offset", I960_OPERAND_OFFSET, HW_H_UINT, 20, 12, + { 0, { (1<<MACH_BASE) } } }, /* scale: scale */ - { "scale", & HW_ENT (HW_H_UINT), 22, 3, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "scale", I960_OPERAND_SCALE, HW_H_UINT, 22, 3, + { 0, { (1<<MACH_BASE) } } }, /* index: index */ - { "index", & HW_ENT (HW_H_GR), 27, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "index", I960_OPERAND_INDEX, HW_H_GR, 27, 5, + { 0, { (1<<MACH_BASE) } } }, /* optdisp: optional displacement */ - { "optdisp", & HW_ENT (HW_H_UINT), 0, 32, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "optdisp", I960_OPERAND_OPTDISP, HW_H_UINT, 0, 32, + { 0, { (1<<MACH_BASE) } } }, /* br_src1: branch src1 */ - { "br_src1", & HW_ENT (HW_H_GR), 8, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "br_src1", I960_OPERAND_BR_SRC1, HW_H_GR, 8, 5, + { 0, { (1<<MACH_BASE) } } }, /* br_src2: branch src2 */ - { "br_src2", & HW_ENT (HW_H_GR), 13, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "br_src2", I960_OPERAND_BR_SRC2, HW_H_GR, 13, 5, + { 0, { (1<<MACH_BASE) } } }, /* br_disp: branch displacement */ - { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { "br_disp", I960_OPERAND_BR_DISP, HW_H_IADDR, 19, 11, + { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* br_lit1: branch literal 1 */ - { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } }, + { "br_lit1", I960_OPERAND_BR_LIT1, HW_H_UINT, 8, 5, + { 0, { (1<<MACH_BASE) } } }, /* ctrl_disp: ctrl branch disp */ - { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22, - { CGEN_OPERAND_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { "ctrl_disp", I960_OPERAND_CTRL_DISP, HW_H_IADDR, 8, 22, + { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { 0 } }; #undef A -#define A(a) (1 << (CONCAT2 (CGEN_INSN_,a) - CGEN_ATTR_BOOL_OFFSET)) +#define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) /* The instruction table. */ @@ -296,1417 +315,1457 @@ static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] = /* mulo $src1, $src2, $dst */ { I960_INSN_MULO, "mulo", "mulo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* mulo $lit1, $src2, $dst */ { I960_INSN_MULO1, "mulo1", "mulo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* mulo $src1, $lit2, $dst */ { I960_INSN_MULO2, "mulo2", "mulo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* mulo $lit1, $lit2, $dst */ { I960_INSN_MULO3, "mulo3", "mulo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remo $src1, $src2, $dst */ { I960_INSN_REMO, "remo", "remo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remo $lit1, $src2, $dst */ { I960_INSN_REMO1, "remo1", "remo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remo $src1, $lit2, $dst */ { I960_INSN_REMO2, "remo2", "remo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remo $lit1, $lit2, $dst */ { I960_INSN_REMO3, "remo3", "remo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divo $src1, $src2, $dst */ { I960_INSN_DIVO, "divo", "divo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divo $lit1, $src2, $dst */ { I960_INSN_DIVO1, "divo1", "divo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divo $src1, $lit2, $dst */ { I960_INSN_DIVO2, "divo2", "divo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divo $lit1, $lit2, $dst */ { I960_INSN_DIVO3, "divo3", "divo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remi $src1, $src2, $dst */ { I960_INSN_REMI, "remi", "remi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remi $lit1, $src2, $dst */ { I960_INSN_REMI1, "remi1", "remi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remi $src1, $lit2, $dst */ { I960_INSN_REMI2, "remi2", "remi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* remi $lit1, $lit2, $dst */ { I960_INSN_REMI3, "remi3", "remi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divi $src1, $src2, $dst */ { I960_INSN_DIVI, "divi", "divi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divi $lit1, $src2, $dst */ { I960_INSN_DIVI1, "divi1", "divi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divi $src1, $lit2, $dst */ { I960_INSN_DIVI2, "divi2", "divi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* divi $lit1, $lit2, $dst */ { I960_INSN_DIVI3, "divi3", "divi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* addo $src1, $src2, $dst */ { I960_INSN_ADDO, "addo", "addo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* addo $lit1, $src2, $dst */ { I960_INSN_ADDO1, "addo1", "addo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* addo $src1, $lit2, $dst */ { I960_INSN_ADDO2, "addo2", "addo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* addo $lit1, $lit2, $dst */ { I960_INSN_ADDO3, "addo3", "addo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* subo $src1, $src2, $dst */ { I960_INSN_SUBO, "subo", "subo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* subo $lit1, $src2, $dst */ { I960_INSN_SUBO1, "subo1", "subo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* subo $src1, $lit2, $dst */ { I960_INSN_SUBO2, "subo2", "subo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* subo $lit1, $lit2, $dst */ { I960_INSN_SUBO3, "subo3", "subo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notbit $src1, $src2, $dst */ { I960_INSN_NOTBIT, "notbit", "notbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notbit $lit1, $src2, $dst */ { I960_INSN_NOTBIT1, "notbit1", "notbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notbit $src1, $lit2, $dst */ { I960_INSN_NOTBIT2, "notbit2", "notbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notbit $lit1, $lit2, $dst */ { I960_INSN_NOTBIT3, "notbit3", "notbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* and $src1, $src2, $dst */ { I960_INSN_AND, "and", "and", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* and $lit1, $src2, $dst */ { I960_INSN_AND1, "and1", "and", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* and $src1, $lit2, $dst */ { I960_INSN_AND2, "and2", "and", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* and $lit1, $lit2, $dst */ { I960_INSN_AND3, "and3", "and", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* andnot $src1, $src2, $dst */ { I960_INSN_ANDNOT, "andnot", "andnot", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* andnot $lit1, $src2, $dst */ { I960_INSN_ANDNOT1, "andnot1", "andnot", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* andnot $src1, $lit2, $dst */ { I960_INSN_ANDNOT2, "andnot2", "andnot", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* andnot $lit1, $lit2, $dst */ { I960_INSN_ANDNOT3, "andnot3", "andnot", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* setbit $src1, $src2, $dst */ { I960_INSN_SETBIT, "setbit", "setbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* setbit $lit1, $src2, $dst */ { I960_INSN_SETBIT1, "setbit1", "setbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* setbit $src1, $lit2, $dst */ { I960_INSN_SETBIT2, "setbit2", "setbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* setbit $lit1, $lit2, $dst */ { I960_INSN_SETBIT3, "setbit3", "setbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notand $src1, $src2, $dst */ { I960_INSN_NOTAND, "notand", "notand", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notand $lit1, $src2, $dst */ { I960_INSN_NOTAND1, "notand1", "notand", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notand $src1, $lit2, $dst */ { I960_INSN_NOTAND2, "notand2", "notand", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* notand $lit1, $lit2, $dst */ { I960_INSN_NOTAND3, "notand3", "notand", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* xor $src1, $src2, $dst */ { I960_INSN_XOR, "xor", "xor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* xor $lit1, $src2, $dst */ { I960_INSN_XOR1, "xor1", "xor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* xor $src1, $lit2, $dst */ { I960_INSN_XOR2, "xor2", "xor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* xor $lit1, $lit2, $dst */ { I960_INSN_XOR3, "xor3", "xor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* or $src1, $src2, $dst */ { I960_INSN_OR, "or", "or", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* or $lit1, $src2, $dst */ { I960_INSN_OR1, "or1", "or", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* or $src1, $lit2, $dst */ { I960_INSN_OR2, "or2", "or", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* or $lit1, $lit2, $dst */ { I960_INSN_OR3, "or3", "or", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* nor $src1, $src2, $dst */ { I960_INSN_NOR, "nor", "nor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* nor $lit1, $src2, $dst */ { I960_INSN_NOR1, "nor1", "nor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* nor $src1, $lit2, $dst */ { I960_INSN_NOR2, "nor2", "nor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* nor $lit1, $lit2, $dst */ { I960_INSN_NOR3, "nor3", "nor", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } + }, +/* xnor $src1, $src2, $dst */ + { + I960_INSN_XNOR, "xnor", "xnor", 32, + { 0, { (1<<MACH_BASE) } } + }, +/* xnor $lit1, $src2, $dst */ + { + I960_INSN_XNOR1, "xnor1", "xnor", 32, + { 0, { (1<<MACH_BASE) } } + }, +/* xnor $src1, $lit2, $dst */ + { + I960_INSN_XNOR2, "xnor2", "xnor", 32, + { 0, { (1<<MACH_BASE) } } + }, +/* xnor $lit1, $lit2, $dst */ + { + I960_INSN_XNOR3, "xnor3", "xnor", 32, + { 0, { (1<<MACH_BASE) } } }, /* not $src1, $src2, $dst */ { I960_INSN_NOT, "not", "not", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* not $lit1, $src2, $dst */ { I960_INSN_NOT1, "not1", "not", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* not $src1, $lit2, $dst */ { I960_INSN_NOT2, "not2", "not", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* not $lit1, $lit2, $dst */ { I960_INSN_NOT3, "not3", "not", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } + }, +/* ornot $src1, $src2, $dst */ + { + I960_INSN_ORNOT, "ornot", "ornot", 32, + { 0, { (1<<MACH_BASE) } } + }, +/* ornot $lit1, $src2, $dst */ + { + I960_INSN_ORNOT1, "ornot1", "ornot", 32, + { 0, { (1<<MACH_BASE) } } + }, +/* ornot $src1, $lit2, $dst */ + { + I960_INSN_ORNOT2, "ornot2", "ornot", 32, + { 0, { (1<<MACH_BASE) } } + }, +/* ornot $lit1, $lit2, $dst */ + { + I960_INSN_ORNOT3, "ornot3", "ornot", 32, + { 0, { (1<<MACH_BASE) } } }, /* clrbit $src1, $src2, $dst */ { I960_INSN_CLRBIT, "clrbit", "clrbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* clrbit $lit1, $src2, $dst */ { I960_INSN_CLRBIT1, "clrbit1", "clrbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* clrbit $src1, $lit2, $dst */ { I960_INSN_CLRBIT2, "clrbit2", "clrbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* clrbit $lit1, $lit2, $dst */ { I960_INSN_CLRBIT3, "clrbit3", "clrbit", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shlo $src1, $src2, $dst */ { I960_INSN_SHLO, "shlo", "shlo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shlo $lit1, $src2, $dst */ { I960_INSN_SHLO1, "shlo1", "shlo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shlo $src1, $lit2, $dst */ { I960_INSN_SHLO2, "shlo2", "shlo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shlo $lit1, $lit2, $dst */ { I960_INSN_SHLO3, "shlo3", "shlo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shro $src1, $src2, $dst */ { I960_INSN_SHRO, "shro", "shro", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shro $lit1, $src2, $dst */ { I960_INSN_SHRO1, "shro1", "shro", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shro $src1, $lit2, $dst */ { I960_INSN_SHRO2, "shro2", "shro", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shro $lit1, $lit2, $dst */ { I960_INSN_SHRO3, "shro3", "shro", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shli $src1, $src2, $dst */ { I960_INSN_SHLI, "shli", "shli", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shli $lit1, $src2, $dst */ { I960_INSN_SHLI1, "shli1", "shli", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shli $src1, $lit2, $dst */ { I960_INSN_SHLI2, "shli2", "shli", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shli $lit1, $lit2, $dst */ { I960_INSN_SHLI3, "shli3", "shli", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shri $src1, $src2, $dst */ { I960_INSN_SHRI, "shri", "shri", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shri $lit1, $src2, $dst */ { I960_INSN_SHRI1, "shri1", "shri", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shri $src1, $lit2, $dst */ { I960_INSN_SHRI2, "shri2", "shri", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* shri $lit1, $lit2, $dst */ { I960_INSN_SHRI3, "shri3", "shri", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* emul $src1, $src2, $dst */ { I960_INSN_EMUL, "emul", "emul", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* emul $lit1, $src2, $dst */ { I960_INSN_EMUL1, "emul1", "emul", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* emul $src1, $lit2, $dst */ { I960_INSN_EMUL2, "emul2", "emul", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* emul $lit1, $lit2, $dst */ { I960_INSN_EMUL3, "emul3", "emul", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* mov $src1, $dst */ { I960_INSN_MOV, "mov", "mov", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* mov $lit1, $dst */ { I960_INSN_MOV1, "mov1", "mov", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* movl $src1, $dst */ { I960_INSN_MOVL, "movl", "movl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* movl $lit1, $dst */ { I960_INSN_MOVL1, "movl1", "movl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* movt $src1, $dst */ { I960_INSN_MOVT, "movt", "movt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* movt $lit1, $dst */ { I960_INSN_MOVT1, "movt1", "movt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* movq $src1, $dst */ { I960_INSN_MOVQ, "movq", "movq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* movq $lit1, $dst */ { I960_INSN_MOVQ1, "movq1", "movq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* modpc $src1, $src2, $dst */ { I960_INSN_MODPC, "modpc", "modpc", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* modac $src1, $src2, $dst */ { I960_INSN_MODAC, "modac", "modac", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda $offset, $dst */ { I960_INSN_LDA_OFFSET, "lda-offset", "lda", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda $offset($abase), $dst */ { I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda ($abase), $dst */ { I960_INSN_LDA_INDIRECT, "lda-indirect", "lda", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda ($abase)[$index*S$scale], $dst */ { I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda $optdisp, $dst */ { I960_INSN_LDA_DISP, "lda-disp", "lda", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda $optdisp($abase), $dst */ { I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda $optdisp[$index*S$scale], $dst */ { I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* lda $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld $offset, $dst */ { I960_INSN_LD_OFFSET, "ld-offset", "ld", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld $offset($abase), $dst */ { I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld ($abase), $dst */ { I960_INSN_LD_INDIRECT, "ld-indirect", "ld", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld ($abase)[$index*S$scale], $dst */ { I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld $optdisp, $dst */ { I960_INSN_LD_DISP, "ld-disp", "ld", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld $optdisp($abase), $dst */ { I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld $optdisp[$index*S$scale], $dst */ { I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ld $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob $offset, $dst */ { I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob $offset($abase), $dst */ { I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob ($abase), $dst */ { I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob ($abase)[$index*S$scale], $dst */ { I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob $optdisp, $dst */ { I960_INSN_LDOB_DISP, "ldob-disp", "ldob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob $optdisp($abase), $dst */ { I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob $optdisp[$index*S$scale], $dst */ { I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldob $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos $offset, $dst */ { I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos $offset($abase), $dst */ { I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos ($abase), $dst */ { I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos ($abase)[$index*S$scale], $dst */ { I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos $optdisp, $dst */ { I960_INSN_LDOS_DISP, "ldos-disp", "ldos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos $optdisp($abase), $dst */ { I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos $optdisp[$index*S$scale], $dst */ { I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldos $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib $offset, $dst */ { I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib $offset($abase), $dst */ { I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib ($abase), $dst */ { I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib ($abase)[$index*S$scale], $dst */ { I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib $optdisp, $dst */ { I960_INSN_LDIB_DISP, "ldib-disp", "ldib", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib $optdisp($abase), $dst */ { I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib $optdisp[$index*S$scale], $dst */ { I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldib $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis $offset, $dst */ { I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis $offset($abase), $dst */ { I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis ($abase), $dst */ { I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis ($abase)[$index*S$scale], $dst */ { I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis $optdisp, $dst */ { I960_INSN_LDIS_DISP, "ldis-disp", "ldis", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis $optdisp($abase), $dst */ { I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis $optdisp[$index*S$scale], $dst */ { I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldis $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl $offset, $dst */ { I960_INSN_LDL_OFFSET, "ldl-offset", "ldl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl $offset($abase), $dst */ { I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl ($abase), $dst */ { I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl ($abase)[$index*S$scale], $dst */ { I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl $optdisp, $dst */ { I960_INSN_LDL_DISP, "ldl-disp", "ldl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl $optdisp($abase), $dst */ { I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl $optdisp[$index*S$scale], $dst */ { I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldl $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt $offset, $dst */ { I960_INSN_LDT_OFFSET, "ldt-offset", "ldt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt $offset($abase), $dst */ { I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt ($abase), $dst */ { I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt ($abase)[$index*S$scale], $dst */ { I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt $optdisp, $dst */ { I960_INSN_LDT_DISP, "ldt-disp", "ldt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt $optdisp($abase), $dst */ { I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt $optdisp[$index*S$scale], $dst */ { I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldt $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq $offset, $dst */ { I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq $offset($abase), $dst */ { I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq ($abase), $dst */ { I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq ($abase)[$index*S$scale], $dst */ { I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq $optdisp, $dst */ { I960_INSN_LDQ_DISP, "ldq-disp", "ldq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq $optdisp($abase), $dst */ { I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq $optdisp[$index*S$scale], $dst */ { I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* ldq $optdisp($abase)[$index*S$scale], $dst */ { I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, $offset */ { I960_INSN_ST_OFFSET, "st-offset", "st", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, $offset($abase) */ { I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, ($abase) */ { I960_INSN_ST_INDIRECT, "st-indirect", "st", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, ($abase)[$index*S$scale] */ { I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, $optdisp */ { I960_INSN_ST_DISP, "st-disp", "st", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, $optdisp($abase) */ { I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, $optdisp[$index*S$scale */ { I960_INSN_ST_INDEX_DISP, "st-index-disp", "st", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* st $st_src, $optdisp($abase)[$index*S$scale] */ { I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, $offset */ { I960_INSN_STOB_OFFSET, "stob-offset", "stob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, $offset($abase) */ { I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, ($abase) */ { I960_INSN_STOB_INDIRECT, "stob-indirect", "stob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, ($abase)[$index*S$scale] */ { I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, $optdisp */ { I960_INSN_STOB_DISP, "stob-disp", "stob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, $optdisp($abase) */ { I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, $optdisp[$index*S$scale */ { I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stob $st_src, $optdisp($abase)[$index*S$scale] */ { I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, $offset */ { I960_INSN_STOS_OFFSET, "stos-offset", "stos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, $offset($abase) */ { I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, ($abase) */ { I960_INSN_STOS_INDIRECT, "stos-indirect", "stos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, ($abase)[$index*S$scale] */ { I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, $optdisp */ { I960_INSN_STOS_DISP, "stos-disp", "stos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, $optdisp($abase) */ { I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, $optdisp[$index*S$scale */ { I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stos $st_src, $optdisp($abase)[$index*S$scale] */ { I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, $offset */ { I960_INSN_STL_OFFSET, "stl-offset", "stl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, $offset($abase) */ { I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, ($abase) */ { I960_INSN_STL_INDIRECT, "stl-indirect", "stl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, ($abase)[$index*S$scale] */ { I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, $optdisp */ { I960_INSN_STL_DISP, "stl-disp", "stl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, $optdisp($abase) */ { I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, $optdisp[$index*S$scale */ { I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stl $st_src, $optdisp($abase)[$index*S$scale] */ { I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, $offset */ { I960_INSN_STT_OFFSET, "stt-offset", "stt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, $offset($abase) */ { I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, ($abase) */ { I960_INSN_STT_INDIRECT, "stt-indirect", "stt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, ($abase)[$index*S$scale] */ { I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, $optdisp */ { I960_INSN_STT_DISP, "stt-disp", "stt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, $optdisp($abase) */ { I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, $optdisp[$index*S$scale */ { I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stt $st_src, $optdisp($abase)[$index*S$scale] */ { I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, $offset */ { I960_INSN_STQ_OFFSET, "stq-offset", "stq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, $offset($abase) */ { I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, ($abase) */ { I960_INSN_STQ_INDIRECT, "stq-indirect", "stq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, ($abase)[$index*S$scale] */ { I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, $optdisp */ { I960_INSN_STQ_DISP, "stq-disp", "stq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, $optdisp($abase) */ { I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, $optdisp[$index*S$scale */ { I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* stq $st_src, $optdisp($abase)[$index*S$scale] */ { I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq", 64, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpobe $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobe $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobne $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobne $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobl $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobl $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpoble $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpoble $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobg $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobg $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobge $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpobge $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibe $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibe $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibne $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibne $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibl $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibl $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpible $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpible $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibg $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibg $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibge $br_src1, $br_src2, $br_disp */ { I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpibge $br_lit1, $br_src2, $br_disp */ { I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bbc $br_src1, $br_src2, $br_disp */ { I960_INSN_BBC_REG, "bbc-reg", "bbc", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bbc $br_lit1, $br_src2, $br_disp */ { I960_INSN_BBC_LIT, "bbc-lit", "bbc", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bbs $br_src1, $br_src2, $br_disp */ { I960_INSN_BBS_REG, "bbs-reg", "bbs", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bbs $br_lit1, $br_src2, $br_disp */ { I960_INSN_BBS_LIT, "bbs-lit", "bbs", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* cmpi $src1, $src2 */ { I960_INSN_CMPI, "cmpi", "cmpi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpi $lit1, $src2 */ { I960_INSN_CMPI1, "cmpi1", "cmpi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpi $src1, $lit2 */ { I960_INSN_CMPI2, "cmpi2", "cmpi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpi $lit1, $lit2 */ { I960_INSN_CMPI3, "cmpi3", "cmpi", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpo $src1, $src2 */ { I960_INSN_CMPO, "cmpo", "cmpo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpo $lit1, $src2 */ { I960_INSN_CMPO1, "cmpo1", "cmpo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpo $src1, $lit2 */ { I960_INSN_CMPO2, "cmpo2", "cmpo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* cmpo $lit1, $lit2 */ { I960_INSN_CMPO3, "cmpo3", "cmpo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testno $br_src1 */ { I960_INSN_TESTNO_REG, "testno-reg", "testno", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testg $br_src1 */ { I960_INSN_TESTG_REG, "testg-reg", "testg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* teste $br_src1 */ { I960_INSN_TESTE_REG, "teste-reg", "teste", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testge $br_src1 */ { I960_INSN_TESTGE_REG, "testge-reg", "testge", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testl $br_src1 */ { I960_INSN_TESTL_REG, "testl-reg", "testl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testne $br_src1 */ { I960_INSN_TESTNE_REG, "testne-reg", "testne", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testle $br_src1 */ { I960_INSN_TESTLE_REG, "testle-reg", "testle", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* testo $br_src1 */ { I960_INSN_TESTO_REG, "testo-reg", "testo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, /* bno $ctrl_disp */ { I960_INSN_BNO, "bno", "bno", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bg $ctrl_disp */ { I960_INSN_BG, "bg", "bg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* be $ctrl_disp */ { I960_INSN_BE, "be", "be", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bge $ctrl_disp */ { I960_INSN_BGE, "bge", "bge", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bl $ctrl_disp */ { I960_INSN_BL, "bl", "bl", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bne $ctrl_disp */ { I960_INSN_BNE, "bne", "bne", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* ble $ctrl_disp */ { I960_INSN_BLE, "ble", "ble", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* bo $ctrl_disp */ { I960_INSN_BO, "bo", "bo", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } } + { 0|A(COND_CTI), { (1<<MACH_BASE) } } }, /* b $ctrl_disp */ { I960_INSN_B, "b", "b", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* bx $offset($abase) */ { I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* bx ($abase) */ { I960_INSN_BX_INDIRECT, "bx-indirect", "bx", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* bx ($abase)[$index*S$scale] */ { I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* bx $optdisp */ { I960_INSN_BX_DISP, "bx-disp", "bx", 64, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* bx $optdisp($abase) */ { I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx", 64, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* callx $optdisp */ { I960_INSN_CALLX_DISP, "callx-disp", "callx", 64, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* callx ($abase) */ { I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* callx $offset($abase) */ { I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* ret */ { I960_INSN_RET, "ret", "ret", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* calls $src1 */ { I960_INSN_CALLS, "calls", "calls", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* fmark */ { I960_INSN_FMARK, "fmark", "fmark", 32, - { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } }, /* flushreg */ { I960_INSN_FLUSHREG, "flushreg", "flushreg", 32, - { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } + { 0, { (1<<MACH_BASE) } } }, }; @@ -1714,21 +1773,217 @@ static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] = #undef MNEM #undef OP +/* Initialize anything needed to be done once, before any cpu_open call. */ + static void init_tables () { } +/* Subroutine of i960_cgen_cpu_open to look up a mach via its bfd name. */ + +static const CGEN_MACH * +lookup_mach_via_bfd_name (table, name) + const CGEN_MACH *table; + const char *name; +{ + while (table->name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of i960_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & i960_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of i960_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & i960_cgen_ifld_table[0]; +} + +/* Subroutine of i960_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & i960_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of i960_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & i960_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of i960_cgen_cpu_open to rebuild the tables. + This is also called by cgen_set_cpu (via an entry in CD). */ + +static void +i960_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i,n_isas,n_machs; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & i960_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be equal or we set + the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal or we set + the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + + ++n_isas; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & i960_cgen_mach_table[i]; + + ++n_machs; + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + /* Initialize a cpu table and return a descriptor. - It's much like opening a file, and must be the first function called. */ + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ CGEN_CPU_DESC -i960_cgen_cpu_open (mach, endian) - int mach; - enum cgen_endian endian; +i960_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; if (! init_p) { @@ -1738,7 +1993,55 @@ i960_cgen_cpu_open (mach, endian) memset (cd, 0, sizeof (*cd)); - cd->mach = mach; + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (i960_cgen_mach_table, name); + + machs |= mach->num << 1; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "i960_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "i960_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. The worry here is where both data and insn endian can be independently @@ -1746,32 +2049,30 @@ i960_cgen_cpu_open (mach, endian) Actually, will want to allow for more arguments in the future anyway. */ cd->insn_endian = endian; - cd->int_insn_p = CGEN_INT_INSN_P; + /* Table (re)builder. */ + cd->rebuild_tables = i960_cgen_rebuild_tables; + i960_cgen_rebuild_tables (cd); - cd->max_insn_size = CGEN_MAX_INSN_SIZE; - - cd->hw_list = & i960_cgen_hw_table[0]; - - cd->ifld_table = & i960_cgen_ifld_table[0]; + return (CGEN_CPU_DESC) cd; +} - cd->operand_table = & i960_cgen_operand_table[0]; +/* Cover fn to i960_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ - { - int i; - const CGEN_IBASE *ib = & i960_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); - memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); - for (i = 0; i < MAX_INSNS; ++i) - insns[i].base = &ib[i]; - cd->insn_table.init_entries = insns; - } - cd->insn_table.entry_size = sizeof (CGEN_IBASE); - cd->insn_table.num_init_entries = MAX_INSNS; - - return (CGEN_CPU_DESC) cd; +CGEN_CPU_DESC +i960_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return i960_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); } -/* Close a cpu table. */ +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ void i960_cgen_cpu_close (cd) @@ -1779,6 +2080,8 @@ i960_cgen_cpu_close (cd) { if (cd->insn_table.init_entries) free ((CGEN_INSN *) cd->insn_table.init_entries); + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); free (cd); } diff --git a/sim/i960/i960-desc.h b/sim/i960/i960-desc.h index 7a3310f..75b3d63 100644 --- a/sim/i960/i960-desc.h +++ b/sim/i960/i960-desc.h @@ -34,15 +34,10 @@ with this program; if not, write to the Free Software Foundation, Inc., #define HAVE_CPU_I960BASE #define CGEN_INSN_LSB0_P 0 -#define CGEN_WORD_BITSIZE 32 -#define CGEN_DEFAULT_INSN_BITSIZE 32 -#define CGEN_BASE_INSN_BITSIZE 32 -#define CGEN_MIN_INSN_BITSIZE 32 -#define CGEN_MAX_INSN_BITSIZE 64 -#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) -#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) -#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) -#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 8 + #define CGEN_INT_INSN_P 0 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ @@ -193,24 +188,6 @@ typedef enum insn_ctrl_zero { CTRL_ZERO_0 } INSN_CTRL_ZERO; -/* Enum declaration for general registers. */ -typedef enum h_gr { - H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1 - , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5 - , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9 - , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13 - , H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17 - , H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21 - , H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25 - , H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29 - , H_GR_G14 = 30, H_GR_G15 = 31 -} H_GR; - -/* Enum declaration for condition code. */ -typedef enum h_cc { - H_CC_CC -} H_CC; - /* Attributes. */ /* Enum declaration for machine type selection. */ @@ -218,7 +195,13 @@ typedef enum mach_attr { MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX } MACH_ATTR; +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_I960, ISA_MAX +} ISA_ATTR; + /* Number of architecture variants. */ +#define MAX_ISAS 1 #define MAX_MACHS ((int) MACH_MAX) /* Ifield support. */ @@ -229,13 +212,13 @@ extern const struct cgen_ifld i960_cgen_ifld_table[]; /* Enum declaration for cgen_ifld attrs. */ typedef enum cgen_ifld_attr { - CGEN_IFLD_MACH, CGEN_IFLD_NBOOLS, CGEN_IFLD_START_BOOL = 31, CGEN_IFLD_VIRTUAL - , CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED - , CGEN_IFLD_SIGN_OPT + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS } CGEN_IFLD_ATTR; -/* Number of non-boolean elements in cgen_ifld. */ -#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_NBOOLS) +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) /* Enum declaration for i960 ifield types. */ typedef enum ifield_type { @@ -254,20 +237,19 @@ typedef enum ifield_type { /* Enum declaration for cgen_hw attrs. */ typedef enum cgen_hw_attr { - CGEN_HW_MACH, CGEN_HW_NBOOLS, CGEN_HW_START_BOOL = 31, CGEN_HW_VIRTUAL - , CGEN_HW_UNSIGNED, CGEN_HW_SIGNED, CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS - , CGEN_HW_PC, CGEN_HW_PROFILE + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS } CGEN_HW_ATTR; -/* Number of non-boolean elements in cgen_hw. */ -#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_NBOOLS) +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) /* Enum declaration for i960 hardware types. */ -typedef enum hw_type { - HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT - , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CC , HW_MAX -} HW_TYPE; +} CGEN_HW_TYPE; #define MAX_HW ((int) HW_MAX) @@ -275,13 +257,13 @@ typedef enum hw_type { /* Enum declaration for cgen_operand attrs. */ typedef enum cgen_operand_attr { - CGEN_OPERAND_MACH, CGEN_OPERAND_NBOOLS, CGEN_OPERAND_START_BOOL = 31, CGEN_OPERAND_VIRTUAL - , CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT - , CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS } CGEN_OPERAND_ATTR; -/* Number of non-boolean elements in cgen_operand. */ -#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_NBOOLS) +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) /* Enum declaration for i960 operand types. */ typedef enum cgen_operand_type { @@ -302,20 +284,21 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { - CGEN_INSN_MACH, CGEN_INSN_NBOOLS, CGEN_INSN_START_BOOL = 31, CGEN_INSN_ALIAS - , CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI - , CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_NO_DIS - , CGEN_INSN_PBB + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; -/* Number of non-boolean elements in cgen_insn. */ -#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_NBOOLS) +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" /* Attributes. */ -extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[]; +extern const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[]; extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[]; extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[]; @@ -324,18 +307,6 @@ extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[]; extern CGEN_KEYWORD i960_cgen_opval_h_gr; extern CGEN_KEYWORD i960_cgen_opval_h_cc; -#define CGEN_INIT_PARSE(od) \ -{\ -} -#define CGEN_INIT_INSERT(od) \ -{\ -} -#define CGEN_INIT_EXTRACT(od) \ -{\ -} -#define CGEN_INIT_PRINT(od) \ -{\ -} diff --git a/sim/i960/i960-opc.h b/sim/i960/i960-opc.h index a454ab3..0b9da78 100644 --- a/sim/i960/i960-opc.h +++ b/sim/i960/i960-opc.h @@ -54,8 +54,10 @@ typedef enum cgen_insn_type { , I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2 , I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2 , I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2 - , I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2 - , I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2 + , I960_INSN_NOR3, I960_INSN_XNOR, I960_INSN_XNOR1, I960_INSN_XNOR2 + , I960_INSN_XNOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2 + , I960_INSN_NOT3, I960_INSN_ORNOT, I960_INSN_ORNOT1, I960_INSN_ORNOT2 + , I960_INSN_ORNOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2 , I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2 , I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2 , I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2 @@ -151,6 +153,18 @@ struct cgen_fields long f_ctrl_zero; }; +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} #endif /* I960_OPC_H */ diff --git a/sim/i960/i960-sim.h b/sim/i960/i960-sim.h index e4794da..471b03e 100644 --- a/sim/i960/i960-sim.h +++ b/sim/i960/i960-sim.h @@ -10,6 +10,11 @@ #define FP0_REGNUM 36 /* First floating point register */ /* Some registers have more than one name */ #define PC_REGNUM IP_REGNUM /* GDB refers to ip as the Program Counter */ + +SI a_i960_h_gr_get (SIM_CPU *, UINT); +void a_i960_h_gr_set (SIM_CPU *, UINT, SI); +IADDR a_i960_h_pc_get (SIM_CPU *); +void a_i960_h_pc_set (SIM_CPU *, IADDR); #define GETTWI GETTSI #define SETTWI SETTSI diff --git a/sim/i960/i960.c b/sim/i960/i960.c index 9737c52..78fac37 100644 --- a/sim/i960/i960.c +++ b/sim/i960/i960.c @@ -68,6 +68,70 @@ i960base_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, return -1; /*FIXME*/ } +/* Cover fns for mach independent register accesses. */ + +SI +a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_I960BASE + case MACH_I960_KA_SA : + case MACH_I960_CA : + return i960base_h_gr_get (current_cpu, regno); +#endif + default : + abort (); + } +} + +void +a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_I960BASE + case MACH_I960_KA_SA : + case MACH_I960_CA : + i960base_h_gr_set (current_cpu, regno, newval); + break; +#endif + default : + abort (); + } +} + +IADDR +a_i960_h_pc_get (SIM_CPU *current_cpu) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_I960BASE + case MACH_I960_KA_SA : + case MACH_I960_CA : + return i960base_h_pc_get (current_cpu); +#endif + default : + abort (); + } +} + +void +a_i960_h_pc_set (SIM_CPU *current_cpu, IADDR newval) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_I960BASE + case MACH_I960_KA_SA : + case MACH_I960_CA : + i960base_h_pc_set (current_cpu, newval); + break; +#endif + default : + abort (); + } +} + #if WITH_PROFILE_MODEL_P /* FIXME: Some of these should be inline or macros. Later. */ diff --git a/sim/i960/model.c b/sim/i960/model.c index 5069eb4..8881f3e 100644 --- a/sim/i960/model.c +++ b/sim/i960/model.c @@ -995,6 +995,70 @@ model_i960KA_nor3 (SIM_CPU *current_cpu, void *sem_arg) } static int +model_i960KA_xnor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960KA_xnor1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo1.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960KA_xnor2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo2.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960KA_xnor3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_i960KA_not (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_not.f @@ -1059,6 +1123,70 @@ model_i960KA_not3 (SIM_CPU *current_cpu, void *sem_arg) } static int +model_i960KA_ornot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960KA_ornot1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo1.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960KA_ornot2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo2.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960KA_ornot3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_i960KA_clrbit (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_notbit.f @@ -1125,7 +1253,7 @@ model_i960KA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1141,7 +1269,7 @@ model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1157,7 +1285,7 @@ model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1173,7 +1301,7 @@ model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1189,7 +1317,7 @@ model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1205,7 +1333,7 @@ model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1221,7 +1349,7 @@ model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1237,7 +1365,7 @@ model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1253,7 +1381,7 @@ model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1269,7 +1397,7 @@ model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1285,7 +1413,7 @@ model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1301,7 +1429,7 @@ model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1317,7 +1445,7 @@ model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1333,7 +1461,7 @@ model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1349,7 +1477,7 @@ model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1365,7 +1493,7 @@ model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5523,6 +5651,70 @@ model_i960CA_nor3 (SIM_CPU *current_cpu, void *sem_arg) } static int +model_i960CA_xnor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960CA_xnor1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo1.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960CA_xnor2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo2.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960CA_xnor3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_i960CA_not (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_not.f @@ -5587,6 +5779,70 @@ model_i960CA_not3 (SIM_CPU *current_cpu, void *sem_arg) } static int +model_i960CA_ornot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960CA_ornot1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo1.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960CA_ornot2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo2.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_i960CA_ornot3 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo3.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_i960CA_clrbit (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.fmt_notbit.f @@ -5653,7 +5909,7 @@ model_i960CA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5669,7 +5925,7 @@ model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5685,7 +5941,7 @@ model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5701,7 +5957,7 @@ model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5717,7 +5973,7 @@ model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5733,7 +5989,7 @@ model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5749,7 +6005,7 @@ model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5765,7 +6021,7 @@ model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5781,7 +6037,7 @@ model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5797,7 +6053,7 @@ model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5813,7 +6069,7 @@ model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5829,7 +6085,7 @@ model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5845,7 +6101,7 @@ model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5861,7 +6117,7 @@ model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5877,7 +6133,7 @@ model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5893,7 +6149,7 @@ model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9162,10 +9418,18 @@ static const INSN_TIMING i960KA_timing[] = { { I960BASE_INSN_NOR1, model_i960KA_nor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOR2, model_i960KA_nor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOR3, model_i960KA_nor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR, model_i960KA_xnor, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR1, model_i960KA_xnor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR2, model_i960KA_xnor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR3, model_i960KA_xnor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT, model_i960KA_not, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT1, model_i960KA_not1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT2, model_i960KA_not2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT3, model_i960KA_not3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT, model_i960KA_ornot, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT1, model_i960KA_ornot1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT2, model_i960KA_ornot2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT3, model_i960KA_ornot3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_CLRBIT, model_i960KA_clrbit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_CLRBIT1, model_i960KA_clrbit1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_CLRBIT2, model_i960KA_clrbit2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } }, @@ -9456,10 +9720,18 @@ static const INSN_TIMING i960CA_timing[] = { { I960BASE_INSN_NOR1, model_i960CA_nor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOR2, model_i960CA_nor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOR3, model_i960CA_nor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR, model_i960CA_xnor, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR1, model_i960CA_xnor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR2, model_i960CA_xnor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_XNOR3, model_i960CA_xnor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT, model_i960CA_not, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT1, model_i960CA_not1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT2, model_i960CA_not2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_NOT3, model_i960CA_not3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT, model_i960CA_ornot, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT1, model_i960CA_ornot1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT2, model_i960CA_ornot2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, + { I960BASE_INSN_ORNOT3, model_i960CA_ornot3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_CLRBIT, model_i960CA_clrbit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_CLRBIT1, model_i960CA_clrbit1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, { I960BASE_INSN_CLRBIT2, model_i960CA_clrbit2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } }, @@ -9759,7 +10031,7 @@ i960_ka_sa_init_cpu (SIM_CPU *cpu) const MACH i960_ka_sa_mach = { - "i960:ka_sa", "i960:ka_sa", + "i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA, 32, 32, & i960_ka_sa_models[0], & i960base_imp_properties, i960_ka_sa_init_cpu, i960base_prepare_run @@ -9785,7 +10057,7 @@ i960_ca_init_cpu (SIM_CPU *cpu) const MACH i960_ca_mach = { - "i960:ca", "i960:ca", + "i960:ca", "i960:ca", MACH_I960_CA, 32, 32, & i960_ca_models[0], & i960base_imp_properties, i960_ca_init_cpu, i960base_prepare_run diff --git a/sim/i960/sem-switch.c b/sim/i960/sem-switch.c index 2ab52eb..b45109f 100644 --- a/sim/i960/sem-switch.c +++ b/sim/i960/sem-switch.c @@ -98,10 +98,18 @@ with this program; if not, write to the Free Software Foundation, Inc., { I960BASE_INSN_NOR1, && case_sem_INSN_NOR1 }, { I960BASE_INSN_NOR2, && case_sem_INSN_NOR2 }, { I960BASE_INSN_NOR3, && case_sem_INSN_NOR3 }, + { I960BASE_INSN_XNOR, && case_sem_INSN_XNOR }, + { I960BASE_INSN_XNOR1, && case_sem_INSN_XNOR1 }, + { I960BASE_INSN_XNOR2, && case_sem_INSN_XNOR2 }, + { I960BASE_INSN_XNOR3, && case_sem_INSN_XNOR3 }, { I960BASE_INSN_NOT, && case_sem_INSN_NOT }, { I960BASE_INSN_NOT1, && case_sem_INSN_NOT1 }, { I960BASE_INSN_NOT2, && case_sem_INSN_NOT2 }, { I960BASE_INSN_NOT3, && case_sem_INSN_NOT3 }, + { I960BASE_INSN_ORNOT, && case_sem_INSN_ORNOT }, + { I960BASE_INSN_ORNOT1, && case_sem_INSN_ORNOT1 }, + { I960BASE_INSN_ORNOT2, && case_sem_INSN_ORNOT2 }, + { I960BASE_INSN_ORNOT3, && case_sem_INSN_ORNOT3 }, { I960BASE_INSN_CLRBIT, && case_sem_INSN_CLRBIT }, { I960BASE_INSN_CLRBIT1, && case_sem_INSN_CLRBIT1 }, { I960BASE_INSN_CLRBIT2, && case_sem_INSN_CLRBIT2 }, @@ -1652,6 +1660,82 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) } NEXT (vpc); + CASE (sem, INSN_XNOR) : /* xnor $src1, $src2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (* FLD (i_src1), * FLD (i_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XNOR1) : /* xnor $lit1, $src2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo1.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (FLD (f_src1), * FLD (i_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XNOR2) : /* xnor $src1, $lit2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo2.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (* FLD (i_src1), FLD (f_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_XNOR3) : /* xnor $lit1, $lit2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (FLD (f_src1), FLD (f_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_NOT) : /* not $src1, $src2, $dst */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); @@ -1728,6 +1812,82 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) } NEXT (vpc); + CASE (sem, INSN_ORNOT) : /* ornot $src1, $src2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (* FLD (i_src2), INVSI (* FLD (i_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ORNOT1) : /* ornot $lit1, $src2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo1.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (* FLD (i_src2), INVSI (FLD (f_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ORNOT2) : /* ornot $src1, $lit2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo2.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (FLD (f_src2), INVSI (* FLD (i_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_ORNOT3) : /* ornot $lit1, $lit2, $dst */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.fmt_mulo3.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (FLD (f_src2), INVSI (FLD (f_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_CLRBIT) : /* clrbit $src1, $src2, $dst */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); @@ -1808,13 +1968,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1827,13 +1987,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1846,13 +2006,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1865,13 +2025,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1884,13 +2044,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1903,13 +2063,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1922,13 +2082,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1941,13 +2101,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1960,13 +2120,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1979,13 +2139,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1998,13 +2158,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -2017,13 +2177,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -2036,13 +2196,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -2055,13 +2215,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -2074,13 +2234,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -2093,13 +2253,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -2117,9 +2277,9 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (* FLD (i_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2130,9 +2290,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -2147,9 +2307,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (* FLD (i_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2160,9 +2320,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -2177,9 +2337,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (FLD (f_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2190,9 +2350,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -2207,9 +2367,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (FLD (f_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2220,9 +2380,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -2275,9 +2435,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_sregno; +{ SI tmp_dregno; + SI tmp_sregno; tmp_dregno = FLD (f_srcdst); tmp_sregno = FLD (f_src1); { @@ -2288,9 +2448,9 @@ do { { SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -2305,7 +2465,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_dregno; tmp_dregno = FLD (f_srcdst); { @@ -2316,9 +2476,9 @@ do { { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -2333,9 +2493,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_sregno; +{ SI tmp_dregno; + SI tmp_sregno; tmp_dregno = FLD (f_srcdst); tmp_sregno = FLD (f_src1); { @@ -2346,14 +2506,14 @@ do { { SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -2368,7 +2528,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_dregno; tmp_dregno = FLD (f_srcdst); { @@ -2379,14 +2539,14 @@ do { { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -2401,9 +2561,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_sregno; +{ SI tmp_dregno; + SI tmp_sregno; tmp_dregno = FLD (f_srcdst); tmp_sregno = FLD (f_src1); { @@ -2414,19 +2574,19 @@ do { { SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = CPU (h_gr[((FLD (f_src1)) + (3))]); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -2441,7 +2601,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_dregno; tmp_dregno = FLD (f_srcdst); { @@ -2452,19 +2612,19 @@ do { { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -3429,9 +3589,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_offset); { @@ -3442,9 +3602,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3459,9 +3619,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase)); { @@ -3472,9 +3632,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3489,9 +3649,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = * FLD (i_abase); { @@ -3502,9 +3662,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3519,9 +3679,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3532,9 +3692,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3549,9 +3709,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_optdisp); { @@ -3562,9 +3722,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3579,9 +3739,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase)); { @@ -3592,9 +3752,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3609,9 +3769,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3622,9 +3782,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3639,9 +3799,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))); { @@ -3652,9 +3812,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} #undef FLD } @@ -3669,9 +3829,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_offset); { @@ -3682,14 +3842,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3704,9 +3864,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase)); { @@ -3717,14 +3877,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3739,9 +3899,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = * FLD (i_abase); { @@ -3752,14 +3912,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3774,9 +3934,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3787,14 +3947,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3809,9 +3969,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_optdisp); { @@ -3822,14 +3982,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3844,9 +4004,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase)); { @@ -3857,14 +4017,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3879,9 +4039,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3892,14 +4052,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3914,9 +4074,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))); { @@ -3927,14 +4087,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} #undef FLD } @@ -3949,9 +4109,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_offset); { @@ -3962,19 +4122,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -3989,9 +4149,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase)); { @@ -4002,19 +4162,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4029,9 +4189,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = * FLD (i_abase); { @@ -4042,19 +4202,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4069,9 +4229,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -4082,19 +4242,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4109,9 +4269,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_optdisp); { @@ -4122,19 +4282,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4149,9 +4309,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase)); { @@ -4162,19 +4322,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4189,9 +4349,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -4202,19 +4362,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4229,9 +4389,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))); { @@ -4242,19 +4402,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} #undef FLD } @@ -4725,7 +4885,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4738,7 +4898,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4753,7 +4913,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4766,7 +4926,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4781,7 +4941,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4794,7 +4954,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4809,7 +4969,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4822,7 +4982,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4837,7 +4997,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4850,7 +5010,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4865,7 +5025,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4878,7 +5038,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4893,7 +5053,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4906,7 +5066,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4921,7 +5081,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4934,7 +5094,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4949,7 +5109,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4967,7 +5127,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4982,7 +5142,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5000,7 +5160,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5015,7 +5175,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5033,7 +5193,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5048,7 +5208,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5066,7 +5226,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5081,7 +5241,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5099,7 +5259,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5114,7 +5274,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5132,7 +5292,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5147,7 +5307,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5165,7 +5325,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5180,7 +5340,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5198,7 +5358,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5213,7 +5373,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5236,7 +5396,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5251,7 +5411,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5274,7 +5434,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5289,7 +5449,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5312,7 +5472,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5327,7 +5487,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5350,7 +5510,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5365,7 +5525,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5388,7 +5548,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5403,7 +5563,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5426,7 +5586,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5441,7 +5601,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5464,7 +5624,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -5479,7 +5639,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5502,7 +5662,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -6220,7 +6380,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6239,7 +6399,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6258,7 +6418,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6277,7 +6437,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6296,7 +6456,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTUSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6315,7 +6475,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTUSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6334,7 +6494,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTUSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6353,7 +6513,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SI opval = (LTUSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } #undef FLD @@ -6848,7 +7008,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_temp; tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63)); { @@ -6908,7 +7068,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; CPU (h_gr[((UINT) 1)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -6925,7 +7085,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_temp; tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63)); { @@ -6985,7 +7145,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; CPU (h_gr[((UINT) 1)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -7002,7 +7162,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_temp; tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63)); { @@ -7062,7 +7222,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; CPU (h_gr[((UINT) 1)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -7079,7 +7239,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ { SI opval = CPU (h_gr[((UINT) 0)]); CPU (h_gr[((UINT) 31)]) = opval; @@ -7106,7 +7266,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD diff --git a/sim/i960/sem.c b/sim/i960/sem.c index e062188..45f4f7f 100644 --- a/sim/i960/sem.c +++ b/sim/i960/sem.c @@ -1440,6 +1440,90 @@ SEM_FN_NAME (i960base,nor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } +/* xnor: xnor $src1, $src2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (* FLD (i_src1), * FLD (i_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xnor1: xnor $lit1, $src2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,xnor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo1.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (FLD (f_src1), * FLD (i_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xnor2: xnor $src1, $lit2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,xnor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo2.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (* FLD (i_src1), FLD (f_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xnor3: xnor $lit1, $lit2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,xnor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo3.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = INVSI (XORSI (FLD (f_src1), FLD (f_src2))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + /* not: not $src1, $src2, $dst */ SEM_PC @@ -1524,6 +1608,90 @@ SEM_FN_NAME (i960base,not3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } +/* ornot: ornot $src1, $src2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,ornot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (* FLD (i_src2), INVSI (* FLD (i_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ornot1: ornot $lit1, $src2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,ornot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo1.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (* FLD (i_src2), INVSI (FLD (f_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ornot2: ornot $src1, $lit2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,ornot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo2.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (FLD (f_src2), INVSI (* FLD (i_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ornot3: ornot $lit1, $lit2, $dst */ + +SEM_PC +SEM_FN_NAME (i960base,ornot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_mulo3.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = ORSI (FLD (f_src2), INVSI (FLD (f_src1))); + * FLD (i_dst) = opval; + TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); + } + + return vpc; +#undef FLD +} + /* clrbit: clrbit $src1, $src2, $dst */ SEM_PC @@ -1613,14 +1781,14 @@ SEM_FN_NAME (i960base,clrbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1634,14 +1802,14 @@ SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1655,14 +1823,14 @@ SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1676,14 +1844,14 @@ SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1697,14 +1865,14 @@ SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1718,14 +1886,14 @@ SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1739,14 +1907,14 @@ SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1760,14 +1928,14 @@ SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRLSI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1781,14 +1949,14 @@ SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1802,14 +1970,14 @@ SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1823,14 +1991,14 @@ SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1844,14 +2012,14 @@ SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SLLSI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1865,14 +2033,14 @@ SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.fmt_shlo.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (* FLD (i_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1886,14 +2054,14 @@ SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.fmt_shlo1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (* FLD (i_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1907,14 +2075,14 @@ SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.fmt_shlo2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (FLD (f_src2), * FLD (i_src1)); + SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), * FLD (i_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1928,14 +2096,14 @@ SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC SEM_FN_NAME (i960base,shri3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.fmt_shlo3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI opval = SRASI (FLD (f_src2), FLD (f_src1)); + SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), FLD (f_src1))); * FLD (i_dst) = opval; TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval); } @@ -1955,9 +2123,9 @@ SEM_FN_NAME (i960base,emul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (* FLD (i_src2))); tmp_dregno = FLD (f_srcdst); { @@ -1968,9 +2136,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1987,9 +2155,9 @@ SEM_FN_NAME (i960base,emul1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (* FLD (i_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2000,9 +2168,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2019,9 +2187,9 @@ SEM_FN_NAME (i960base,emul2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (FLD (f_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2032,9 +2200,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2051,9 +2219,9 @@ SEM_FN_NAME (i960base,emul3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ DI tmp_temp; + SI tmp_dregno; tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (FLD (f_src2))); tmp_dregno = FLD (f_srcdst); { @@ -2064,9 +2232,9 @@ do { { SI opval = TRUNCDISI (SRLDI (tmp_temp, 32)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2125,9 +2293,9 @@ SEM_FN_NAME (i960base,movl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_sregno; +{ SI tmp_dregno; + SI tmp_sregno; tmp_dregno = FLD (f_srcdst); tmp_sregno = FLD (f_src1); { @@ -2138,9 +2306,9 @@ do { { SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2157,7 +2325,7 @@ SEM_FN_NAME (i960base,movl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_dregno; tmp_dregno = FLD (f_srcdst); { @@ -2168,9 +2336,9 @@ do { { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2187,9 +2355,9 @@ SEM_FN_NAME (i960base,movt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_sregno; +{ SI tmp_dregno; + SI tmp_sregno; tmp_dregno = FLD (f_srcdst); tmp_sregno = FLD (f_src1); { @@ -2200,14 +2368,14 @@ do { { SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2224,7 +2392,7 @@ SEM_FN_NAME (i960base,movt1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_dregno; tmp_dregno = FLD (f_srcdst); { @@ -2235,14 +2403,14 @@ do { { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2259,9 +2427,9 @@ SEM_FN_NAME (i960base,movq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_sregno; +{ SI tmp_dregno; + SI tmp_sregno; tmp_dregno = FLD (f_srcdst); tmp_sregno = FLD (f_src1); { @@ -2272,19 +2440,19 @@ do { { SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = CPU (h_gr[((FLD (f_src1)) + (3))]); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2301,7 +2469,7 @@ SEM_FN_NAME (i960base,movq1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_dregno; tmp_dregno = FLD (f_srcdst); { @@ -2312,19 +2480,19 @@ do { { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = 0; CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3391,9 +3559,9 @@ SEM_FN_NAME (i960base,ldl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_offset); { @@ -3404,9 +3572,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3423,9 +3591,9 @@ SEM_FN_NAME (i960base,ldl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase)); { @@ -3436,9 +3604,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3455,9 +3623,9 @@ SEM_FN_NAME (i960base,ldl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = * FLD (i_abase); { @@ -3468,9 +3636,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3487,9 +3655,9 @@ SEM_FN_NAME (i960base,ldl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3500,9 +3668,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3519,9 +3687,9 @@ SEM_FN_NAME (i960base,ldl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_optdisp); { @@ -3532,9 +3700,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3551,9 +3719,9 @@ SEM_FN_NAME (i960base,ldl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase)); { @@ -3564,9 +3732,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3583,9 +3751,9 @@ SEM_FN_NAME (i960base,ldl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3596,9 +3764,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3615,9 +3783,9 @@ SEM_FN_NAME (i960base,ldl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))); { @@ -3628,9 +3796,9 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3647,9 +3815,9 @@ SEM_FN_NAME (i960base,ldt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_offset); { @@ -3660,14 +3828,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3684,9 +3852,9 @@ SEM_FN_NAME (i960base,ldt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase)); { @@ -3697,14 +3865,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3721,9 +3889,9 @@ SEM_FN_NAME (i960base,ldt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = * FLD (i_abase); { @@ -3734,14 +3902,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3758,9 +3926,9 @@ SEM_FN_NAME (i960base,ldt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3771,14 +3939,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3795,9 +3963,9 @@ SEM_FN_NAME (i960base,ldt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_optdisp); { @@ -3808,14 +3976,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3832,9 +4000,9 @@ SEM_FN_NAME (i960base,ldt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase)); { @@ -3845,14 +4013,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3869,9 +4037,9 @@ SEM_FN_NAME (i960base,ldt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -3882,14 +4050,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3906,9 +4074,9 @@ SEM_FN_NAME (i960base,ldt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))); { @@ -3919,14 +4087,14 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3943,9 +4111,9 @@ SEM_FN_NAME (i960base,ldq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_offset); { @@ -3956,19 +4124,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -3985,9 +4153,9 @@ SEM_FN_NAME (i960base,ldq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase)); { @@ -3998,19 +4166,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4027,9 +4195,9 @@ SEM_FN_NAME (i960base,ldq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = * FLD (i_abase); { @@ -4040,19 +4208,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4069,9 +4237,9 @@ SEM_FN_NAME (i960base,ldq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -4082,19 +4250,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4111,9 +4279,9 @@ SEM_FN_NAME (i960base,ldq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = FLD (f_optdisp); { @@ -4124,19 +4292,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4153,9 +4321,9 @@ SEM_FN_NAME (i960base,ldq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase)); { @@ -4166,19 +4334,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4195,9 +4363,9 @@ SEM_FN_NAME (i960base,ldq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))); { @@ -4208,19 +4376,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4237,9 +4405,9 @@ SEM_FN_NAME (i960base,ldq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { - SI tmp_dregno; +{ SI tmp_temp; + SI tmp_dregno; tmp_dregno = FLD (f_srcdst); tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))); { @@ -4250,19 +4418,19 @@ do { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4)); CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8)); CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12)); CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval; - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4783,7 +4951,7 @@ SEM_FN_NAME (i960base,stl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4796,7 +4964,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4813,7 +4981,7 @@ SEM_FN_NAME (i960base,stl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4826,7 +4994,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4843,7 +5011,7 @@ SEM_FN_NAME (i960base,stl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4856,7 +5024,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4873,7 +5041,7 @@ SEM_FN_NAME (i960base,stl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4886,7 +5054,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4903,7 +5071,7 @@ SEM_FN_NAME (i960base,stl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4916,7 +5084,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4933,7 +5101,7 @@ SEM_FN_NAME (i960base,stl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4946,7 +5114,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4963,7 +5131,7 @@ SEM_FN_NAME (i960base,stl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -4976,7 +5144,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4993,7 +5161,7 @@ SEM_FN_NAME (i960base,stl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5006,7 +5174,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5023,7 +5191,7 @@ SEM_FN_NAME (i960base,stt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5041,7 +5209,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5058,7 +5226,7 @@ SEM_FN_NAME (i960base,stt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5076,7 +5244,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5093,7 +5261,7 @@ SEM_FN_NAME (i960base,stt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5111,7 +5279,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5128,7 +5296,7 @@ SEM_FN_NAME (i960base,stt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5146,7 +5314,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5163,7 +5331,7 @@ SEM_FN_NAME (i960base,stt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5181,7 +5349,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5198,7 +5366,7 @@ SEM_FN_NAME (i960base,stt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5216,7 +5384,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5233,7 +5401,7 @@ SEM_FN_NAME (i960base,stt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5251,7 +5419,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5268,7 +5436,7 @@ SEM_FN_NAME (i960base,stt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5286,7 +5454,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5303,7 +5471,7 @@ SEM_FN_NAME (i960base,stq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5326,7 +5494,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5343,7 +5511,7 @@ SEM_FN_NAME (i960base,stq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5366,7 +5534,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5383,7 +5551,7 @@ SEM_FN_NAME (i960base,stq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5406,7 +5574,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5423,7 +5591,7 @@ SEM_FN_NAME (i960base,stq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5446,7 +5614,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5463,7 +5631,7 @@ SEM_FN_NAME (i960base,stq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5486,7 +5654,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5503,7 +5671,7 @@ SEM_FN_NAME (i960base,stq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5526,7 +5694,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5543,7 +5711,7 @@ SEM_FN_NAME (i960base,stq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5566,7 +5734,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5583,7 +5751,7 @@ SEM_FN_NAME (i960base,stq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_sregno; tmp_sregno = FLD (f_srcdst); { @@ -5606,7 +5774,7 @@ do { SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 12), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -6382,7 +6550,7 @@ SEM_FN_NAME (i960base,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6403,7 +6571,7 @@ SEM_FN_NAME (i960base,cmpi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6424,7 +6592,7 @@ SEM_FN_NAME (i960base,cmpi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6445,7 +6613,7 @@ SEM_FN_NAME (i960base,cmpi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6466,7 +6634,7 @@ SEM_FN_NAME (i960base,cmpo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTUSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6487,7 +6655,7 @@ SEM_FN_NAME (i960base,cmpo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTUSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6508,7 +6676,7 @@ SEM_FN_NAME (i960base,cmpo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTUSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -6529,7 +6697,7 @@ SEM_FN_NAME (i960base,cmpo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = (LTUSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1); CPU (h_cc) = opval; - TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval); } return vpc; @@ -7070,7 +7238,7 @@ SEM_FN_NAME (i960base,callx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); -do { +{ SI tmp_temp; tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63)); { @@ -7130,7 +7298,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; CPU (h_gr[((UINT) 1)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -7149,7 +7317,7 @@ SEM_FN_NAME (i960base,callx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_temp; tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63)); { @@ -7209,7 +7377,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; CPU (h_gr[((UINT) 1)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -7228,7 +7396,7 @@ SEM_FN_NAME (i960base,callx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ SI tmp_temp; tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63)); { @@ -7288,7 +7456,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; CPU (h_gr[((UINT) 1)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -7307,7 +7475,7 @@ SEM_FN_NAME (i960base,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ { SI opval = CPU (h_gr[((UINT) 0)]); CPU (h_gr[((UINT) 31)]) = opval; @@ -7334,7 +7502,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; diff --git a/sim/i960/sim-if.c b/sim/i960/sim-if.c index 3a58548..6179739 100644 --- a/sim/i960/sim-if.c +++ b/sim/i960/sim-if.c @@ -31,7 +31,7 @@ static void free_state (SIM_DESC); disassembler. */ static CGEN_DISASSEMBLER i960_disassemble_insn; -/* Records simulator descriptor so utilities like m32r_dump_regs can be +/* Records simulator descriptor so utilities like i960_dump_regs can be called from gdb. */ SIM_DESC current_state; @@ -145,8 +145,8 @@ sim_open (kind, callback, abfd, argv) /* Open a copy of the cpu descriptor table. */ { - CGEN_CPU_DESC cd = i960_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach, - CGEN_ENDIAN_LITTLE); + CGEN_CPU_DESC cd = i960_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, + CGEN_ENDIAN_LITTLE); for (i = 0; i < MAX_NR_PROCESSORS; ++i) { SIM_CPU *cpu = STATE_CPU (sd, i); @@ -156,10 +156,10 @@ sim_open (kind, callback, abfd, argv) } /* Initialize various cgen things not done by common framework. - Must be done after m32r_cgen_cpu_open. */ + Must be done after i960_cgen_cpu_open. */ cgen_init (sd); - /* Store in a global so things like sparc32_dump_regs can be invoked + /* Store in a global so things like i960_dump_regs can be invoked from the gdb command line. */ current_state = sd; diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index aba789a..010f2a4 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,45 @@ +Fri Apr 16 16:47:43 1999 Doug Evans <devans@charmed.cygnus.com> + + * devices.c (device_io_read_buffer): New arg `sd'. + (device_io_write_buffer): New arg `sd'. + (device_error): Give proper arg spec. + +1999-04-10 Doug Evans <devans@casey.cygnus.com> + + * sem-switch.c,sem.c: Rebuild. + +1999-03-27 Doug Evans <devans@casey.cygnus.com> + + * decode.c: Rebuild. + +1999-03-26 Doug Evans <devans@casey.cygnus.com> + + * m32r-sim.h (M32R_DEVICE_LEN): Fix off by one error. + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,model.c: Rebuild. + * m32r-sim.h (a_m32r_h_gr_get,a_m32r_h_gr_set): Declare. + (a_m32r_h_cr_get,a_m32r_h_cr_set): Declare. + * m32r.c (m32rbf_fetch_register): Replace calls to a_m32r_h_pc_get, + a_m32r_h_accum_get with appropriate calls to m32rbf_*. + (m32rbf_store_register): Ditto. + (a_m32r_h_gr_get,a_m32r_h_gr_set): New functions. + (a_m32r_h_cr_get,a_m32r_h_cr_set): Ditto. + * sim-if.c (sim_open): Update call to m32r_cgen_cpu_open. + * traps.c (m32r_core_signal): Replace calls to a_m32r_h_*, + with appropriate calls to m32rbf_*. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,cpu.c,cpu.h,sem.c,sem-switch.c: Rebuild. + * m32r-sim.h (GET_H_*,SET_H_*, except GET_H_SM): Delete. + * sim-if.c (sim_open): Update call to m32r_cgen_cpu_open. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * cpu.c,cpu.h: Rebuild. + 1999-02-09 Doug Evans <devans@casey.cygnus.com> * Makefile.in (SIM_EXTRA_DEPS): Add m32r-desc.h, delete cpu-opc.h. diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c index 2caa300..c6da47c 100644 --- a/sim/m32r/arch.c +++ b/sim/m32r/arch.c @@ -33,324 +33,3 @@ const MACH *sim_machs[] = 0 }; -/* Get the value of h-pc. */ - -USI -a_m32r_h_pc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_pc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pc. */ - -void -a_m32r_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_pc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-gr. */ - -SI -a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_gr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-gr. */ - -void -a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_gr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cr. */ - -USI -a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_cr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-cr. */ - -void -a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_cr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-accum. */ - -DI -a_m32r_h_accum_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_accum_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-accum. */ - -void -a_m32r_h_accum_set (SIM_CPU *current_cpu, DI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_accum_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-accums. */ - -DI -a_m32r_h_accums_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { - default : - abort (); - } -} - -/* Set a value for h-accums. */ - -void -a_m32r_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { - default : - abort (); - } -} - -/* Get the value of h-cond. */ - -BI -a_m32r_h_cond_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_cond_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cond. */ - -void -a_m32r_h_cond_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_cond_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-psw. */ - -UQI -a_m32r_h_psw_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_psw_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-psw. */ - -void -a_m32r_h_psw_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_psw_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-bpsw. */ - -UQI -a_m32r_h_bpsw_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_bpsw_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-bpsw. */ - -void -a_m32r_h_bpsw_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_bpsw_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-bbpsw. */ - -UQI -a_m32r_h_bbpsw_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_bbpsw_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-bbpsw. */ - -void -a_m32r_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_bbpsw_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-lock. */ - -BI -a_m32r_h_lock_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - return m32rbf_h_lock_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-lock. */ - -void -a_m32r_h_lock_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_M32RBF - case bfd_mach_m32r : - m32rbf_h_lock_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h index ace8104..f5ea3b2 100644 --- a/sim/m32r/arch.h +++ b/sim/m32r/arch.h @@ -27,28 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #define TARGET_BIG_ENDIAN 1 -/* Cover fns for register access. */ -USI a_m32r_h_pc_get (SIM_CPU *); -void a_m32r_h_pc_set (SIM_CPU *, USI); -SI a_m32r_h_gr_get (SIM_CPU *, UINT); -void a_m32r_h_gr_set (SIM_CPU *, UINT, SI); -USI a_m32r_h_cr_get (SIM_CPU *, UINT); -void a_m32r_h_cr_set (SIM_CPU *, UINT, USI); -DI a_m32r_h_accum_get (SIM_CPU *); -void a_m32r_h_accum_set (SIM_CPU *, DI); -DI a_m32r_h_accums_get (SIM_CPU *, UINT); -void a_m32r_h_accums_set (SIM_CPU *, UINT, DI); -BI a_m32r_h_cond_get (SIM_CPU *); -void a_m32r_h_cond_set (SIM_CPU *, BI); -UQI a_m32r_h_psw_get (SIM_CPU *); -void a_m32r_h_psw_set (SIM_CPU *, UQI); -UQI a_m32r_h_bpsw_get (SIM_CPU *); -void a_m32r_h_bpsw_set (SIM_CPU *, UQI); -UQI a_m32r_h_bbpsw_get (SIM_CPU *); -void a_m32r_h_bbpsw_set (SIM_CPU *, UQI); -BI a_m32r_h_lock_get (SIM_CPU *); -void a_m32r_h_lock_set (SIM_CPU *, BI); - /* Enum declaration for model types. */ typedef enum model_type { MODEL_M32R_D, MODEL_TEST diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c index fb856f5..f6474a0 100644 --- a/sim/m32r/cpu.c +++ b/sim/m32r/cpu.c @@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #define WANT_CPU_M32RBF #include "sim-main.h" +#include "cgen-ops.h" /* Get the value of h-pc. */ @@ -91,22 +92,6 @@ m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval) SET_H_ACCUM (newval); } -/* Get the value of h-accums. */ - -DI -m32rbf_h_accums_get (SIM_CPU *current_cpu, UINT regno) -{ - return GET_H_ACCUMS (regno); -} - -/* Set a value for h-accums. */ - -void -m32rbf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval) -{ - SET_H_ACCUMS (regno, newval); -} - /* Get the value of h-cond. */ BI diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index ccb4676..6ebe199 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -46,20 +46,29 @@ typedef struct { #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) /* control registers */ USI h_cr[16]; -/* GET_H_CR macro user-written */ -/* SET_H_CR macro user-written */ +#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index) +#define SET_H_CR(index, x) \ +do { \ +m32rbf_h_cr_set_handler (current_cpu, (index), (x));\ +} while (0) /* accumulator */ DI h_accum; -/* GET_H_ACCUM macro user-written */ -/* SET_H_ACCUM macro user-written */ +#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu) +#define SET_H_ACCUM(x) \ +do { \ +m32rbf_h_accum_set_handler (current_cpu, (x));\ +} while (0) /* condition bit */ BI h_cond; #define GET_H_COND() CPU (h_cond) #define SET_H_COND(x) (CPU (h_cond) = (x)) /* psw part of psw */ UQI h_psw; -/* GET_H_PSW macro user-written */ -/* SET_H_PSW macro user-written */ +#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu) +#define SET_H_PSW(x) \ +do { \ +m32rbf_h_psw_set_handler (current_cpu, (x));\ +} while (0) /* backup psw */ UQI h_bpsw; #define GET_H_BPSW() CPU (h_bpsw) @@ -85,8 +94,6 @@ USI m32rbf_h_cr_get (SIM_CPU *, UINT); void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); DI m32rbf_h_accum_get (SIM_CPU *); void m32rbf_h_accum_set (SIM_CPU *, DI); -DI m32rbf_h_accums_get (SIM_CPU *, UINT); -void m32rbf_h_accums_set (SIM_CPU *, UINT, DI); BI m32rbf_h_cond_get (SIM_CPU *); void m32rbf_h_cond_set (SIM_CPU *, BI); UQI m32rbf_h_psw_get (SIM_CPU *); diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index 63913af..8bac0ef 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -46,6 +46,11 @@ with this program; if not, write to the Free Software Foundation, Inc., #define FAST(fn) #endif +/* The INSN_ prefix is not here and is instead part of the `insn' argument + to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ +#define IDX(insn) CONCAT2 (M32RBF_,insn) +#define TYPE(insn) CONCAT2 (M32R_,insn) + /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -53,11 +58,6 @@ with this program; if not, write to the Free Software Foundation, Inc., addition of instructions nor an SMP machine with different cpus). */ static IDESC m32rbf_insn_data[M32RBF_INSN_MAX]; -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (M32RBF_,insn) -#define TYPE(insn) CONCAT2 (M32R_,insn) - /* Commas between elements are contained in the macros. Some of these are conditionally compiled out. */ @@ -175,6 +175,9 @@ static const struct insn_sem m32rbf_insn_sem_invalid = VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }; +#undef FMT +#undef FULL +#undef FAST #undef IDX #undef TYPE @@ -236,50 +239,6 @@ m32rbf_init_idesc_table (SIM_CPU *cpu) CPU_IDESC (cpu) = table; } -/* Enum declaration for all instruction semantic formats. */ -typedef enum sfmt { - FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3 - , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3 - , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ - , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BRA8 - , FMT_BRA24, FMT_CMP, FMT_CMPI, FMT_DIV - , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D - , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D - , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16 - , FMT_LOCK, FMT_MACHI, FMT_MULHI, FMT_MV - , FMT_MVFACHI, FMT_MVFC, FMT_MVTACHI, FMT_MVTC - , FMT_NOP, FMT_RAC, FMT_RTE, FMT_SETH - , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D - , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D - , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK -} SFMT; - -/* The decoder uses this to record insns and direct extraction handling. */ - -typedef struct { - const IDESC *idesc; -#ifdef __GNUC__ - void *sfmt; -#else - enum sfmt sfmt; -#endif -} DECODE_DESC; - -/* Macro to go from decode phase to extraction phase. */ - -#ifdef __GNUC__ -#define GOTO_EXTRACT(id) goto *(id)->sfmt -#else -#define GOTO_EXTRACT(id) goto extract -#endif - -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) -#endif - /* Given an instruction, return a pointer to its IDESC entry. */ const IDESC * @@ -287,370 +246,254 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, ARGBUF *abuf) { - /* Result of decoder, used by extractor. */ - const DECODE_DESC *idecode; - - /* First decode the instruction. */ + /* Result of decoder. */ + M32RBF_INSN_TYPE itype; { -#define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)] -#ifdef __GNUC__ -#define E(fmt) && case_ex_##fmt -#else -#define E(fmt) fmt -#endif CGEN_INSN_INT insn = base_insn; - static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) }; { -#ifdef __GNUC__ - static const void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_28, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_87, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_95, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_112, && case_0_113, && case_0_114, && case_0_115, - && case_0_116, && case_0_117, && case_0_118, && case_0_119, - && case_0_120, && case_0_121, && case_0_122, && case_0_123, - && case_0_124, && case_0_125, && case_0_126, && case_0_127, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_240, && case_0_241, && case_0_242, && case_0_243, - && case_0_244, && case_0_245, && case_0_246, && case_0_247, - && case_0_248, && case_0_249, && case_0_250, && case_0_251, - && case_0_252, && case_0_253, && case_0_254, && case_0_255, - }; -#endif - static const DECODE_DESC insns[256] = { - { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) }, - { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) }, - { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) }, - { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) }, - { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) }, - { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) }, - { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { 0 }, { I (INSN_RTE), E (FMT_RTE) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) }, - { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) }, - { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) }, - { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) }, - { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) }, - { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) }, - { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_MULHI), E (FMT_MULHI) }, { I (INSN_MULLO), E (FMT_MULHI) }, - { I (INSN_MULWHI), E (FMT_MULHI) }, { I (INSN_MULWLO), E (FMT_MULHI) }, - { I (INSN_MACHI), E (FMT_MACHI) }, { I (INSN_MACLO), E (FMT_MACHI) }, - { I (INSN_MACWHI), E (FMT_MACHI) }, { I (INSN_MACWLO), E (FMT_MACHI) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, - { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) }, - { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) }, - { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { I (INSN_RACH), E (FMT_RAC) }, { I (INSN_RAC), E (FMT_RAC) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) }, - { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVU), E (FMT_DIV) }, - { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) }, - { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) }, - { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) }, - { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) }, - { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) }, - { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - { 0 }, { 0 }, - }; - unsigned int val; - val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); - DECODE_SWITCH (0, val) + unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); + switch (val) + { + case 0 : itype = M32RBF_INSN_SUBV; goto extract_fmt_addv; + case 1 : itype = M32RBF_INSN_SUBX; goto extract_fmt_addx; + case 2 : itype = M32RBF_INSN_SUB; goto extract_fmt_add; + case 3 : itype = M32RBF_INSN_NEG; goto extract_fmt_mv; + case 4 : itype = M32RBF_INSN_CMP; goto extract_fmt_cmp; + case 5 : itype = M32RBF_INSN_CMPU; goto extract_fmt_cmp; + case 8 : itype = M32RBF_INSN_ADDV; goto extract_fmt_addv; + case 9 : itype = M32RBF_INSN_ADDX; goto extract_fmt_addx; + case 10 : itype = M32RBF_INSN_ADD; goto extract_fmt_add; + case 11 : itype = M32RBF_INSN_NOT; goto extract_fmt_mv; + case 12 : itype = M32RBF_INSN_AND; goto extract_fmt_add; + case 13 : itype = M32RBF_INSN_XOR; goto extract_fmt_add; + case 14 : itype = M32RBF_INSN_OR; goto extract_fmt_add; + case 16 : itype = M32RBF_INSN_SRL; goto extract_fmt_add; + case 18 : itype = M32RBF_INSN_SRA; goto extract_fmt_add; + case 20 : itype = M32RBF_INSN_SLL; goto extract_fmt_add; + case 22 : itype = M32RBF_INSN_MUL; goto extract_fmt_add; + case 24 : itype = M32RBF_INSN_MV; goto extract_fmt_mv; + case 25 : itype = M32RBF_INSN_MVFC; goto extract_fmt_mvfc; + case 26 : itype = M32RBF_INSN_MVTC; goto extract_fmt_mvtc; + case 28 : { - CASE (0, 28) : + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) }, - }; - unsigned int val = (((insn >> 8) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 14 : itype = M32RBF_INSN_JL; goto extract_fmt_jl; + case 15 : itype = M32RBF_INSN_JMP; goto extract_fmt_jmp; + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 87) : + } + case 29 : itype = M32RBF_INSN_RTE; goto extract_fmt_rte; + case 31 : itype = M32RBF_INSN_TRAP; goto extract_fmt_trap; + case 32 : itype = M32RBF_INSN_STB; goto extract_fmt_stb; + case 34 : itype = M32RBF_INSN_STH; goto extract_fmt_sth; + case 36 : itype = M32RBF_INSN_ST; goto extract_fmt_st; + case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_fmt_unlock; + case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_fmt_st_plus; + case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_fmt_st_plus; + case 40 : itype = M32RBF_INSN_LDB; goto extract_fmt_ldb; + case 41 : itype = M32RBF_INSN_LDUB; goto extract_fmt_ldb; + case 42 : itype = M32RBF_INSN_LDH; goto extract_fmt_ldh; + case 43 : itype = M32RBF_INSN_LDUH; goto extract_fmt_ldh; + case 44 : itype = M32RBF_INSN_LD; goto extract_fmt_ld; + case 45 : itype = M32RBF_INSN_LOCK; goto extract_fmt_lock; + case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_fmt_ld_plus; + case 48 : itype = M32RBF_INSN_MULHI; goto extract_fmt_mulhi; + case 49 : itype = M32RBF_INSN_MULLO; goto extract_fmt_mulhi; + case 50 : itype = M32RBF_INSN_MULWHI; goto extract_fmt_mulhi; + case 51 : itype = M32RBF_INSN_MULWLO; goto extract_fmt_mulhi; + case 52 : itype = M32RBF_INSN_MACHI; goto extract_fmt_machi; + case 53 : itype = M32RBF_INSN_MACLO; goto extract_fmt_machi; + case 54 : itype = M32RBF_INSN_MACWHI; goto extract_fmt_machi; + case 55 : itype = M32RBF_INSN_MACWLO; goto extract_fmt_machi; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : /* fall through */ + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : /* fall through */ + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : /* fall through */ + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : itype = M32RBF_INSN_ADDI; goto extract_fmt_addi; + case 80 : /* fall through */ + case 81 : itype = M32RBF_INSN_SRLI; goto extract_fmt_slli; + case 82 : /* fall through */ + case 83 : itype = M32RBF_INSN_SRAI; goto extract_fmt_slli; + case 84 : /* fall through */ + case 85 : itype = M32RBF_INSN_SLLI; goto extract_fmt_slli; + case 87 : + { + unsigned int val = (((insn >> 0) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_MVTACHI), E (FMT_MVTACHI) }, { I (INSN_MVTACLO), E (FMT_MVTACHI) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 0) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_fmt_mvtachi; + case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_fmt_mvtachi; + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 95) : + } + case 88 : itype = M32RBF_INSN_RACH; goto extract_fmt_rac; + case 89 : itype = M32RBF_INSN_RAC; goto extract_fmt_rac; + case 95 : + { + unsigned int val = (((insn >> 0) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_MVFACHI), E (FMT_MVFACHI) }, { I (INSN_MVFACLO), E (FMT_MVFACHI) }, - { I (INSN_MVFACMI), E (FMT_MVFACHI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 0) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_fmt_mvfachi; + case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_fmt_mvfachi; + case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_fmt_mvfachi; + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 112) : + } + case 96 : /* fall through */ + case 97 : /* fall through */ + case 98 : /* fall through */ + case 99 : /* fall through */ + case 100 : /* fall through */ + case 101 : /* fall through */ + case 102 : /* fall through */ + case 103 : /* fall through */ + case 104 : /* fall through */ + case 105 : /* fall through */ + case 106 : /* fall through */ + case 107 : /* fall through */ + case 108 : /* fall through */ + case 109 : /* fall through */ + case 110 : /* fall through */ + case 111 : itype = M32RBF_INSN_LDI8; goto extract_fmt_ldi8; + case 112 : + { + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, - { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, - }; - unsigned int val = (((insn >> 8) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = M32RBF_INSN_NOP; goto extract_fmt_nop; + case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8; + case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8; + case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8; + case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8; + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 113) : /* fall through */ - CASE (0, 114) : /* fall through */ - CASE (0, 115) : /* fall through */ - CASE (0, 116) : /* fall through */ - CASE (0, 117) : /* fall through */ - CASE (0, 118) : /* fall through */ - CASE (0, 119) : /* fall through */ - CASE (0, 120) : /* fall through */ - CASE (0, 121) : /* fall through */ - CASE (0, 122) : /* fall through */ - CASE (0, 123) : /* fall through */ - CASE (0, 124) : /* fall through */ - CASE (0, 125) : /* fall through */ - CASE (0, 126) : /* fall through */ - CASE (0, 127) : + } + case 113 : /* fall through */ + case 114 : /* fall through */ + case 115 : /* fall through */ + case 116 : /* fall through */ + case 117 : /* fall through */ + case 118 : /* fall through */ + case 119 : /* fall through */ + case 120 : /* fall through */ + case 121 : /* fall through */ + case 122 : /* fall through */ + case 123 : /* fall through */ + case 124 : /* fall through */ + case 125 : /* fall through */ + case 126 : /* fall through */ + case 127 : + { + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, - { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, - }; - unsigned int val = (((insn >> 8) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8; + case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8; + case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8; + case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8; + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 240) : /* fall through */ - CASE (0, 241) : /* fall through */ - CASE (0, 242) : /* fall through */ - CASE (0, 243) : /* fall through */ - CASE (0, 244) : /* fall through */ - CASE (0, 245) : /* fall through */ - CASE (0, 246) : /* fall through */ - CASE (0, 247) : /* fall through */ - CASE (0, 248) : /* fall through */ - CASE (0, 249) : /* fall through */ - CASE (0, 250) : /* fall through */ - CASE (0, 251) : /* fall through */ - CASE (0, 252) : /* fall through */ - CASE (0, 253) : /* fall through */ - CASE (0, 254) : /* fall through */ - CASE (0, 255) : + } + case 132 : itype = M32RBF_INSN_CMPI; goto extract_fmt_cmpi; + case 133 : itype = M32RBF_INSN_CMPUI; goto extract_fmt_cmpi; + case 136 : itype = M32RBF_INSN_ADDV3; goto extract_fmt_addv3; + case 138 : itype = M32RBF_INSN_ADD3; goto extract_fmt_add3; + case 140 : itype = M32RBF_INSN_AND3; goto extract_fmt_and3; + case 141 : itype = M32RBF_INSN_XOR3; goto extract_fmt_and3; + case 142 : itype = M32RBF_INSN_OR3; goto extract_fmt_or3; + case 144 : itype = M32RBF_INSN_DIV; goto extract_fmt_div; + case 145 : itype = M32RBF_INSN_DIVU; goto extract_fmt_div; + case 146 : itype = M32RBF_INSN_REM; goto extract_fmt_div; + case 147 : itype = M32RBF_INSN_REMU; goto extract_fmt_div; + case 152 : itype = M32RBF_INSN_SRL3; goto extract_fmt_sll3; + case 154 : itype = M32RBF_INSN_SRA3; goto extract_fmt_sll3; + case 156 : itype = M32RBF_INSN_SLL3; goto extract_fmt_sll3; + case 159 : itype = M32RBF_INSN_LDI16; goto extract_fmt_ldi16; + case 160 : itype = M32RBF_INSN_STB_D; goto extract_fmt_stb_d; + case 162 : itype = M32RBF_INSN_STH_D; goto extract_fmt_sth_d; + case 164 : itype = M32RBF_INSN_ST_D; goto extract_fmt_st_d; + case 168 : itype = M32RBF_INSN_LDB_D; goto extract_fmt_ldb_d; + case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_fmt_ldb_d; + case 170 : itype = M32RBF_INSN_LDH_D; goto extract_fmt_ldh_d; + case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_fmt_ldh_d; + case 172 : itype = M32RBF_INSN_LD_D; goto extract_fmt_ld_d; + case 176 : itype = M32RBF_INSN_BEQ; goto extract_fmt_beq; + case 177 : itype = M32RBF_INSN_BNE; goto extract_fmt_beq; + case 184 : itype = M32RBF_INSN_BEQZ; goto extract_fmt_beqz; + case 185 : itype = M32RBF_INSN_BNEZ; goto extract_fmt_beqz; + case 186 : itype = M32RBF_INSN_BLTZ; goto extract_fmt_beqz; + case 187 : itype = M32RBF_INSN_BGEZ; goto extract_fmt_beqz; + case 188 : itype = M32RBF_INSN_BLEZ; goto extract_fmt_beqz; + case 189 : itype = M32RBF_INSN_BGTZ; goto extract_fmt_beqz; + case 220 : itype = M32RBF_INSN_SETH; goto extract_fmt_seth; + case 224 : /* fall through */ + case 225 : /* fall through */ + case 226 : /* fall through */ + case 227 : /* fall through */ + case 228 : /* fall through */ + case 229 : /* fall through */ + case 230 : /* fall through */ + case 231 : /* fall through */ + case 232 : /* fall through */ + case 233 : /* fall through */ + case 234 : /* fall through */ + case 235 : /* fall through */ + case 236 : /* fall through */ + case 237 : /* fall through */ + case 238 : /* fall through */ + case 239 : itype = M32RBF_INSN_LD24; goto extract_fmt_ld24; + case 240 : /* fall through */ + case 241 : /* fall through */ + case 242 : /* fall through */ + case 243 : /* fall through */ + case 244 : /* fall through */ + case 245 : /* fall through */ + case 246 : /* fall through */ + case 247 : /* fall through */ + case 248 : /* fall through */ + case 249 : /* fall through */ + case 250 : /* fall through */ + case 251 : /* fall through */ + case 252 : /* fall through */ + case 253 : /* fall through */ + case 254 : /* fall through */ + case 255 : + { + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) }, - { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) }, - }; - unsigned int val = (((insn >> 8) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 12 : itype = M32RBF_INSN_BC24; goto extract_fmt_bc24; + case 13 : itype = M32RBF_INSN_BNC24; goto extract_fmt_bc24; + case 14 : itype = M32RBF_INSN_BL24; goto extract_fmt_bl24; + case 15 : itype = M32RBF_INSN_BRA24; goto extract_fmt_bra24; + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; } - DEFAULT (0) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); } - ENDSWITCH (0) + default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + } } -#undef I -#undef E } /* The instruction has been decoded, now extract the fields. */ - extract: - { -#ifndef __GNUC__ - switch (idecode->sfmt) -#endif - { - - CASE (ex, FMT_EMPTY) : + extract_fmt_empty: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_empty.f EXTRACT_IFMT_EMPTY_VARS /* */ @@ -661,11 +504,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADD) : + extract_fmt_add: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_add.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -687,11 +531,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADD3) : + extract_fmt_add3: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_add3.f EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -713,11 +558,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_AND3) : + extract_fmt_and3: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_and3.f EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ @@ -739,11 +585,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_OR3) : + extract_fmt_or3: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_or3.f EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ @@ -765,11 +612,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDI) : + extract_fmt_addi: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addi.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ @@ -790,11 +638,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDV) : + extract_fmt_addv: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addv.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -816,11 +665,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDV3) : + extract_fmt_addv3: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addv3.f EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -842,11 +692,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDX) : + extract_fmt_addx: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addx.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -868,11 +719,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BC8) : + extract_fmt_bc8: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ @@ -891,11 +743,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BC24) : + extract_fmt_bc24: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ @@ -914,11 +767,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BEQ) : + extract_fmt_beq: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_beq.f EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ @@ -941,11 +795,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BEQZ) : + extract_fmt_beqz: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ @@ -966,11 +821,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BL8) : + extract_fmt_bl8: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ @@ -990,11 +846,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BL24) : + extract_fmt_bl24: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ @@ -1014,11 +871,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BRA8) : + extract_fmt_bra8: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ @@ -1037,11 +895,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BRA24) : + extract_fmt_bra24: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ @@ -1060,11 +919,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMP) : + extract_fmt_cmp: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_cmp.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1085,11 +945,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI) : + extract_fmt_cmpi: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_cmpi.f EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1109,11 +970,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV) : + extract_fmt_div: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_div.f EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1135,11 +997,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_JL) : + extract_fmt_jl: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jl.f EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1160,11 +1023,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_JMP) : + extract_fmt_jmp: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1184,11 +1048,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD) : + extract_fmt_ld: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1209,11 +1074,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_D) : + extract_fmt_ld_d: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld_d.f EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1235,11 +1101,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDB) : + extract_fmt_ldb: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1260,11 +1127,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDB_D) : + extract_fmt_ldb_d: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldb_d.f EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1286,11 +1154,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDH) : + extract_fmt_ldh: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1311,11 +1180,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDH_D) : + extract_fmt_ldh_d: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldh_d.f EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1337,11 +1207,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD_PLUS) : + extract_fmt_ld_plus: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld_plus.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1363,11 +1234,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD24) : + extract_fmt_ld24: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld24.f EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */ @@ -1387,11 +1259,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI8) : + extract_fmt_ldi8: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldi8.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ @@ -1411,11 +1284,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI16) : + extract_fmt_ldi16: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldi16.f EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1435,11 +1309,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LOCK) : + extract_fmt_lock: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_lock.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1460,11 +1335,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MACHI) : + extract_fmt_machi: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_machi.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1485,11 +1361,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULHI) : + extract_fmt_mulhi: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mulhi.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1510,11 +1387,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MV) : + extract_fmt_mv: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mv.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1535,11 +1413,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MVFACHI) : + extract_fmt_mvfachi: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvfachi.f EXTRACT_IFMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1558,11 +1437,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MVFC) : + extract_fmt_mvfc: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvfc.f EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1582,11 +1462,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MVTACHI) : + extract_fmt_mvtachi: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvtachi.f EXTRACT_IFMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1605,11 +1486,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MVTC) : + extract_fmt_mvtc: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvtc.f EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1629,11 +1511,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOP) : + extract_fmt_nop: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_nop.f EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1644,11 +1527,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RAC) : + extract_fmt_rac: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_rac.f EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1659,11 +1543,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RTE) : + extract_fmt_rte: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_rte.f EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1681,11 +1566,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_SETH) : + extract_fmt_seth: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_seth.f EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ @@ -1705,11 +1591,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_SLL3) : + extract_fmt_sll3: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sll3.f EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1731,11 +1618,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_SLLI) : + extract_fmt_slli: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_slli.f EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ @@ -1756,11 +1644,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST) : + extract_fmt_st: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_st.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1781,11 +1670,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_D) : + extract_fmt_st_d: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_st_d.f EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1807,11 +1697,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STB) : + extract_fmt_stb: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_stb.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1832,11 +1723,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STB_D) : + extract_fmt_stb_d: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_stb_d.f EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1858,11 +1750,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STH) : + extract_fmt_sth: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sth.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1883,11 +1776,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STH_D) : + extract_fmt_sth_d: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sth_d.f EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ @@ -1909,11 +1803,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST_PLUS) : + extract_fmt_st_plus: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_st_plus.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1935,11 +1830,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_TRAP) : + extract_fmt_trap: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_trap.f EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ @@ -1958,11 +1854,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_UNLOCK) : + extract_fmt_unlock: { + const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_unlock.f EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ @@ -1983,14 +1880,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); - } - - - } - ENDSWITCH (ex) - + return idesc; } - return idecode->idesc; } diff --git a/sim/m32r/devices.c b/sim/m32r/devices.c index d706869..032c8e7 100644 --- a/sim/m32r/devices.c +++ b/sim/m32r/devices.c @@ -32,10 +32,8 @@ device m32r_devices; int device_io_read_buffer (device *me, void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) return nr_bytes; @@ -70,10 +68,8 @@ device_io_read_buffer (device *me, void *source, int space, int device_io_write_buffer (device *me, const void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - #if WITH_SCACHE /* MSPR support is deprecated but is kept in for upward compatibility with existing overlay support. */ @@ -105,4 +101,7 @@ device_io_write_buffer (device *me, const void *source, int space, return nr_bytes; } -void device_error () {} +void +device_error (device *me, char *message, ...) +{ +} diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h index 1dd1878..d0fae5e 100644 --- a/sim/m32r/m32r-sim.h +++ b/sim/m32r/m32r-sim.h @@ -41,26 +41,19 @@ extern int m32r_decode_gdb_ctrl_regnum (int); FIXME: Eventually move to cgen. */ #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0) +extern SI a_m32r_h_gr_get (SIM_CPU *, UINT); +extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI); +extern USI a_m32r_h_cr_get (SIM_CPU *, UINT); +extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI); + extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT); extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); -#define GET_H_CR(regno) \ - XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno)) -#define SET_H_CR(regno, val) \ - XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val)) extern UQI m32rbf_h_psw_get_handler (SIM_CPU *); extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); -#define GET_H_PSW() \ - XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu) -#define SET_H_PSW(val) \ - XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val)) extern DI m32rbf_h_accum_get_handler (SIM_CPU *); extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI); -#define GET_H_ACCUM() \ - XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu) -#define SET_H_ACCUM(val) \ - XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val)) /* Misc. profile data. */ @@ -189,7 +182,7 @@ do { \ /* Start address and length of all device support. */ #define M32R_DEVICE_ADDR 0xff000000 -#define M32R_DEVICE_LEN 0x00ffffff +#define M32R_DEVICE_LEN 0x01000000 /* sim_core_attach device argument. */ extern device m32r_devices; diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c index 13e71e6..3e5e4aa 100644 --- a/sim/m32r/m32r.c +++ b/sim/m32r/m32r.c @@ -48,6 +48,8 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum) int m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { + int mach = MACH_NUM (CPU_MACH (current_cpu)); + if (rn < 16) SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn)); else @@ -64,13 +66,22 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len m32r_decode_gdb_ctrl_regnum (rn))); break; case PC_REGNUM : - SETTWI (buf, a_m32r_h_pc_get (current_cpu)); + if (mach == MACH_M32R) + SETTWI (buf, m32rbf_h_pc_get (current_cpu)); + else + SETTWI (buf, m32rxf_h_pc_get (current_cpu)); break; case ACCL_REGNUM : - SETTWI (buf, GETLODI (a_m32r_h_accum_get (current_cpu))); + if (mach == MACH_M32R) + SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu))); + else + SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu))); break; case ACCH_REGNUM : - SETTWI (buf, GETHIDI (a_m32r_h_accum_get (current_cpu))); + if (mach == MACH_M32R) + SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu))); + else + SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu))); break; default : return 0; @@ -84,6 +95,8 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len int m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { + int mach = MACH_NUM (CPU_MACH (current_cpu)); + if (rn < 16) a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf)); else @@ -101,20 +114,37 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len GETTWI (buf)); break; case PC_REGNUM : - a_m32r_h_pc_set (current_cpu, GETTWI (buf)); + if (mach == MACH_M32R) + m32rbf_h_pc_set (current_cpu, GETTWI (buf)); + else + m32rxf_h_pc_set (current_cpu, GETTWI (buf)); break; case ACCL_REGNUM : { - DI val = a_m32r_h_accum_get (current_cpu); + DI val; + if (mach == MACH_M32R) + val = m32rbf_h_accum_get (current_cpu); + else + val = m32rxf_h_accum_get (current_cpu); SETLODI (val, GETTWI (buf)); - a_m32r_h_accum_set (current_cpu, val); + if (mach == MACH_M32R) + m32rbf_h_accum_set (current_cpu, val); + else + m32rxf_h_accum_set (current_cpu, val); break; } case ACCH_REGNUM : { - DI val = a_m32r_h_accum_get (current_cpu); + DI val; + if (mach == MACH_M32R) + val = m32rbf_h_accum_get (current_cpu); + else + val = m32rxf_h_accum_get (current_cpu); SETHIDI (val, GETTWI (buf)); - a_m32r_h_accum_set (current_cpu, val); + if (mach == MACH_M32R) + m32rbf_h_accum_set (current_cpu, val); + else + m32rxf_h_accum_set (current_cpu, val); break; } default : @@ -124,6 +154,84 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len return -1; /*FIXME*/ } +/* Cover fns for mach independent register accesses. */ + +SI +a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_M32RBF + case MACH_M32R : + return m32rbf_h_gr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_M32RXF + case MACH_M32RX : + return m32rxf_h_gr_get (current_cpu, regno); +#endif + default : + abort (); + } +} + +void +a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_M32RBF + case MACH_M32R : + m32rbf_h_gr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_M32RXF + case MACH_M32RX : + m32rxf_h_gr_set (current_cpu, regno, newval); + break; +#endif + default : + abort (); + } +} + +USI +a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_M32RBF + case MACH_M32R : + return m32rbf_h_cr_get (current_cpu, regno); +#endif +#ifdef HAVE_CPU_M32RXF + case MACH_M32RX : + return m32rxf_h_cr_get (current_cpu, regno); +#endif + default : + abort (); + } +} + +void +a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) +{ + switch (MACH_NUM (CPU_MACH (current_cpu))) + { +#ifdef HAVE_CPU_M32RBF + case MACH_M32R : + m32rbf_h_cr_set (current_cpu, regno, newval); + break; +#endif +#ifdef HAVE_CPU_M32RXF + case MACH_M32RX : + m32rxf_h_cr_set (current_cpu, regno, newval); + break; +#endif + default : + abort (); + } +} + USI m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr) { diff --git a/sim/m32r/model.c b/sim/m32r/model.c index 8e0454e..e82881e 100644 --- a/sim/m32r/model.c +++ b/sim/m32r/model.c @@ -4160,7 +4160,7 @@ m32r_init_cpu (SIM_CPU *cpu) const MACH m32r_mach = { - "m32r", "m32r", + "m32r", "m32r", MACH_M32R, 32, 32, & m32r_models[0], & m32rbf_imp_properties, m32r_init_cpu, m32rbf_prepare_run diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c index b729074..673b836 100644 --- a/sim/m32r/sem-switch.c +++ b/sim/m32r/sem-switch.c @@ -508,8 +508,8 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); { @@ -522,7 +522,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -537,8 +537,8 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16)); temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0); { @@ -551,7 +551,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -566,8 +566,8 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); { @@ -580,7 +580,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -821,7 +821,7 @@ if (NESI (* FLD (i_src2), 0)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (ANDSI (pc, -4), 4); CPU (h_gr[((UINT) 14)]) = opval; @@ -832,7 +832,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -849,7 +849,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ { SI opval = ADDSI (pc, 4); CPU (h_gr[((UINT) 14)]) = opval; @@ -860,7 +860,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -1162,8 +1162,8 @@ if (NESI (* FLD (i_sr), 0)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - USI temp1;SI temp0; +{ + SI temp0;USI temp1; temp0 = ADDSI (ANDSI (pc, -4), 4); temp1 = ANDSI (* FLD (i_sr), -4); { @@ -1176,7 +1176,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -1403,8 +1403,8 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - SI temp1;SI temp0; +{ + SI temp0;SI temp1; temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); temp1 = ADDSI (* FLD (i_sr), 4); { @@ -1417,7 +1417,7 @@ do { * FLD (i_sr) = opval; TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); } -} while (0); +} #undef FLD } @@ -1489,18 +1489,18 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = 1; CPU (h_lock) = opval; - TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); * FLD (i_dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } -} while (0); +} #undef FLD } @@ -1891,7 +1891,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp1; tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1); tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); @@ -1900,7 +1900,7 @@ do { SET_H_ACCUM (opval); TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); } -} while (0); +} #undef FLD } @@ -1915,7 +1915,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp1; tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff)); if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { @@ -1933,7 +1933,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 SET_H_ACCUM (opval); TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); } -} while (0); +} #undef FLD } @@ -1949,7 +1949,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -1963,14 +1963,14 @@ do { { UQI opval = CPU (h_bpsw); SET_H_PSW (opval); - TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); } { UQI opval = CPU (h_bbpsw); CPU (h_bpsw) = opval; - TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -2290,7 +2290,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_new_src2; tmp_new_src2 = ADDSI (* FLD (i_src2), 4); { @@ -2303,7 +2303,7 @@ do { * FLD (i_src2) = opval; TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval); } -} while (0); +} #undef FLD } @@ -2318,7 +2318,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_new_src2; tmp_new_src2 = SUBSI (* FLD (i_src2), 4); { @@ -2331,7 +2331,7 @@ do { * FLD (i_src2) = opval; TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval); } -} while (0); +} #undef FLD } @@ -2365,8 +2365,8 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); { @@ -2379,7 +2379,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -2394,8 +2394,8 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); { @@ -2408,7 +2408,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -2424,7 +2424,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GET_H_CR (((UINT) 6)); SET_H_CR (((UINT) 14), opval); @@ -2438,24 +2438,24 @@ do { { UQI opval = CPU (h_bpsw); CPU (h_bbpsw) = opval; - TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); } { UQI opval = GET_H_PSW (); CPU (h_bpsw) = opval; - TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); } { UQI opval = ANDQI (GET_H_PSW (), 128); SET_H_PSW (opval); - TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); } { SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -2471,7 +2471,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_lock)) { { SI opval = * FLD (i_src1); @@ -2483,9 +2483,9 @@ if (CPU (h_lock)) { { BI opval = 0; CPU (h_lock) = opval; - TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c index 62fe70c..03b0a6f 100644 --- a/sim/m32r/sem.c +++ b/sim/m32r/sem.c @@ -380,8 +380,8 @@ SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr)); temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0); { @@ -394,7 +394,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -411,8 +411,8 @@ SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16)); temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0); { @@ -425,7 +425,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -442,8 +442,8 @@ SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); { @@ -456,7 +456,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -717,7 +717,7 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (ANDSI (pc, -4), 4); CPU (h_gr[((UINT) 14)]) = opval; @@ -728,7 +728,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -747,7 +747,7 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -do { +{ { SI opval = ADDSI (pc, 4); CPU (h_gr[((UINT) 14)]) = opval; @@ -758,7 +758,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -1088,8 +1088,8 @@ SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - USI temp1;SI temp0; +{ + SI temp0;USI temp1; temp0 = ADDSI (ANDSI (pc, -4), 4); temp1 = ANDSI (* FLD (i_sr), -4); { @@ -1102,7 +1102,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -1353,8 +1353,8 @@ SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - SI temp1;SI temp0; +{ + SI temp0;SI temp1; temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr)); temp1 = ADDSI (* FLD (i_sr), 4); { @@ -1367,7 +1367,7 @@ do { * FLD (i_sr) = opval; TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1447,18 +1447,18 @@ SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = 1; CPU (h_lock) = opval; - TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); } { SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr)); * FLD (i_dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1891,7 +1891,7 @@ SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp1; tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1); tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); @@ -1900,7 +1900,7 @@ do { SET_H_ACCUM (opval); TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); } -} while (0); +} return vpc; #undef FLD @@ -1917,7 +1917,7 @@ SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp1; tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff)); if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) { @@ -1935,7 +1935,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 SET_H_ACCUM (opval); TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); } -} while (0); +} return vpc; #undef FLD @@ -1953,7 +1953,7 @@ SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -1967,14 +1967,14 @@ do { { UQI opval = CPU (h_bpsw); SET_H_PSW (opval); - TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); } { UQI opval = CPU (h_bbpsw); CPU (h_bpsw) = opval; - TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -2328,7 +2328,7 @@ SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_new_src2; tmp_new_src2 = ADDSI (* FLD (i_src2), 4); { @@ -2341,7 +2341,7 @@ do { * FLD (i_src2) = opval; TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2358,7 +2358,7 @@ SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_new_src2; tmp_new_src2 = SUBSI (* FLD (i_src2), 4); { @@ -2371,7 +2371,7 @@ do { * FLD (i_src2) = opval; TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2409,8 +2409,8 @@ SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr)); temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0); { @@ -2423,7 +2423,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2440,8 +2440,8 @@ SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { - BI temp1;SI temp0; +{ + SI temp0;BI temp1; temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond)); { @@ -2454,7 +2454,7 @@ do { CPU (h_cond) = opval; TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2472,7 +2472,7 @@ SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GET_H_CR (((UINT) 6)); SET_H_CR (((UINT) 14), opval); @@ -2486,24 +2486,24 @@ do { { UQI opval = CPU (h_bpsw); CPU (h_bbpsw) = opval; - TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval); } { UQI opval = GET_H_PSW (); CPU (h_bpsw) = opval; - TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval); } { UQI opval = ANDQI (GET_H_PSW (), 128); SET_H_PSW (opval); - TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval); } { SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -2521,7 +2521,7 @@ SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_lock)) { { SI opval = * FLD (i_src1); @@ -2533,9 +2533,9 @@ if (CPU (h_lock)) { { BI opval = 0; CPU (h_lock) = opval; - TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c index 6116af8..3ef5a31 100644 --- a/sim/m32r/sim-if.c +++ b/sim/m32r/sim-if.c @@ -155,8 +155,8 @@ sim_open (kind, callback, abfd, argv) /* Open a copy of the cpu descriptor table. */ { - CGEN_CPU_DESC cd = m32r_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach, - CGEN_ENDIAN_BIG); + CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, + CGEN_ENDIAN_BIG); for (i = 0; i < MAX_NR_PROCESSORS; ++i) { SIM_CPU *cpu = STATE_CPU (sd, i); diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index c81a862..f3009f3 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -59,9 +59,18 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, { a_m32r_h_cr_set (current_cpu, H_CR_BBPC, a_m32r_h_cr_get (current_cpu, H_CR_BPC)); - a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu)); - /* sm not changed */ - a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80); + if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R) + { + m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu)); + /* sm not changed */ + m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); + } + else + { + m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); + /* sm not changed */ + m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); + } a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia); sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index bb8ac40..2efd41a 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,24 @@ +1999-04-21 Frank Ch. Eigler <fche@cygnus.com> + + * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub. + +Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com> + + * configure.in: Any mips64vr5*-*-* target should have + -DTARGET_ENABLE_FR=1. + (default_endian): Any mips64vr*el-*-* target should default to + LITTLE_ENDIAN. + * configure: Re-generate. + +1999-02-19 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.igen (ldl): Extend from _16_, not 32. + +Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com> + + * interp.c (sim_store_register): Force registers written to by GDB + into an un-interpreted state. + 1999-02-05 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the diff --git a/sim/mips/configure b/sim/mips/configure index 58be065..fe3e2d2 100755 --- a/sim/mips/configure +++ b/sim/mips/configure @@ -135,7 +135,7 @@ sim_inline="-DDEFAULT_INLINE=0" # Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.12.2 +# Generated automatically using autoconf version 2.13 # Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. # # This configure script is free software; the Free Software Foundation @@ -511,7 +511,7 @@ EOF verbose=yes ;; -version | --version | --versio | --versi | --vers) - echo "configure generated by autoconf version 2.12.2" + echo "configure generated by autoconf version 2.13" exit 0 ;; -with-* | --with-*) @@ -1062,7 +1062,7 @@ else #endif EOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - egrep "off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then rm -rf conftest* ac_cv_type_off_t=yes else @@ -1095,7 +1095,7 @@ else #endif EOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - egrep "size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then rm -rf conftest* ac_cv_type_size_t=yes else @@ -1755,7 +1755,8 @@ else ac_cv_prog_CC="$CC" # Let the user override the test. else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_prog_CC="gcc" @@ -1776,7 +1777,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1780: checking for $ac_word" >&5 +echo "configure:1781: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1785,7 +1786,8 @@ else else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" ac_prog_rejected=no - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then @@ -1826,7 +1828,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1830: checking for $ac_word" >&5 +echo "configure:1832: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1834,7 +1836,8 @@ else ac_cv_prog_CC="$CC" # Let the user override the test. else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_prog_CC="cl" @@ -1857,7 +1860,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:1861: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:1864: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -1866,12 +1869,14 @@ ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' cross_compiling=$ac_cv_prog_cc_cross -cat > conftest.$ac_ext <<EOF -#line 1871 "configure" +cat > conftest.$ac_ext << EOF + +#line 1875 "configure" #include "confdefs.h" + main(){return(0);} EOF -if { (eval echo configure:1875: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1880: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -1885,18 +1890,24 @@ else ac_cv_prog_cc_works=no fi rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:1895: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:1906: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:1900: checking whether we are using GNU C" >&5 +echo "configure:1911: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1905,7 +1916,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1909: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1920: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -1924,7 +1935,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:1928: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:1939: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1967,7 +1978,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:1971: checking for a BSD compatible install" >&5 +echo "configure:1982: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -2015,6 +2026,8 @@ echo "$ac_t""$INSTALL" 1>&6 # It thinks the first close brace ends the variable substitution. test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' + test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' @@ -2033,7 +2046,7 @@ AR=${AR-ar} # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2037: checking for $ac_word" >&5 +echo "configure:2050: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2041,7 +2054,8 @@ else ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_prog_RANLIB="ranlib" @@ -2067,17 +2081,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2071: checking for $ac_hdr" >&5 +echo "configure:2085: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2076 "configure" +#line 2090 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2081: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2095: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2107,12 +2121,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2111: checking for $ac_func" >&5 +echo "configure:2125: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2116 "configure" +#line 2130 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2135,7 +2149,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2139: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2153: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2164,12 +2178,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2168: checking for $ac_func" >&5 +echo "configure:2182: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2173 "configure" +#line 2187 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2192,7 +2206,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2196: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2210: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2226,19 +2240,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:2230: checking for LC_MESSAGES" >&5 +echo "configure:2244: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2235 "configure" +#line 2249 "configure" #include "confdefs.h" #include <locale.h> int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:2242: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2256: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -2259,7 +2273,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:2263: checking whether NLS is requested" >&5 +echo "configure:2277: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -2279,7 +2293,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:2283: checking whether included gettext is requested" >&5 +echo "configure:2297: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -2298,17 +2312,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:2302: checking for libintl.h" >&5 +echo "configure:2316: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2307 "configure" +#line 2321 "configure" #include "confdefs.h" #include <libintl.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2312: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2326: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2325,19 +2339,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:2329: checking for gettext in libc" >&5 +echo "configure:2343: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2334 "configure" +#line 2348 "configure" #include "confdefs.h" #include <libintl.h> int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:2341: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2355: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -2353,7 +2367,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:2357: checking for bindtextdomain in -lintl" >&5 +echo "configure:2371: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -2361,7 +2375,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <<EOF -#line 2365 "configure" +#line 2379 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -2372,7 +2386,7 @@ int main() { bindtextdomain() ; return 0; } EOF -if { (eval echo configure:2376: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2390: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -2388,19 +2402,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:2392: checking for gettext in libintl" >&5 +echo "configure:2406: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2397 "configure" +#line 2411 "configure" #include "confdefs.h" int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:2404: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2418: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -2428,7 +2442,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2432: checking for $ac_word" >&5 +echo "configure:2446: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2462,12 +2476,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:2466: checking for $ac_func" >&5 +echo "configure:2480: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2471 "configure" +#line 2485 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -2490,7 +2504,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:2494: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2508: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -2517,7 +2531,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2521: checking for $ac_word" >&5 +echo "configure:2535: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2530,7 +2544,8 @@ else ;; *) IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_path_GMSGFMT="$ac_dir/$ac_word" @@ -2552,7 +2567,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2556: checking for $ac_word" >&5 +echo "configure:2571: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2584,7 +2599,7 @@ else fi cat > conftest.$ac_ext <<EOF -#line 2588 "configure" +#line 2603 "configure" #include "confdefs.h" int main() { @@ -2592,7 +2607,7 @@ extern int _nl_msg_cat_cntr; return _nl_msg_cat_cntr ; return 0; } EOF -if { (eval echo configure:2596: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2611: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -2624,7 +2639,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2628: checking for $ac_word" >&5 +echo "configure:2643: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2658,7 +2673,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2662: checking for $ac_word" >&5 +echo "configure:2677: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2671,7 +2686,8 @@ else ;; *) IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - for ac_dir in $PATH; do + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$ac_word; then ac_cv_path_GMSGFMT="$ac_dir/$ac_word" @@ -2693,7 +2709,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2697: checking for $ac_word" >&5 +echo "configure:2713: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2783,7 +2799,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:2787: checking for catalogs to be installed" >&5 +echo "configure:2803: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -2811,17 +2827,17 @@ echo "configure:2787: checking for catalogs to be installed" >&5 if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:2815: checking for linux/version.h" >&5 +echo "configure:2831: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2820 "configure" +#line 2836 "configure" #include "confdefs.h" #include <linux/version.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2825: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2841: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2890,17 +2906,17 @@ for ac_hdr in stdlib.h string.h strings.h unistd.h time.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2894: checking for $ac_hdr" >&5 +echo "configure:2910: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2899 "configure" +#line 2915 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2904: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2920: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2930,17 +2946,17 @@ for ac_hdr in sys/time.h sys/resource.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2934: checking for $ac_hdr" >&5 +echo "configure:2950: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2939 "configure" +#line 2955 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2944: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2960: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2970,17 +2986,17 @@ for ac_hdr in fcntl.h fpu_control.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:2974: checking for $ac_hdr" >&5 +echo "configure:2990: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2979 "configure" +#line 2995 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2984: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3000: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3010,17 +3026,17 @@ for ac_hdr in dlfcn.h errno.h sys/stat.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3014: checking for $ac_hdr" >&5 +echo "configure:3030: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3019 "configure" +#line 3035 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3024: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3040: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3049,12 +3065,12 @@ done for ac_func in getrusage time sigaction __setfpucw do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3053: checking for $ac_func" >&5 +echo "configure:3069: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3058 "configure" +#line 3074 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3077,7 +3093,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3081: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3097: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3104,7 +3120,7 @@ done # Check for socket libraries echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6 -echo "configure:3108: checking for bind in -lsocket" >&5 +echo "configure:3124: checking for bind in -lsocket" >&5 ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3112,7 +3128,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lsocket $LIBS" cat > conftest.$ac_ext <<EOF -#line 3116 "configure" +#line 3132 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3123,7 +3139,7 @@ int main() { bind() ; return 0; } EOF -if { (eval echo configure:3127: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3143: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3151,7 +3167,7 @@ else fi echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6 -echo "configure:3155: checking for gethostbyname in -lnsl" >&5 +echo "configure:3171: checking for gethostbyname in -lnsl" >&5 ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3159,7 +3175,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lnsl $LIBS" cat > conftest.$ac_ext <<EOF -#line 3163 "configure" +#line 3179 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3170,7 +3186,7 @@ int main() { gethostbyname() ; return 0; } EOF -if { (eval echo configure:3174: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3190: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3346,12 +3362,12 @@ fi echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 -echo "configure:3350: checking return type of signal handlers" >&5 +echo "configure:3366: checking return type of signal handlers" >&5 if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3355 "configure" +#line 3371 "configure" #include "confdefs.h" #include <sys/types.h> #include <signal.h> @@ -3368,7 +3384,7 @@ int main() { int i; ; return 0; } EOF -if { (eval echo configure:3372: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:3388: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_type_signal=void else @@ -3388,7 +3404,7 @@ EOF echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:3392: checking for executable suffix" >&5 +echo "configure:3408: checking for executable suffix" >&5 if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3541,14 +3557,14 @@ else if test "x$cross_compiling" = "xno"; then echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6 -echo "configure:3545: checking whether byte ordering is bigendian" >&5 +echo "configure:3561: checking whether byte ordering is bigendian" >&5 if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_bigendian=unknown # See if sys/param.h defines the BYTE_ORDER macro. cat > conftest.$ac_ext <<EOF -#line 3552 "configure" +#line 3568 "configure" #include "confdefs.h" #include <sys/types.h> #include <sys/param.h> @@ -3559,11 +3575,11 @@ int main() { #endif ; return 0; } EOF -if { (eval echo configure:3563: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:3579: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* # It does; now see whether it defined to BIG_ENDIAN or not. cat > conftest.$ac_ext <<EOF -#line 3567 "configure" +#line 3583 "configure" #include "confdefs.h" #include <sys/types.h> #include <sys/param.h> @@ -3574,7 +3590,7 @@ int main() { #endif ; return 0; } EOF -if { (eval echo configure:3578: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:3594: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_bigendian=yes else @@ -3594,7 +3610,7 @@ if test "$cross_compiling" = yes; then { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; } else cat > conftest.$ac_ext <<EOF -#line 3598 "configure" +#line 3614 "configure" #include "confdefs.h" main () { /* Are we little or big endian? From Harbison&Steele. */ @@ -3607,7 +3623,7 @@ main () { exit (u.c[sizeof (long) - 1] == 1); } EOF -if { (eval echo configure:3611: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3627: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_bigendian=no else @@ -3683,6 +3699,7 @@ mips_endian= default_endian= case "${target}" in mips64el*-*-*) mips_endian=LITTLE_ENDIAN ;; + mips64vr*el-*-*) default_endian=LITTLE_ENDIAN ;; mips64*-*-*) default_endian=BIG_ENDIAN ;; mips16*-*-*) default_endian=BIG_ENDIAN ;; mips*-*-*) default_endian=BIG_ENDIAN ;; @@ -4021,7 +4038,7 @@ esac # Uses ac_ vars as temps to allow command line to override cache and checks. # --without-x overrides everything else, but does not touch the cache. echo $ac_n "checking for X""... $ac_c" 1>&6 -echo "configure:4125: checking for X" >&5 +echo "configure:4142: checking for X" >&5 # Check whether --with-x or --without-x was given. if test "${with_x+set}" = set; then @@ -4083,12 +4100,12 @@ if test "$ac_x_includes" = NO; then # First, try using that file with no special directory specified. cat > conftest.$ac_ext <<EOF -#line 4187 "configure" +#line 4204 "configure" #include "confdefs.h" #include <$x_direct_test_include> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4192: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4209: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4157,14 +4174,14 @@ if test "$ac_x_libraries" = NO; then ac_save_LIBS="$LIBS" LIBS="-l$x_direct_test_library $LIBS" cat > conftest.$ac_ext <<EOF -#line 4261 "configure" +#line 4278 "configure" #include "confdefs.h" int main() { ${x_direct_test_function}() ; return 0; } EOF -if { (eval echo configure:4268: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4285: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* LIBS="$ac_save_LIBS" # We can link X programs with no special library path. @@ -4257,17 +4274,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:5155: checking for $ac_hdr" >&5 +echo "configure:5172: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5160 "configure" +#line 5177 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:5165: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:5182: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4294,7 +4311,7 @@ fi done echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6 -echo "configure:5192: checking for fabs in -lm" >&5 +echo "configure:5209: checking for fabs in -lm" >&5 ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4302,7 +4319,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lm $LIBS" cat > conftest.$ac_ext <<EOF -#line 5200 "configure" +#line 5217 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -4313,7 +4330,7 @@ int main() { fabs() ; return 0; } EOF -if { (eval echo configure:5211: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5228: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -4343,12 +4360,12 @@ fi for ac_func in aint anint sqrt do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:5241: checking for $ac_func" >&5 +echo "configure:5258: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5246 "configure" +#line 5263 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -4371,7 +4388,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:5269: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5286: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4421,7 +4438,7 @@ EOF # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. (set) 2>&1 | - case `(ac_space=' '; set) 2>&1 | grep ac_space` in + case `(ac_space=' '; set | grep ac_space) 2>&1` in *ac_space=\ *) # `set' does not quote correctly, so add quotes (double-quote substitution # turns \\\\ into \\, and sed turns \\ into \). @@ -4488,7 +4505,7 @@ do echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; -version | --version | --versio | --versi | --vers | --ver | --ve | --v) - echo "$CONFIG_STATUS generated by autoconf version 2.12.2" + echo "$CONFIG_STATUS generated by autoconf version 2.13" exit 0 ;; -help | --help | --hel | --he | --h) echo "\$ac_cs_usage"; exit 0 ;; @@ -4532,6 +4549,7 @@ s%@SHELL@%$SHELL%g s%@CFLAGS@%$CFLAGS%g s%@CPPFLAGS@%$CPPFLAGS%g s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g s%@DEFS@%$DEFS%g s%@LDFLAGS@%$LDFLAGS%g s%@LIBS@%$LIBS%g @@ -4567,6 +4585,7 @@ s%@build_vendor@%$build_vendor%g s%@build_os@%$build_os%g s%@CC@%$CC%g s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g +s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g s%@INSTALL_DATA@%$INSTALL_DATA%g s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g s%@HDEFINES@%$HDEFINES%g diff --git a/sim/mips/configure.in b/sim/mips/configure.in index 89959fe..bff4bc3 100644 --- a/sim/mips/configure.in +++ b/sim/mips/configure.in @@ -32,6 +32,7 @@ mips_endian= default_endian= case "${target}" in mips64el*-*-*) mips_endian=LITTLE_ENDIAN ;; + mips64vr*el-*-*) default_endian=LITTLE_ENDIAN ;; mips64*-*-*) default_endian=BIG_ENDIAN ;; mips16*-*-*) default_endian=BIG_ENDIAN ;; mips*-*-*) default_endian=BIG_ENDIAN ;; diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 75bc54b..a2ed20f 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -750,6 +750,7 @@ sim_store_register (sd,rn,memory,length) if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) { + cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted; if (cpu->register_widths[rn] == 32) { cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index bfc209a..66c475a 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1551,7 +1551,7 @@ *vr5000: *r3900: { - GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT])); + GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); } @@ -3738,6 +3738,14 @@ *vr4100: *vr5000: +010000,01000,00000,16.OFFSET:COP0:32::BC0F +"bc0f <OFFSET>" +// stub needed for eCos as tx39 hardware bug workaround +*r3900: +{ + /* do nothing */ +} + 010000,01000,00010,16.OFFSET:COP0:32::BC0FL "bc0fl <OFFSET>" diff --git a/sim/mn10200/ChangeLog b/sim/mn10200/ChangeLog index ce38f13..1eb7fbd 100644 --- a/sim/mn10200/ChangeLog +++ b/sim/mn10200/ChangeLog @@ -1,3 +1,18 @@ +1999-04-06 Keith Seitz <keiths@cygnus.com> + + * interp.c (sim_stop): Set the sim's exception + to SIGINT. + +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * interp.c (UI_LOOP_POLL_INTERVAL): Define. Used to tweak the + frequency at which ui_loop_hook is called. + (ui_loop_hook_counter): New global defined when NEED_UI_LOOP_HOOK + is defined. + (sim_resume): Call ui_loop_hook (if defined) when the interval + passes. + * Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK. + Wed Jun 17 11:37:59 1998 Mark Alexander <marka@cygnus.com> * Makefile.in: Define NL_TARGET so that targ-vals.h will be used diff --git a/sim/mn10200/Makefile.in b/sim/mn10200/Makefile.in index dd9581c..e19d9e7 100644 --- a/sim/mn10200/Makefile.in +++ b/sim/mn10200/Makefile.in @@ -19,7 +19,7 @@ ## COMMON_PRE_CONFIG_FRAG SIM_OBJS = interp.o table.o simops.o sim-load.o -SIM_EXTRA_CFLAGS = -I$(srcdir)/../../newlib/libc/sys/sysmec +SIM_EXTRA_CFLAGS = -I$(srcdir)/../../newlib/libc/sys/sysmec -DNEED_UI_LOOP_HOOK SIM_EXTRA_CLEAN = clean-extra # Select mn10200 support in nltvals.def. diff --git a/sim/mn10200/interp.c b/sim/mn10200/interp.c index df95b7c..43a8750 100644 --- a/sim/mn10200/interp.c +++ b/sim/mn10200/interp.c @@ -4,6 +4,17 @@ #include "mn10200_sim.h" +#ifdef NEED_UI_LOOP_HOOK +/* How often to run the ui_loop update, when in use */ +#define UI_LOOP_POLL_INTERVAL 0x60000 + +/* Counter for the ui_loop_hook update */ +static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + +/* Actual hook to call to run through gdb's gui event loop */ +extern int (*ui_loop_hook) (int); +#endif /* NEED_UI_LOOP_HOOK */ + host_callback *mn10200_callback; int mn10200_debug; static SIM_OPEN_KIND sim_kind; @@ -292,7 +303,8 @@ int sim_stop (sd) SIM_DESC sd; { - return 0; + State.exception = SIGINT; + return 1; } void @@ -313,6 +325,14 @@ sim_resume (sd, step, siggnal) { unsigned long insn, extension; +#ifdef NEED_UI_LOOP_HOOK + if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) + { + ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + ui_loop_hook (0); + } +#endif /* NEED_UI_LOOP_HOOK */ + /* Fetch the current instruction, fetch a double word to avoid redundant fetching for the common cases below. */ inst = load_mem_big (PC, 2); diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index d992099..161acf2 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,28 @@ +1999-04-16 Frank Ch. Eigler <fche@cygnus.com> + + * interp.c (program_interrupt): Detect undesired recursion using + static flag. Set NMIRC register's SYSEF flag during + --board=stdeval1 mode. + * dv-mn103-int.c (write_icr): Add backdoor address to allow CPU to + set SYSEF flag. + +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * Makefile.in (SIM_EXTRA_CFLAGS): Define a POLL_QUIT_INTERVAL + for use in the simulator so that the poll_quit callback is + not called too often. + +Tue Mar 9 21:26:41 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * dv-mn103int.c (mn103int_ioctl): Return something. + * dv-mn103tim.c (write_tm6md): GCC suggested parentheses around && + within ||. + +Tue Feb 16 23:57:17 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.igen (retf): Fix return address computation and store + the new pc value into nia. + 1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o. diff --git a/sim/mn10300/Makefile.in b/sim/mn10300/Makefile.in index f5123c4..612576c 100644 --- a/sim/mn10300/Makefile.in +++ b/sim/mn10300/Makefile.in @@ -51,7 +51,7 @@ NL_TARGET = -DNL_TARGET_mn10300 INCLUDE = mn10300_sim.h $(srcdir)/../../include/callback.h # List of extra flags to always pass to $(CC). -SIM_EXTRA_CFLAGS = @sim_gen@ +SIM_EXTRA_CFLAGS = @sim_gen@ -DPOLL_QUIT_INTERVAL=0x20 ## COMMON_POST_CONFIG_FRAG diff --git a/sim/mn10300/dv-mn103int.c b/sim/mn10300/dv-mn103int.c index 11982fb..d64e007 100644 --- a/sim/mn10300/dv-mn103int.c +++ b/sim/mn10300/dv-mn103int.c @@ -585,6 +585,12 @@ write_icr (struct hw *me, group->gid, val)); group->request &= ~EXTRACT_ID (val); break; + /* Special backdoor access to SYSEF flag from CPU. See + interp.c:program_interrupt(). */ + case 3: + HW_TRACE ((me, "write-icr-special group=%d:0 nmi 0x%02x", + group->gid, val)); + group->request |= EXTRACT_ID (val); default: break; } @@ -815,6 +821,7 @@ mn103int_ioctl(struct hw *me, struct mn103int *controller = (struct mn103int *)hw_data(me); controller->group[0].request = EXTRACT_ID(4); mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0); + return 0; } diff --git a/sim/mn10300/dv-mn103tim.c b/sim/mn10300/dv-mn103tim.c index d93bb71..cd79f91 100644 --- a/sim/mn10300/dv-mn103tim.c +++ b/sim/mn10300/dv-mn103tim.c @@ -842,7 +842,7 @@ write_tm6md (struct hw *me, unsigned_word offset = address - timers->block[0].base; - if ( offset != 0x84 && nr_bytes > 1 || nr_bytes > 2 ) + if ((offset != 0x84 && nr_bytes > 1) || nr_bytes > 2 ) { hw_abort (me, "Bad write size of %d bytes to TM6MD", nr_bytes); } diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c index d5e833e..12dffff 100644 --- a/sim/mn10300/interp.c +++ b/sim/mn10300/interp.c @@ -1329,19 +1329,39 @@ program_interrupt (SIM_DESC sd, { int status; struct hw *device; + static int in_interrupt = 0; #ifdef SIM_CPU_EXCEPTION_TRIGGER SIM_CPU_EXCEPTION_TRIGGER(sd,cpu,cia); #endif - /* copy NMI handler code from dv-mn103cpu.c */ - /* XXX: possible infinite recursion if these store_*() calls fail! */ - store_word (SP - 4, CIA_GET (cpu)); - store_half (SP - 8, PSW); + /* avoid infinite recursion */ + if (in_interrupt) + { + (*mn10300_callback->printf_filtered) (mn10300_callback, + "ERROR: recursion in program_interrupt during software exception dispatch."); + } + else + { + in_interrupt = 1; + /* copy NMI handler code from dv-mn103cpu.c */ + store_word (SP - 4, CIA_GET (cpu)); + store_half (SP - 8, PSW); + + /* Set the SYSEF flag in NMICR by backdoor method. See + dv-mn103int.c:write_icr(). This is necessary because + software exceptions are not modelled by actually talking to + the interrupt controller, so it cannot set its own SYSEF + flag. */ + if ((NULL != board) && (strcmp(board, BOARD_AM32) == 0)) + store_byte (0x34000103, 0x04); + } + PSW &= ~PSW_IE; SP = SP - 8; CIA_SET (cpu, 0x40000008); + in_interrupt = 0; sim_engine_halt(sd, cpu, NULL, cia, sim_stopped, sig); } diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen index 7c4f03d..1b42db4 100644 --- a/sim/mn10300/mn10300.igen +++ b/sim/mn10300/mn10300.igen @@ -3486,7 +3486,7 @@ PC = cia; State.regs[REG_SP] += IMM8; sp = State.regs[REG_SP]; - State.regs[REG_PC] = State.regs[REG_MDR] - 3; + State.regs[REG_PC] = State.regs[REG_MDR]; offset = -4; mask = REGS; @@ -3533,5 +3533,6 @@ State.regs[REG_LAR] = load_word (sp + offset); offset -= 4; } + nia = PC; } diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 49cf8ce..93312f0 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,3 +1,21 @@ +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * sim_calls.c (POLL_QUIT_INTERVAL): Define. Used to tweak + the frequency at which the poll_quit callback is called. + (poll_quit_count): New global. + (sim_io_poll_quit): Only call the poll_quit callback + after the specified POLL_QUIT_INTERVAL. + +1999-02-22 Jim Lemke <jlemke@cygnus.com> + + * dc-complex: Force expansion on all bits of field BO. + Previously, the least-significant (prediction) bit was ignored. + * ppc-instructions (conditional branches): Implement mpc860c0 option. + * igen.c (gen_semantics_[ch]): Setup for mpc860c0 option. + * psim.c (is_num, psim_options): Added parsing for mpc860c0 option. + * interrupts.h: Added "mpc860c0_instruction_program_interrupt". + * interrupts.c (program_interrupt): Added handling for above interrupt. + 1999-02-01 Jim Blandy <jimb@zwingli.cygnus.com> Make the simulator compatible with the MPC750. It would be nicer diff --git a/sim/ppc/dc-complex b/sim/ppc/dc-complex index 13361ec..34a5861 100644 --- a/sim/ppc/dc-complex +++ b/sim/ppc/dc-complex @@ -20,9 +20,9 @@ array,normal: 0: 5: 0: 5: array,normal: 21:31:32:-1:OE,LR,AA,Rc,LK: ## -## Branch Conditional instruction - Expand BO{0:4} only, ignore BO{5} +## Branch Conditional instruction - Expand BO{0:4} ## -array,expand-forced: 6: 9: 6: 9:BO: 0xfc000000:0x40000000 +array,expand-forced: 6:10: 6:10:BO: 0xfc000000:0x40000000 ## ## Expand RA on equality with 0 in Add instructions were if(RA==0) appears. ## diff --git a/sim/ppc/igen.c b/sim/ppc/igen.c index dc87087..94dcf51 100644 --- a/sim/ppc/igen.c +++ b/sim/ppc/igen.c @@ -181,14 +181,12 @@ gen_semantics_h(insn_table *table, SEMANTIC_FUNCTION_FORMAL); lf_printf(file, "\n"); if ((code & generate_calls)) { - lf_printf(file, "#ifdef WITH_OPTION_MPC860C0\n"); lf_printf(file, "extern int option_mpc860c0;\n"); lf_printf(file, "#define PAGE_SIZE 0x1000\n"); lf_printf(file, "\n"); lf_printf(file, "EXTERN_SEMANTICS(void)\n"); lf_printf(file, "semantic_init(device* root);\n"); lf_printf(file, "\n"); - lf_printf(file, "#endif // WITH_OPTION_MPC860C0\n"); if (generate_expanded_instructions) insn_table_traverse_tree(table, file, NULL, @@ -222,7 +220,6 @@ gen_semantics_c(insn_table *table, lf_printf(file, "#include \"semantics.h\"\n"); lf_printf(file, "#include \"support.h\"\n"); lf_printf(file, "\n"); - lf_printf(file, "#ifdef WITH_OPTION_MPC860C0\n"); lf_printf(file, "int option_mpc860c0 = 0;\n"); lf_printf(file, "\n"); lf_printf(file, "EXTERN_SEMANTICS(void)\n"); @@ -231,9 +228,9 @@ gen_semantics_c(insn_table *table, lf_printf(file, " option_mpc860c0 = 0;\n"); lf_printf(file, " if (tree_find_property(root, \"/options/mpc860c0\"))\n"); lf_printf(file, " option_mpc860c0 = tree_find_integer_property(root, \"/options/mpc860c0\");\n"); + lf_printf(file, " option_mpc860c0 *= 4; /* convert word count to byte count */\n"); lf_printf(file, "}\n"); lf_printf(file, "\n"); - lf_printf(file, "#endif // WITH_OPTION_MPC860C0\n"); if (generate_expanded_instructions) insn_table_traverse_tree(table, file, cache_rules, diff --git a/sim/ppc/interrupts.c b/sim/ppc/interrupts.c index 7a13f76..deab7e9 100644 --- a/sim/ppc/interrupts.c +++ b/sim/ppc/interrupts.c @@ -315,12 +315,10 @@ program_interrupt(cpu *processor, cpu_error(processor, cia, "program interrupt - %s", "illegal instruction (optional instruction not supported)"); break; -#ifdef WITH_OPTION_MPC860C0 case mpc860c0_instruction_program_interrupt: cpu_error(processor, cia, "program interrupt - %s", "problematic branch detected, see MPC860 C0 errata"); break; -#endif // WITH_OPTION_MPC860C0 default: error("internal error - program_interrupt - reason %d not implemented", reason); } @@ -342,13 +340,11 @@ program_interrupt(cpu *processor, case trap_program_interrupt: srr1_set = srr1_trap; break; -#ifdef WITH_OPTION_MPC860C0 case mpc860c0_instruction_program_interrupt: srr1_set = 0; - error(processor, cia, "program interrupt - %s", + cpu_error(processor, cia, "program interrupt - %s", "problematic branch detected, see MPC860 C0 errata"); break; -#endif // WITH_OPTION_MPC860C0 default: srr1_set = 0; error("internal error - program_interrupt - reason %d not implemented", reason); diff --git a/sim/ppc/interrupts.h b/sim/ppc/interrupts.h index 6e87b77..93447a8 100644 --- a/sim/ppc/interrupts.h +++ b/sim/ppc/interrupts.h @@ -94,9 +94,7 @@ typedef enum { privileged_instruction_program_interrupt, trap_program_interrupt, optional_instruction_program_interrupt, /* subset of illegal instruction */ -#ifdef WITH_OPTION_MPC860C0 mpc860c0_instruction_program_interrupt, /* fwd br, taken but not predicted, near EO page */ -#endif // WITH_OPTION_MPC860C0 nr_program_interrupt_reasons } program_interrupt_reasons; diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions index 6ebe081..cfbac64 100644 --- a/sim/ppc/ppc-instructions +++ b/sim/ppc/ppc-instructions @@ -1440,7 +1440,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, *603: PPC_UNIT_BPU, PPC_UNIT_BPU, 1, 1, 0 *603e:PPC_UNIT_BPU, PPC_UNIT_BPU, 1, 1, 0 *604: PPC_UNIT_BPU, PPC_UNIT_BPU, 1, 1, 0 - /* WITH_OPTION_MPC860C0 + /* option_mpc860c0: No problem here because this branch is predicted taken (unconditional). */ if (AA) NIA = IEA(EXTS(LI_0b00)); else NIA = IEA(CIA + EXTS(LI_0b00)); @@ -1469,9 +1469,8 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, else succeed = 0; if (LK) LR = (spreg)IEA(CIA + 4); - #ifdef WITH_OPTION_MPC860C0 - if (option_mpc860c0 && (BO{0} && BO{2} || !BO{4})) { - /* This branch is predicted as not-taken. + if (option_mpc860c0 && (!BO{0} || !BO{2}) && !BO{4}) { + /* This branch is predicted as "normal". If this is a forward branch and it is near the end of a page, we've detected a problematic branch. */ if (succeed && NIA > CIA) { @@ -1479,7 +1478,6 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, program_interrupt(processor, cia, mpc860c0_instruction_program_interrupt); } } - #endif // WITH_OPTION_MPC860C0 if (CURRENT_MODEL_ISSUE > 0) model_branches(cpu_model(processor), succeed, BO); if (! BO{0}) { @@ -1513,8 +1511,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, else succeed = 0; if (LK) LR = (spreg)IEA(CIA + 4); - #ifdef WITH_OPTION_MPC860C0 - if (option_mpc860c0 && (BO{0} && BO{2} || !BO{4})) { + if (option_mpc860c0 && (!BO{0} || !BO{2}) && !BO{4}) { /* This branch is predicted as not-taken. If this is a forward branch and it is near the end of a page, we've detected a problematic branch. */ @@ -1523,7 +1520,6 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, program_interrupt(processor, cia, mpc860c0_instruction_program_interrupt); } } - #endif // WITH_OPTION_MPC860C0 if (CURRENT_MODEL_ISSUE > 0) { model_branches(cpu_model(processor), succeed, BO); if (! BO{0}) @@ -1546,8 +1542,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, else succeed = 0; if (LK) LR = (spreg)IEA(CIA + 4); - #ifdef WITH_OPTION_MPC860C0 - if (option_mpc860c0 && (BO{0} && BO{2} || !BO{4})) { + if (option_mpc860c0 && (!BO{0} || !BO{2}) && !BO{4}) { /* This branch is predicted as not-taken. If this is a forward branch and it is near the end of a page, we've detected a problematic branch. */ @@ -1556,7 +1551,6 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, program_interrupt(processor, cia, mpc860c0_instruction_program_interrupt); } } - #endif // WITH_OPTION_MPC860C0 if (CURRENT_MODEL_ISSUE > 0) { model_branches(cpu_model(processor), succeed, BO); if (! BO{0}) diff --git a/sim/ppc/psim.c b/sim/ppc/psim.c index 81e54b0..20d843b 100644 --- a/sim/ppc/psim.c +++ b/sim/ppc/psim.c @@ -220,7 +220,7 @@ psim_usage(int verbose) } /* Test "string" for containing a string of digits that form a number -between "min" and "max". The return value is the number of "err". */ +between "min" and "max". The return value is the number or "err". */ static int is_num( char *string, int min, int max, int err) { @@ -316,7 +316,6 @@ psim_options(device *root, break; case 'o': param = find_arg("Missing <dev-spec> option for -o\n", &argp, argv); -#ifdef WITH_OPTION_MPC860C0 if (memcmp(param, "mpc860c0", 8) == 0) { if (param[8] == '\0') @@ -328,7 +327,6 @@ psim_options(device *root, else error("Invalid mpc860c0 option for -o\n"); } else -#endif // WITH_OPTION_MPC860C0 current = tree_parse(current, "%s", param); break; case 'r': @@ -354,9 +352,10 @@ psim_options(device *root, NULL, 0, device_ioctl_set_trace); -#ifdef WITH_OPTION_MPC860C0 - semantic_init(root); -#endif // WITH_OPTION_MPC860C0 + { + void semantic_init(device* root); + semantic_init(root); + } /* return where the options end */ return argv + argp; diff --git a/sim/ppc/sim_calls.c b/sim/ppc/sim_calls.c index bb84539..15df3c5 100644 --- a/sim/ppc/sim_calls.c +++ b/sim/ppc/sim_calls.c @@ -45,6 +45,13 @@ #include "callback.h" #include "remote-sim.h" +/* Define the rate at which the simulator should poll the host + for a quit. */ +#ifndef POLL_QUIT_INTERVAL +#define POLL_QUIT_INTERVAL 0x20 +#endif + +static int poll_quit_count = POLL_QUIT_INTERVAL; /* Structures used by the simulator, for gdb just have static structures */ @@ -324,8 +331,9 @@ sim_do_command (SIM_DESC sd, char *cmd) void sim_io_poll_quit (void) { - if (callbacks->poll_quit != NULL) + if (callbacks->poll_quit != NULL && poll_quit_count-- < 0) { + poll_quit_count = POLL_QUIT_INTERVAL; if (callbacks->poll_quit (callbacks)) psim_stop (simulator); } diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index 1939d18..61de57b 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,3 +1,10 @@ +1999-04-02 Keith Seitz <keiths@cygnus.com> + + * interp.c (POLL_QUIT_INTERVAL): Define. Used to tweak the + frequency at which the poll_quit callback is called. + (sim_resume): Use POLL_QUIT_INTERVAL instead of a + hard-coded value. + Thu Sep 10 02:16:39 1997 J"orn Rennecke <amylaar@cygnus.co.uk> * interp.c (saved_state.asregs): Add new member pad_dummy. @@ -143,16 +150,51 @@ Mon Jun 23 15:49:14 1997 Andrew Cagney <cagney@b1.cygnus.com> FP's around. (set_dr): Ditto. +Mon Jun 23 15:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * interp.c (XD, SET_XD): Delete. + (XF, SET_XF, XD_TO_XF): Define, move around registers in either + FP bank. + + * gencode.c (fmov): Update. + Sun Jun 22 19:33:33 1997 Andrew Cagney <cagney@b1.cygnus.com> * interp.c (set_fpscr1): From J"orn Rennecke <amylaar@cygnus.co.uk>, Fix typo. Ditto for comment. +Tue Aug 12 00:19:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * interp.c (special_address): New function. + (BUSERROR): Call it. Added parameters bits_written and data. + Changed all callers. + * gencode.c (tab): Fixed ocbwb and pref. + +Fri Jun 20 22:03:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * interp.c (do_wdat, do_wdat): Fix bug in register number calculation. + Thu Jun 19 00:28:08 1997 Andrew Cagney <cagney@b1.cygnus.com> * interp.c (sim_create_inferior): Clear registers each time an inferior is started. +Mon Jun 16 14:01:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * interp.c (*FP, FP_OP, FP_CMP, FP_UNARY): Provide a hook for + when a host doesn't support IEEE FP. + (*DP): Provide alternative definition that supports 64bit floating + point. + (target_little_endian): Combine little_endian and little_endian_p. + (saved_state_type): Make fpscr and sr simple integers. + (SET_FPSCR, GET_FPSCR): Use macros to update fpscr register. + (set_fpscr1): New function. Handle swapping when PR / FR bits + changed. Call via *_FPSCR macro. + (SET_SR*, GET_SR*): Use macro's to access the SR bits - avoids + endian problems. + + * gencode.c (tab): Update. + Sun Jun 15 15:22:52 1997 Andrew Cagney <cagney@b1.cygnus.com> * gencode.c (main): Perform basic checks on tab entries. @@ -185,10 +227,22 @@ Fri Jun 13 15:33:53 1997 J"orn Rennecke <amylaar@cygnus.co.uk> * interp.c (init_pointers): Fix little endian test. +Thu Jun 5 12:56:08 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * interp.c (init_pointers): SH4 hardware is always WORDS_BIT_ENDIAN. + * gencode (fmov from/to memory): take endian_mismatch into account + for 32 bit moves too. + Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk> * gencode.c (swap.b): Fix treatment of high word. +Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh/gencode.c, + * interp.c: experimental SH4 support. + DFmode moves are probaly broken for target little endian. + Tue May 20 10:23:28 1997 Andrew Cagney <cagney@b1.cygnus.com> * interp.c (sim_open): Add callback argument. diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index 338b934..be10e59 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -244,12 +244,43 @@ op tab[] = "FP_CMP (n, >, m);", }, + /* sh4 */ + { "", "", "fcnvds <DR_N>,FPUL", "1111nnnn10111101", + "if (! FPSCR_PR || n & 1)", + " saved_state.asregs.exception = SIGILL;", + "else", + "{", + " char buf[4];", + " *(float *)buf = DR(n);", + " FPUL = *(int *)buf;", + "}", + }, + + /* sh4 */ + { "", "", "fcnvsd FPUL,<DR_N>", "1111nnnn10101101", + "if (! FPSCR_PR || n & 1)", + " saved_state.asregs.exception = SIGILL;", + "else", + "{", + " char buf[4];", + " *(int *)buf = FPUL;", + " SET_DR(n, *(float *)buf);", + "}", + }, + /* sh3e */ { "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011", "FP_OP (n, /, m);", "/* FIXME: check for DP and (n & 1) == 0? */", }, + /* sh4 */ + { "", "", "fipr <FV_M>,<FV_N>", "1111nnmm11101101", + "/* FIXME: not implemented */", + "saved_state.asregs.exception = SIGILL;", + "/* FIXME: check for DP and (n & 1) == 0? */", + }, + /* sh3e */ { "", "", "fldi0 <FREG_N>", "1111nnnn10001101", "SET_FR (n, (float)0.0);", @@ -271,6 +302,10 @@ op tab[] = /* sh3e */ { "", "", "float FPUL,<FREG_N>", "1111nnnn00101101", + /* sh4 */ + "if (FPSCR_PR)", + " SET_DR (n, (double)FPUL);", + "else", "{", " SET_FR (n, (float)FPUL);", "}", @@ -284,12 +319,26 @@ op tab[] = /* sh3e */ { "", "", "fmov <FREG_M>,<FREG_N>", "1111nnnnmmmm1100", + /* sh4 */ + "if (FPSCR_SZ) {", + " int ni = XD_TO_XF (n);", + " int mi = XD_TO_XF (m);", + " SET_XF (ni + 0, XF (mi + 0));", + " SET_XF (ni + 1, XF (mi + 1));", + "}", + "else", "{", " SET_FR (n, FR (m));", "}", }, /* sh3e */ { "", "", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010", + /* sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " WDAT (R[n], m);", + "}", + "else", "{", " MA (1);", " WLAT (R[n], FI(m));", @@ -297,6 +346,12 @@ op tab[] = }, /* sh3e */ { "", "", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000", + /* sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " RDAT (R[m], n);", + "}", + "else", "{", " MA (1);", " SET_FI(n, RLAT(R[m]));", @@ -304,6 +359,13 @@ op tab[] = }, /* sh3e */ { "", "", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001", + /* sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " RDAT (R[m], n);", + " R[m] += 8;", + "}", + "else", "{", " MA (1);", " SET_FI (n, RLAT (R[m]));", @@ -312,6 +374,13 @@ op tab[] = }, /* sh3e */ { "", "", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011", + /* sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " R[n] -= 8;", + " WDAT (R[n], m);", + "}", + "else", "{", " MA (1);", " R[n] -= 4;", @@ -320,6 +389,12 @@ op tab[] = }, /* sh3e */ { "", "", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110", + /* sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " RDAT (R[0]+R[m], n);", + "}", + "else", "{", " MA (1);", " SET_FI(n, RLAT(R[0] + R[m]));", @@ -327,12 +402,20 @@ op tab[] = }, /* sh3e */ { "", "", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111", + /* sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " WDAT (R[0]+R[n], m);", + "}", + "else", "{", " MA (1);", " WLAT((R[0]+R[n]), FI(m));", "}", }, + /* sh4: See fmov instructions above for move to/from extended fp registers */ + /* sh3e */ { "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010", "FP_OP(n, *, m);", @@ -343,6 +426,16 @@ op tab[] = "FP_UNARY(n, -);", }, + /* sh4 */ + { "", "", "frchg", "1111101111111101", + "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_FR);", + }, + + /* sh4 */ + { "", "", "fschg", "1111001111111101", + "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_SZ);", + }, + /* sh3e */ { "", "", "fsqrt <FREG_N>", "1111nnnn01101101", "FP_UNARY(n, sqrt);", @@ -355,6 +448,14 @@ op tab[] = /* sh3e */ { "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101", + /* sh4 */ + "if (FPSCR_PR) {", + " if (DR(n) != DR(n)) /* NaN */", + " FPUL = 0x80000000;", + " else", + " FPUL = (int)DR(n);", + "}", + "else", "if (FR(n) != FR(n)) /* NaN */", " FPUL = 0x80000000;", "else", @@ -362,10 +463,6 @@ op tab[] = }, /* sh3e */ - { "", "", "ftst/nan <FREG_N>", "1111nnnn01111101", - "SET_SR_T (isnan (FR(n)));", - }, - /* sh3e */ { "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101", "char buf[4];", "*(int *)buf = FPUL;", @@ -405,6 +502,12 @@ op tab[] = "SPC = R[n];", "/* FIXME: user mode */", }, +#if 0 + { "", "n", "ldc <REG_N>,DBR", "0100nnnn11111010", + "DBR = R[n];", + "/* FIXME: user mode */", + }, +#endif { "", "n", "ldc <REG_N>,R0_BANK", "0100nnnn10001110", "SET_Rn_BANK (0, R[n]);", "/* FIXME: user mode */", @@ -467,6 +570,14 @@ op tab[] = "R[n] += 4;", "/* FIXME: user mode */", }, +#if 0 + { "", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110", + "MA (1);", + "DBR = RLAT (R[n]);", + "R[n] += 4;", + "/* FIXME: user mode */", + }, +#endif { "", "n", "ldc.l @<REG_N>+,R0_BANK", "0100nnnn10000111", "MA (1);", "SET_Rn_BANK (0, RLAT (R[n]));", @@ -740,6 +851,11 @@ op tab[] = "R0 = ((i + 4 + PC) & ~0x3);", }, + { "0", "", "movca.l @R0, <REG_N>", "0000nnnn11000011", + "/* FIXME: Not implemented */", + "saved_state.asregs.exception = SIGILL;", + }, + { "n", "", "movt <REG_N>", "0000nnnn00101001", "R[n] = T;", }, @@ -783,6 +899,21 @@ op tab[] = "R[n] = ~R[m];", }, + { "0", "", "ocbi @<REG_N>", "0000nnnn10010011", + "/* FIXME: Not implemented */", + "saved_state.asregs.exception = SIGILL;", + }, + + { "0", "", "ocbp @<REG_N>", "0000nnnn10100011", + "/* FIXME: Not implemented */", + "saved_state.asregs.exception = SIGILL;", + }, + + { "", "n", "ocbwb @<REG_N>", "0000nnnn10110011", + "RSBAT (R[n]); /* Take exceptions like byte load. */", + "/* FIXME: Cache not implemented */", + }, + { "0", "", "or #<imm>,R0", "11001011i8*1....", "R0 |= i;", }, @@ -920,6 +1051,14 @@ op tab[] = { "n", "", "stc SPC,<REG_N>", "0000nnnn01000010", "R[n] = SPC;", }, +#if 0 + { "n", "", "stc SGR,<REG_N>", "0000nnnn00111010", + "R[n] = SGR;", + }, + { "n", "", "stc DBR,<REG_N>", "0000nnnn11111010", + "R[n] = DBR;", + }, +#endif { "n", "", "stc R0_BANK,<REG_N>", "0000nnnn10000010", "R[n] = Rn_BANK (0);", }, @@ -969,6 +1108,18 @@ op tab[] = "R[n] -= 4;", "WLAT (R[n], SPC);", }, +#if 0 + { "n", "n", "stc.l SGR,@-<REG_N>", "0100nnnn00110010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], SGR);", + }, + { "n", "n", "stc.l DBR,@-<REG_N>", "0100nnnn11110010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], DBR);", + }, +#endif { "n", "", "stc R0_BANK,@-<REG_N>", "0100nnnn10000010", "MA (1);", "R[n] -= 4;", @@ -1153,6 +1304,15 @@ op tab[] = " | ((R[m] << 16) & 0xffff0000));", }, +#if 0 + { "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110", + "divl(0,R[n],R[m]);", + }, + { "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101", + "divl(0,R[n],R[m]);", + }, +#endif + {0, 0}}; /* Tables of things to put into enums for sh-opc.h */ diff --git a/sim/sh/interp.c b/sim/sh/interp.c index bd26967..4d7c5cf 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -56,11 +56,19 @@ #define DEFINE_TABLE #define DISASSEMBLER_TABLE +/* Define the rate at which the simulator should poll the host + for a quit. */ +#define POLL_QUIT_INTERVAL 0x60000 + typedef union { struct { + /* On targets like sparc-sun-solaris, fregs will be aligned on a 64 bit + boundary (because of the d member). To avoid padding between + registers - which whould make the job of sim_fetch_register harder, + we add padding at the start. */ int pad_dummy; int regs[16]; int pc; @@ -84,7 +92,7 @@ typedef union double d[8]; int i[16]; } - fregs; + fregs[2]; int ssr; int spc; @@ -221,9 +229,34 @@ set_sr (new_sr) /* Manipulate FPSCR */ -#define set_fpscr1(x) -#define SET_FPSCR(x) (saved_state.asregs.fpscr = (x)) +#define FPSCR_MASK_FR (1 << 21) +#define FPSCR_MASK_SZ (1 << 20) +#define FPSCR_MASK_PR (1 << 19) + +#define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0) +#define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0) +#define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0) + +static void +set_fpscr1 (x) + int x; +{ + int old = saved_state.asregs.fpscr; + saved_state.asregs.fpscr = (x); + /* swap the floating point register banks */ + if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR) + { + union fregs_u tmpf = saved_state.asregs.fregs[0]; + saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1]; + saved_state.asregs.fregs[1] = tmpf; + } +} + #define GET_FPSCR() (saved_state.asregs.fpscr) +#define SET_FPSCR(x) \ +do { \ + set_fpscr1 (x); \ +} while (0) int @@ -232,6 +265,21 @@ fail () abort (); } +int +special_address (addr, bits_written, data) + void *addr; + int bits_written, data; +{ + if ((unsigned) addr >> 24 == 0xf0 && bits_written == 32 && (data & 1) == 0) + /* This invalidates (if not associative) or might invalidate + (if associative) an instruction cache line. This is used for + trampolines. Since we don't simulate the cache, this is a no-op + as far as the simulator is concerned. */ + return 1; + /* We can't do anything useful with the other stuff, so fail. */ + return 0; +} + /* This function exists solely for the purpose of setting a breakpoint to catch simulated bus errors when running the simulator under GDB. */ @@ -244,8 +292,14 @@ bp_holder () being implemented by ../common/sim_resume.c and the below should make a call to sim_engine_halt */ -#define BUSERROR(addr, mask) \ - if (addr & ~mask) { saved_state.asregs.exception = SIGBUS; bp_holder (); } +#define BUSERROR(addr, mask, bits_written, data) \ + if (addr & ~mask) \ + { \ + if (special_address (addr, bits_written, data)) \ + return; \ + saved_state.asregs.exception = SIGBUS; \ + bp_holder (); \ + } /* Define this to enable register lifetime checking. The compiler generates "add #0,rn" insns to mark registers as invalid, @@ -276,15 +330,98 @@ static host_callback *callback; /* Floating point registers */ -#define FI(n) (saved_state.asregs.fregs.i[(n)]) -#define FR(n) (saved_state.asregs.fregs.f[(n)]) +#define DR(n) (get_dr (n)) +static double +get_dr (n) + int n; +{ + n = (n & ~1); + if (host_little_endian) + { + union + { + int i[2]; + double d; + } dr; + dr.i[1] = saved_state.asregs.fregs[0].i[n + 0]; + dr.i[0] = saved_state.asregs.fregs[0].i[n + 1]; + return dr.d; + } + else + return (saved_state.asregs.fregs[0].d[n >> 1]); +} + +#define SET_DR(n, EXP) set_dr ((n), (EXP)) +static void +set_dr (n, exp) + int n; + double exp; +{ + n = (n & ~1); + if (host_little_endian) + { + union + { + int i[2]; + double d; + } dr; + dr.d = exp; + saved_state.asregs.fregs[0].i[n + 0] = dr.i[1]; + saved_state.asregs.fregs[0].i[n + 1] = dr.i[0]; + } + else + saved_state.asregs.fregs[0].d[n >> 1] = exp; +} + +#define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP)) +#define FI(n) (saved_state.asregs.fregs[0].i[(n)]) -#define SET_FI(n,EXP) (saved_state.asregs.fregs.i[(n)] = (EXP)) -#define SET_FR(n,EXP) (saved_state.asregs.fregs.f[(n)] = (EXP)) +#define FR(n) (saved_state.asregs.fregs[0].f[(n)]) +#define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP)) -#define FP_OP(n, OP, m) (SET_FR(n, (FR(n) OP FR(m)))) -#define FP_UNARY(n, OP) (SET_FR(n, (OP (FR(n))))) -#define FP_CMP(n, OP, m) SET_SR_T(FR(n) OP FR(m)) +#define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e)) +#define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f]) +#define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP)) + + +#define FP_OP(n, OP, m) \ +{ \ + if (FPSCR_PR) \ + { \ + if (((n) & 1) || ((m) & 1)) \ + saved_state.asregs.exception = SIGILL; \ + else \ + SET_DR(n, (DR(n) OP DR(m))); \ + } \ + else \ + SET_FR(n, (FR(n) OP FR(m))); \ +} while (0) + +#define FP_UNARY(n, OP) \ +{ \ + if (FPSCR_PR) \ + { \ + if ((n) & 1) \ + saved_state.asregs.exception = SIGILL; \ + else \ + SET_DR(n, (OP (DR(n)))); \ + } \ + else \ + SET_FR(n, (OP (FR(n)))); \ +} while (0) + +#define FP_CMP(n, OP, m) \ +{ \ + if (FPSCR_PR) \ + { \ + if (((n) & 1) || ((m) & 1)) \ + saved_state.asregs.exception = SIGILL; \ + else \ + SET_SR_T (DR(n) OP DR(m)); \ + } \ + else \ + SET_SR_T (FR(n) OP FR(m)); \ +} while (0) @@ -294,7 +431,7 @@ wlat_little (memory, x, value, maskl) { int v = value; unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, 32, v); p[3] = v >> 24; p[2] = v >> 16; p[1] = v >> 8; @@ -307,7 +444,7 @@ wwat_little (memory, x, value, maskw) { int v = value; unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, 16, v); p[1] = v >> 8; p[0] = v; @@ -320,7 +457,7 @@ wbat_any (memory, x, value, maskb) unsigned char *p = memory + (x & maskb); if (x > 0x5000000) IOMEM (x, 1, value); - BUSERROR(x, maskb); + BUSERROR(x, maskb, 8, value); p[0] = value; } @@ -331,7 +468,7 @@ wlat_big (memory, x, value, maskl) { int v = value; unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, 32, v); p[0] = v >> 24; p[1] = v >> 16; @@ -345,7 +482,7 @@ wwat_big (memory, x, value, maskw) { int v = value; unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, 16, v); p[0] = v >> 8; p[1] = v; @@ -356,7 +493,7 @@ wbat_big (memory, x, value, maskb) unsigned char *memory; { unsigned char *p = memory + (x & maskb); - BUSERROR(x, maskb); + BUSERROR(x, maskb, 8, value); if (x > 0x5000000) IOMEM (x, 1, value); @@ -370,7 +507,7 @@ rlat_little (memory, x, maskl) unsigned char *memory; { unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, -32, -1); return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]; } @@ -380,7 +517,7 @@ rwat_little (memory, x, maskw) unsigned char *memory; { unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, -16, -1); return (p[1] << 8) | p[0]; } @@ -390,7 +527,7 @@ rbat_any (memory, x, maskb) unsigned char *memory; { unsigned char *p = memory + ((x) & maskb); - BUSERROR(x, maskb); + BUSERROR(x, maskb, -8, -1); return p[0]; } @@ -400,7 +537,7 @@ rlat_big (memory, x, maskl) unsigned char *memory; { unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, -32, -1); return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]; } @@ -410,7 +547,7 @@ rwat_big (memory, x, maskw) unsigned char *memory; { unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, -16, -1); return (p[0] << 8) | p[1]; } @@ -426,7 +563,59 @@ rwat_big (memory, x, maskw) #define RSWAT(x) ((short)(RWAT(x))) #define RSBAT(x) (SEXT(RBAT(x))) +#define RDAT(x, n) (do_rdat (memory, (x), (n), (little_endian))) +static int +do_rdat (memory, x, n, little_endian) + char *memory; + int x; + int n; + int little_endian; +{ + int f0; + int f1; + int i = (n & 1); + int j = (n & ~1); + if (little_endian) + { + f0 = rlat_little (memory, x + 0, maskl); + f1 = rlat_little (memory, x + 4, maskl); + } + else + { + f0 = rlat_big (memory, x + 0, maskl); + f1 = rlat_big (memory, x + 4, maskl); + } + saved_state.asregs.fregs[i].i[(j + 0)] = f0; + saved_state.asregs.fregs[i].i[(j + 1)] = f1; + return 0; +} +#define WDAT(x, n) (do_wdat (memory, (x), (n), (little_endian))) +static int +do_wdat (memory, x, n, little_endian) + char *memory; + int x; + int n; + int little_endian; +{ + int f0; + int f1; + int i = (n & 1); + int j = (n & ~1); + f0 = saved_state.asregs.fregs[i].i[(j + 0)]; + f1 = saved_state.asregs.fregs[i].i[(j + 1)]; + if (little_endian) + { + wlat_little (memory, (x + 0), f0, maskl); + wlat_little (memory, (x + 4), f1, maskl); + } + else + { + wlat_big (memory, (x + 0), f0, maskl); + wlat_big (memory, (x + 4), f1, maskl); + } + return 0; +} #define MA(n) do { memstalls += (((pc & 3) != 0) ? (n) : ((n) - 1)); } while (0) @@ -1070,7 +1259,7 @@ sim_resume (sd, step, siggnal) if (--pollcount < 0) { - pollcount = 1000; + pollcount = POLL_QUIT_INTERVAL; if ((*callback->poll_quit) != NULL && (*callback->poll_quit) (callback)) { diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index f863482..953d2a4 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,15 @@ +1999-04-21 Doug Evans <devans@casey.cygnus.com> + + * sim/m32r/nop.cgs: Add missing nop insn. + +Mon Mar 22 13:28:56 1999 Dave Brolley <brolley@cygnus.com> + + * sim/fr30/stb.cgs: Correct for unaligned access. + * sim/fr30/sth.cgs: Correct for unaligned access. + * sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct + for unaligned access. + * sim/fr30/and.cgs: Test unaligned access. + Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com> * lib/sim-defs.exp (sim_run): Print simulator arguments log message. @@ -140,6 +152,11 @@ Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com> * sim/m32r/rte.cgs: Test bbpc,bbpsw. * sim/m32r/trap.cgs: Test bbpc,bbpsw. +Fri Jul 31 17:49:13 1998 Felix Lee <flee@cygnus.com> + + * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of + writeonly. + Fri Jul 24 09:40:34 1998 Doug Evans <devans@canuck.cygnus.com> * Makefile.in (clean,mostlyclean): Change leading spaces to a tab. @@ -148,6 +165,15 @@ Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com> * sim/m32r/hw-trap.ms: New testcase. +Tue Jun 16 15:44:01 1998 Jillian Ye <jillian@cygnus.com> + + * lib/sim-defs.exp: Print out timeout setting info when "-v" is used. + +Thu Jun 11 15:24:53 1998 Doug Evans <devans@canuck.cygnus.com> + + * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options, + which is now a list of options controlling the behaviour of sim_run. + Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com> * sim/m32r/addx.cgs: Add another test. diff --git a/sim/testsuite/d30v-elf/ChangeLog b/sim/testsuite/d30v-elf/ChangeLog index 6d8369f..98e5877 100644 --- a/sim/testsuite/d30v-elf/ChangeLog +++ b/sim/testsuite/d30v-elf/ChangeLog @@ -1,3 +1,7 @@ +1999-03-17 Frank Ch. Eigler <fche@cygnus.com> + + * do-flags.S: Added new test for non-lkr status of MVTSYS. + 1999-01-12 Frank Ch. Eigler <fche@cygnus.com> * do-flags.S: Added one old, one new regression test. diff --git a/sim/testsuite/d30v-elf/do-flags.S b/sim/testsuite/d30v-elf/do-flags.S index 25797e5..f8a15cf 100644 --- a/sim/testsuite/d30v-elf/do-flags.S +++ b/sim/testsuite/d30v-elf/do-flags.S @@ -224,8 +224,22 @@ assert r60, 0x80000000 assert r61, 0x80000000 - - + + # PR 19224 + + add r7,r0,0x80000000 + add r2,r0,r0 || nop + add r1,r0,0x1 || nop + # confirm that these insns do not kill the add in the right container + mvtsys psw,r7 -> add r2,r2,r1 + mvtsys pswh,r7 -> add r2,r2,r1 + mvtsys pswl,r7 -> add r2,r2,r1 + mvtsys f0,r7 -> add r2,r2,r1 + mvtsys mod_s,r7 -> add r2,r2,r1 + + assert r2, 0x5 + + # all okay bra ok diff --git a/sim/testsuite/sim/fr30/and.cgs b/sim/testsuite/sim/fr30/and.cgs index 49db6fd..3148a31 100644 --- a/sim/testsuite/sim/fr30/and.cgs +++ b/sim/testsuite/sim/fr30/and.cgs @@ -42,10 +42,16 @@ and: test_cc 1 0 0 0 test_h_mem 0xaaaa0000,sp - mvi_h_mem 0xffff,sp - set_cc 0x0d ; Set mask opposite of expected + mvr_h_gr sp,r9 + inci_h_gr 4,r9 + mvi_h_mem 0xffffffff,sp + mvi_h_mem 0xffff0000,r9 + inci_h_gr 1,sp ; test unaligned access + set_cc 0x05 ; Set mask opposite of expected and r7,@sp - test_cc 0 0 0 1 - test_h_mem 0xaaaa,sp + test_cc 1 0 0 1 + inci_h_gr -1,sp + test_h_mem 0xaaaaaaaa,sp + test_h_mem 0xffff0000,r9 pass diff --git a/sim/testsuite/sim/fr30/ldub.cgs b/sim/testsuite/sim/fr30/ldub.cgs index 97e00d9..8d42cfa 100644 --- a/sim/testsuite/sim/fr30/ldub.cgs +++ b/sim/testsuite/sim/fr30/ldub.cgs @@ -84,31 +84,31 @@ ldub: add_h_gr r8,r14 set_cc 0x0f ; condition codes should not change - lduh @(r14,0x7f),r7 + ldub @(r14,0x7f),r7 test_cc 1 1 1 1 test_h_gr 0xde,r7 - inci_h_gr 0x3e,r14 + inci_h_gr 0x3f,r14 set_cc 0x07 ; condition codes should not change - lduh @(r14,0x40),r7 + ldub @(r14,0x40),r7 test_cc 0 1 1 1 test_h_gr 0xde,r7 inci_h_gr 0x40,r14 set_cc 0x0b ; condition codes should not change - lduh @(r14,0x0),r7 + ldub @(r14,0x0),r7 test_cc 1 0 1 1 test_h_gr 0xde,r7 inci_h_gr 0x40,r14 set_cc 0x0d ; condition codes should not change - lduh @(r14,-0x40),r7 + ldub @(r14,-0x40),r7 test_cc 1 1 0 1 test_h_gr 0xde,r7 inci_h_gr 0x40,r14 set_cc 0x0e ; condition codes should not change - lduh @(r14,-0x80),r7 + ldub @(r14,-0x80),r7 test_cc 1 1 1 0 test_h_gr 0xde,r7 diff --git a/sim/testsuite/sim/fr30/stb.cgs b/sim/testsuite/sim/fr30/stb.cgs index d9d4fd0..edbf4f2 100644 --- a/sim/testsuite/sim/fr30/stb.cgs +++ b/sim/testsuite/sim/fr30/stb.cgs @@ -55,13 +55,13 @@ stb: mvi_h_gr 0xaaaaaafe,r8 mvi_h_mem 0xdeadbeef,sp mvr_h_gr sp,r14 - inci_h_gr -127,r14 + inci_h_gr -128,r14 ; must be aligned + mvi_h_mem 0xdeadbeef,r14 mvr_h_gr r14,r2 + inci_h_gr -128,r14 ; must be aligned mvi_h_mem 0xdeadbeef,r14 - inci_h_gr -128,r14 mvr_h_gr r14,r3 - mvi_h_mem 0xdeadbeef,r14 - inci_h_gr 128,r14 + inci_h_gr 129,r14 set_cc 0x0b ; Condition codes should not change stb r8,@(r14,127) @@ -72,13 +72,13 @@ stb: set_cc 0x0a ; Condition codes should not change stb r8,@(r14,0) test_cc 1 0 1 0 - test_h_mem 0xfeadbeef,r2 + test_h_mem 0xdefebeef,r2 test_h_gr 0xaaaaaafe,r8 set_cc 0x09 ; Condition codes should not change stb r8,@(r14,-128) test_cc 1 0 0 1 - test_h_mem 0xfeadbeef,r3 + test_h_mem 0xdefebeef,r3 test_h_gr 0xaaaaaafe,r8 pass diff --git a/sim/testsuite/sim/fr30/sth.cgs b/sim/testsuite/sim/fr30/sth.cgs index 64c83e6..8c4a115 100644 --- a/sim/testsuite/sim/fr30/sth.cgs +++ b/sim/testsuite/sim/fr30/sth.cgs @@ -52,33 +52,33 @@ sth: ; Test sth $Ri,@(R14,$disp9) mvr_h_gr r9,sp ; Restore stack pointer - mvi_h_gr 0xaaaabeef,r8 + mvi_h_gr 0xaaaaabcd,r8 mvi_h_mem 0xdeadbeef,sp mvr_h_gr sp,r14 - inci_h_gr -254,r14 + inci_h_gr -256,r14 ; must be aligned mvr_h_gr r14,r2 mvi_h_mem 0xdeadbeef,r14 inci_h_gr -256,r14 mvr_h_gr r14,r3 mvi_h_mem 0xdeadbeef,r14 - inci_h_gr 256,r14 + inci_h_gr 258,r14 set_cc 0x0b ; Condition codes should not change sth r8,@(r14,254) test_cc 1 0 1 1 - test_h_mem 0xbeefbeef,r1 - test_h_gr 0xaaaabeef,r8 + test_h_mem 0xabcdbeef,r1 + test_h_gr 0xaaaaabcd,r8 set_cc 0x0a ; Condition codes should not change sth r8,@(r14,0) test_cc 1 0 1 0 - test_h_mem 0xbeefbeef,r2 - test_h_gr 0xaaaabeef,r8 + test_h_mem 0xdeadabcd,r2 + test_h_gr 0xaaaaabcd,r8 set_cc 0x09 ; Condition codes should not change sth r8,@(r14,-256) test_cc 1 0 0 1 - test_h_mem 0xbeefbeef,r3 - test_h_gr 0xaaaabeef,r8 + test_h_mem 0xdeadabcd,r3 + test_h_gr 0xaaaaabcd,r8 pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs index 05b44bc..e06d656 100644 --- a/sim/testsuite/sim/m32r/nop.cgs +++ b/sim/testsuite/sim/m32r/nop.cgs @@ -7,4 +7,5 @@ .global nop nop: + nop pass |