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-rw-r--r--sim/mips/ChangeLog16
-rw-r--r--sim/mips/interp.c214
-rw-r--r--sim/mips/mips.igen1012
-rw-r--r--sim/mips/sim-main.h8
-rw-r--r--sim/mips/sky-pke.c9
-rw-r--r--sim/mips/sky-pke.h3
6 files changed, 349 insertions, 913 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index f820155..1804d5c 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,19 @@
+start-sanitize-sky
+Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (*): Adapt code to merged VU device & state structs.
+ (decode_coproc): Execute COP2 each macroinstruction without
+ pipelining, by stepping VU to completion state. Adapted to
+ read_vu_*_reg style of register access.
+
+ * mips.igen ([SL]QC2): Removed these COP2 instructions.
+
+ * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
+
+ * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
+
+end-sanitize-sky
+
Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (SIM_OBJS): Add sim-main.o.
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 1ab0f11..dac3a60 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -44,6 +44,7 @@ code on the hardware.
#include "sky-vpe.h"
#include "sky-libvpe.h"
#include "sky-pke.h"
+#include "idecode.h"
#endif
/* end-sanitize-sky */
@@ -671,31 +672,31 @@ sim_store_register (sd,rn,memory,length)
if( rn < NUM_VU_REGS )
{
if (rn < NUM_VU_INTEGER_REGS)
- return write_vu_int_reg (&(vu0_device.state->regs), rn, memory);
+ return write_vu_int_reg (&(vu0_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
- return write_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn&3,
+ return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
- return write_vu_special_reg (vu0_device.state, VU_REG_CIA,
+ return write_vu_special_reg (&vu0_device, VU_REG_CIA,
memory);
case 1:
- return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
+ return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
memory);
case 2: /* VU0 has no P register */
return 4;
case 3:
- return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
+ return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
memory);
case 4:
- return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
+ return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
memory);
default:
- return write_vu_acc_reg (&(vu0_device.state->regs),
+ return write_vu_acc_reg (&(vu0_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@@ -706,32 +707,32 @@ sim_store_register (sd,rn,memory,length)
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
- return write_vu_int_reg (&(vu1_device.state->regs), rn, memory);
+ return write_vu_int_reg (&(vu1_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
- return write_vu_vec_reg (&(vu1_device.state->regs),
+ return write_vu_vec_reg (&(vu1_device.regs),
rn >> 2, rn & 3, memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
- return write_vu_special_reg (vu1_device.state, VU_REG_CIA,
+ return write_vu_special_reg (&vu1_device, VU_REG_CIA,
memory);
case 1:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MR,
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
memory);
case 2:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MP,
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
memory);
case 3:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MI,
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
memory);
case 4:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MQ,
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
memory);
default:
- return write_vu_acc_reg (&(vu1_device.state->regs),
+ return write_vu_acc_reg (&(vu1_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@@ -846,31 +847,31 @@ sim_fetch_register (sd,rn,memory,length)
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
- return read_vu_int_reg (&(vu0_device.state->regs), rn, memory);
+ return read_vu_int_reg (&(vu0_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
- return read_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn & 3,
+ return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
- return read_vu_special_reg(vu0_device.state, VU_REG_CIA, memory);
+ return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
case 1:
- return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
+ return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
memory);
case 2: /* VU0 has no P register */
*((int *) memory) = 0;
return 4;
case 3:
- return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
+ return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
memory);
case 4:
- return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
+ return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
memory);
default:
- return read_vu_acc_reg (&(vu0_device.state->regs),
+ return read_vu_acc_reg (&(vu0_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@@ -881,31 +882,31 @@ sim_fetch_register (sd,rn,memory,length)
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
- return read_vu_int_reg (&(vu1_device.state->regs), rn, memory);
+ return read_vu_int_reg (&(vu1_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
- return read_vu_vec_reg (&(vu1_device.state->regs),
+ return read_vu_vec_reg (&(vu1_device.regs),
rn >> 2, rn & 3, memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
- return read_vu_special_reg(vu1_device.state, VU_REG_CIA, memory);
+ return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
case 1:
- return read_vu_misc_reg (&(vu1_device.state->regs),
+ return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MR, memory);
case 2:
- return read_vu_misc_reg (&(vu1_device.state->regs),
+ return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MP, memory);
case 3:
- return read_vu_misc_reg (&(vu1_device.state->regs),
+ return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MI, memory);
case 4:
- return read_vu_misc_reg (&(vu1_device.state->regs),
+ return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MQ, memory);
default:
- return read_vu_acc_reg (&(vu1_device.state->regs),
+ return read_vu_acc_reg (&(vu1_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@@ -3213,7 +3214,7 @@ decode_coproc (SIM_DESC sd,
}
break;
- case 2: /* undefined co-processor */
+ case 2: /* co-processor 2 */
{
int handle = 0;
@@ -3223,12 +3224,14 @@ decode_coproc (SIM_DESC sd,
int i_25_21 = (instruction >> 21) & 0x1f;
int i_20_16 = (instruction >> 16) & 0x1f;
+ int i_20_6 = (instruction >> 6) & 0x7fff;
int i_15_11 = (instruction >> 11) & 0x1f;
int i_15_0 = instruction & 0xffff;
int i_10_1 = (instruction >> 1) & 0x3ff;
+ int i_10_0 = instruction & 0x7ff;
+ int i_10_6 = (instruction >> 6) & 0x1f;
int i_5_0 = instruction & 0x03f;
int interlock = instruction & 0x01;
- int co = (instruction >> 25) & 0x01;
/* setup for semantic.c-like actions below */
typedef unsigned_4 instruction_word;
int CIA = cia;
@@ -3272,101 +3275,134 @@ decode_coproc (SIM_DESC sd,
{
int rt = i_20_16;
int id = i_15_11;
- address_word vu_cr_addr; /* VU control register address */
- unsigned_4 data;
/* interlock checking */
- if(vu0_busy_in_macro_mode()) /* busy in macro mode */
- {
- /* interlock bit invalid here */
- if(interlock)
- ; /* XXX: warning */
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy() && interlock)
+ vu0_issue(sd);
- /* always check data hazard */
- while(vu0_macro_hazard_check(id))
- vu0_issue(sd);
- }
- else if(vu0_busy_in_micro_mode() && interlock)
+ /* perform VU register address */
+ if(i_25_21 == 0x01) /* QMFC2 */
{
- while(vu0_busy_in_micro_mode())
- vu0_issue(sd);
+ unsigned_16 xyzw;
+ /* one word at a time, argh! */
+ read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
+ read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
+ read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
+ read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
+ xyzw = T2H_16(xyzw);
+ memcpy(& GPR[rt], & xyzw, sizeof(xyzw));
}
-
- /* compute VU register address */
- if(i_25_21 == 0x01) /* QMFC2 */
- vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
else /* CFC2 */
- vu_cr_addr = VU0_MST + (id * 16);
-
- /* read or write word */
- data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
- GPR[rt] = EXTEND64(data);
+ {
+ unsigned_4 data;
+ /* enum + int calculation, argh! */
+ id = VU_REG_MST + 16 * id;
+ read_vu_misc_reg(&(vu0_device.regs), id, & data);
+ GPR[rt] = EXTEND32(T2H_4(data));
+ }
}
else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
(i_25_21 == 0x05)) /* QMTC2 */
{
int rt = i_20_16;
int id = i_15_11;
- address_word vu_cr_addr; /* VU control register address */
- unsigned_4 data;
/* interlock checking */
- if(vu0_busy_in_macro_mode()) /* busy in macro mode */
+ /* POLICY: never busy in macro mode */
+ if(vu0_busy() && interlock)
{
- /* interlock bit invalid here */
- if(interlock)
- ; /* XXX: warning */
-
- /* always check data hazard */
- while(vu0_macro_hazard_check(id))
+ while(! vu0_micro_interlock_released())
vu0_issue(sd);
}
- else if(vu0_busy_in_micro_mode())
+
+ /* perform VU register address */
+ if(i_25_21 == 0x05) /* QMTC2 */
{
- if(interlock)
- {
- while(! vu0_micro_interlock_released())
- vu0_issue(sd);
- }
+ unsigned_16 xyzw;
+ memcpy(& xyzw, & GPR[rt], sizeof(xyzw));
+ xyzw = H2T_16(xyzw);
+ /* one word at a time, argh! */
+ write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
+ write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
+ write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
+ write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
}
-
- /* compute VU register address */
- if(i_25_21 == 0x05) /* QMTC2 */
- vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
else /* CTC2 */
- vu_cr_addr = VU0_MST + (id * 16);
+ {
+ unsigned_4 data = H2T_4(GPR[rt]);
+ /* enum + int calculation, argh! */
+ id = VU_REG_MST + 16 * id;
+ write_vu_misc_reg(&(vu0_device.regs), id, & data);
+ }
+ }
+ else if(i_10_0 == 0x3bf) /* VWAITQ */
+ {
+ while(vu0_q_busy())
+ vu0_issue(sd);
+ }
+ else if(i_5_0 == 0x38) /* VCALLMS */
+ {
+ unsigned_4 data = H2T_2(i_20_6);
+
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ /* write to reserved CIA register to get VU0 moving */
+ write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
+ }
+ else if(i_5_0 == 0x39) /* VCALLMSR */
+ {
+ unsigned_4 data;
+
+ while(vu0_busy())
+ vu0_issue(sd);
- data = GPR[rt];
- sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
+ read_vu_misc_reg(&(vu0_device.regs), VU_REG_CMSAR0, & data);
+ /* write to reserved CIA register to get VU0 moving */
+ write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
}
- else if( 0 /* XXX: ... upper ... */)
+ /* handle all remaining UPPER VU instructions in one block */
+ else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
+ (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
{
unsigned_4 vu_upper, vu_lower;
vu_upper =
- 0x00000000 | /* bits 31 .. 25 */
- instruction & 0x01ffffff; /* bits 24 .. 0 */
+ 0x40000000 | /* bits 31 .. 25 */
+ (instruction & 0x01ffffff); /* bits 24 .. 0 */
vu_lower = 0x8000033c; /* NOP */
- while(vu0_busy_in_micro_mode())
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy())
vu0_issue(sd);
vu0_macro_issue(vu_upper, vu_lower);
+
+ /* POLICY: wait for completion of macro-instruction */
+ while(vu0_busy())
+ vu0_issue(sd);
}
- else if( 0 /* XXX: ... lower ... */)
- {
+ /* handle all remaining LOWER VU instructions in one block */
+ else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
+ (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
+ { /* N.B.: VWAITQ already covered by prior case */
unsigned_4 vu_upper, vu_lower;
- vu_upper = 0x000002ff; /* NOP */
+ vu_upper = 0x400002ff; /* END/NOP */
vu_lower =
0x10000000 | /* bits 31 .. 25 */
- instruction & 0x01ffffff; /* bits 24 .. 0 */
+ (instruction & 0x01ffffff); /* bits 24 .. 0 */
- while(vu0_busy_in_micro_mode())
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy())
vu0_issue(sd);
vu0_macro_issue(vu_upper, vu_lower);
+
+ /* POLICY: wait for completion of macro-instruction */
+ while(vu0_busy())
+ vu0_issue(sd);
}
- /* XXX */
- /* ... other COP2 instructions ... */
+ /* ... no other COP2 instructions ... */
else
{
SignalException(ReservedInstruction, instruction);
@@ -3381,7 +3417,7 @@ decode_coproc (SIM_DESC sd,
if(! handle)
{
- sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
+ sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
instruction,pr_addr(cia));
}
}
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 60a37e6..4a1103c 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -127,7 +127,7 @@
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
-"add r<RT>, r<RS>, <IMMEDIATE>"
+"addu r<RT>, r<RS>, <IMMEDIATE>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
// start-sanitize-vr4320
@@ -150,6 +150,7 @@
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
+"addu r<RD>, r<RS>, r<RT>"
*mipsI,mipsII,mipsIII,mipsIV:
*vr5000:
// start-sanitize-vr4320
@@ -1389,25 +1390,28 @@
}
-:function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
+:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
{
- address_word vaddr = offset + gpr_base;
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
address_word paddr;
int uncached;
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
- byte = ((vaddr & mask) ^ bigend);
- GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
- }
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ if ((vaddr & access) != 0)
+ SignalExceptionAddressLoad ();
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ return (memval >> (8 * byte));
}
+
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
"lb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -1426,34 +1430,7 @@
*tx19:
// end-sanitize-tx19
{
- do_load_byte (SD_, GPR[BASE], RT, OFFSET);
-#if 0
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
- }
- }
- }
-#endif
+ GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1475,31 +1452,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
}
@@ -1521,27 +1474,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = memval;
- }
- }
- }
+ GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1562,62 +1495,10 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
- }
- }
- }
+ COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
-// start-sanitize-sky
-110110,5.BASE,5.RT,16.OFFSET:NORMAL:64::LQC2
-"lqc2 r<RT>, <OFFSET>(r<BASE>)"
-*r5900:
-{
-#ifdef TARGET_SKY
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 0x0f) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned128 qw = U16_8(memval, memval1); /* XXX: check order */
- /* XXX: block on VU0 pipeline if necessary */
- LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
- COP_LQ(((instruction >> 26) & 0x3),destreg,qw);;
- }
- }
- }
-#endif /* TARGET_SKY */
-}
-// end-sanitize-sky
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
@@ -1638,32 +1519,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
- GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
- }
- }
- }
+ GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1685,39 +1541,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
- {
- unsigned64 srcmask;
- if (byte == 0)
- srcmask = 0;
- else
- srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
- GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
- }
- }
- }
- }
+ GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -1739,34 +1563,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
- }
- }
- }
+ GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -1788,34 +1585,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
}
@@ -1953,34 +1723,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
- }
- }
- }
+ GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -2002,34 +1745,44 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
+ /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
+ (long) vaddr, byte, (long) paddr, (long) memval); */
+ if ((byte & ~access) == 0)
+ {
+ int bits = 8 * (access - byte);
+ unsigned_word screen = LSMASK (bits - 1, 0);
+ rt &= screen;
+ rt |= ((memval << bits) & ~screen);
+ }
+ else
+ {
+ unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
+ rt &= screen;
+ rt |= ((memval >> (8 * (mask - byte))) & ~screen);
+ }
+ return rt;
}
@@ -2051,36 +1804,38 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+ GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
+}
+
+
+:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr = paddr & ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
+ LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+ /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
+ (long) paddr, byte, (long) paddr, (long) memval); */
{
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval >>= 32;
- }
- GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
- }
+ unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
+ rt &= ~screen;
+ rt |= (memval >> (8 * byte)) & screen;
}
+ return rt;
}
@@ -2102,43 +1857,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (BigEndianMem)
- paddr &= ~mask;
- LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval >>= 32;
- }
- {
- unsigned64 srcmask;
- if (byte == 0)
- srcmask = 0;
- else
- srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
- GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
- }
- GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
- }
- }
- }
+ GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
@@ -2160,34 +1879,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
}
@@ -2511,6 +2203,28 @@
}
}
+:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ if ((vaddr & access) != 0)
+ SignalExceptionAddressStore ();
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = (word << (8 * byte));
+ StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
+}
+
+
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
"sb r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -2529,33 +2243,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 0;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2674,29 +2362,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = op2;
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2719,68 +2385,8 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-}
-
-
-// start-sanitize-sky
-111010,5.BASE,5.RT,16.OFFSET:NORMAL:64::SQC2
-"sqc2 r<RT>, <OFFSET>(r<BASE>)"
-*r5900:
-{
-#ifdef TARGET_SKY
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 0x0f) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned128 qw;
- unsigned64 memval0 = 0;
- unsigned64 memval1 = 0;
- qw = COP_SQ(((instruction >> 26) & 0x3),destreg);
- memval0 = *A8_16(& qw, 0);
- memval1 = *A8_16(& qw, 1);
- {
- StoreMemory(uncached,AccessLength_WORD,memval0,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
-#endif /* TARGET_SKY */
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
-// end-sanitize-sky
-
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
@@ -2801,32 +2407,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = (op2 >> (8 * (7 - byte)));
- StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2848,21 +2429,7 @@
*tx19:
// end-sanitize-tx19
{
- address_word paddr;
- int uncached;
- unsigned64 memval;
- unsigned64 mask = 7;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
- AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- if (BigEndianMem)
- paddr &= ~mask;
- byte = ((vaddr & mask) ^ bigend);
- memval = (GPR[RT] << (byte * 8));
- StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
+ do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -2884,36 +2451,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 1) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 1;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- byte = ((vaddr & mask) ^ (bigend << shift));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -3197,48 +2735,22 @@
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
"sw r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
-*vr5000:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+*r3900:
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
+*vr5000:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) op2 << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -3257,33 +2769,33 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- int destreg = ((instruction >> 16) & 0x0000001F);
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
+}
+
+
+
+:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem == 0)
+ paddr = paddr & ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ if ((byte & ~access) == 0)
+ memval = (rt >> (8 * (access - byte)));
+ else
+ memval = (rt << (8 * (mask - byte)));
+ StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
}
@@ -3305,38 +2817,31 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- byte = ((vaddr & mask) ^ bigend);
- if (!BigEndianMem)
- paddr &= ~mask;
- memval = (op2 >> (8 * (3 - byte)));
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
- memval <<= 32;
- }
- StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
+:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
+{
+ address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? -1 : 0);
+ address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
+ unsigned int byte;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ address_word vaddr;
+
+ vaddr = base + offset;
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = (paddr ^ (reverseendian & mask));
+ if (BigEndianMem != 0)
+ paddr &= ~access;
+ byte = ((vaddr & mask) ^ (bigendiancpu & mask));
+ memval = (rt << (byte * 8));
+ StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+}
+
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
"swr r<RT>, <OFFSET>(r<BASE>)"
*mipsI,mipsII,mipsIII,mipsIV:
@@ -3355,23 +2860,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned64 memval = 0;
- unsigned64 mask = 3;
- unsigned int reverse = (ReverseEndian ? mask : 0);
- unsigned int bigend = (BigEndianCPU ? mask : 0);
- int byte;
- address_word paddr;
- int uncached;
- address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
- AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
- if (BigEndianMem)
- paddr &= ~mask;
- byte = ((vaddr & mask) ^ bigend);
- memval = (GPR[RT] << (byte * 8));
- if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
- memval <<= 32;
- StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
+ do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
@@ -4448,18 +3937,7 @@
*tx19:
// end-sanitize-tx19
{
- address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- unsigned64 memval;
- AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
- LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
- }
+ COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -4474,27 +3952,7 @@
*vr5400:
// end-sanitize-vr5400
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- COP_LD(1,destreg,memval);;
- }
- }
- }
+ COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
}
@@ -4517,34 +3975,7 @@
*tx19:
// end-sanitize-tx19
{
- unsigned32 instruction = instruction_0;
- signed_word offset = EXTEND16 (OFFSET);
- int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
- signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((uword64)op1 + offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte UNUSED;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
}
@@ -4559,34 +3990,7 @@
*vr5400:
// end-sanitize-vr5400
{
- unsigned32 instruction = instruction_0;
- int destreg = ((instruction >> 6) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
- }
- }
- }
+ COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
}
@@ -5162,22 +4566,12 @@
*tx19:
// end-sanitize-tx19
{
- address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- address_word paddr;
- unsigned64 memval;
- AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
- memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
}
-010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
+"ldxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*vr5000:
// start-sanitize-vr4320
@@ -5187,29 +4581,7 @@
*vr5400:
// end-sanitize-vr5400
{
- unsigned32 instruction = instruction_0;
- int fs = ((instruction >> 11) & 0x0000001F);
- signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
- signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
- {
- address_word vaddr = ((unsigned64)op1 + op2);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- SignalExceptionAddressStore();
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = (unsigned64)COP_SD(1,fs);
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
}
@@ -5586,10 +4958,11 @@
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
*mipsI,mipsII,mipsIII,mipsIV:
-*vr5000:
+*r3900:
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
+*vr5000:
// start-sanitize-vr5400
*vr5400:
// end-sanitize-vr5400
@@ -5672,6 +5045,7 @@
// start-sanitize-r5900
:include::r5900:r5900.igen
// end-sanitize-r5900
+:include:::tx.igen
// start-sanitize-cygnus-never
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index ded67cc..b710386 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -779,12 +779,16 @@ cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
/* start-sanitize-sky */
-void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned128 memword));
-unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
+#ifdef TARGET_SKY
+void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
+ int coproc_num, int coproc_reg, unsigned128 memword));
+unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
+ int coproc_num, int coproc_reg));
#define COP_LQ(coproc_num,coproc_reg,memword) \
cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
#define COP_SQ(coproc_num,coproc_reg) \
cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
+#endif /* TARGET_SKY */
/* end-sanitize-sky */
void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
diff --git a/sim/mips/sky-pke.c b/sim/mips/sky-pke.c
index ce775bd..ce5c478 100644
--- a/sim/mips/sky-pke.c
+++ b/sim/mips/sky-pke.c
@@ -1089,16 +1089,19 @@ pke_check_stall(struct pke_device* me, enum pke_check_target what)
}
else if(what == chk_path1) /* VU -> GPUIF */
{
+ ASSERT(me->pke_number == 1);
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 1)
any_stall = 1;
}
else if(what == chk_path2) /* PKE -> GPUIF */
{
+ ASSERT(me->pke_number == 1);
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 2)
any_stall = 1;
}
else if(what == chk_path3) /* DMA -> GPUIF */
{
+ ASSERT(me->pke_number == 1);
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 3)
any_stall = 1;
}
@@ -1243,12 +1246,12 @@ pke_code_mskpath3(struct pke_device* me, unsigned_4 pkecode)
/* set appropriate bit */
if(BIT_MASK_GET(imm, PKE_REG_MSKPATH3_B, PKE_REG_MSKPATH3_E) != 0)
- gif_mode = GIF_REG_MODE_M3R_MASK;
+ gif_mode = GIF_REG_STAT_M3P;
else
gif_mode = 0;
- /* write register; patrickm code will look at M3R bit only */
- PKE_MEM_WRITE(me, GIF_REG_MODE, & gif_mode, 4);
+ /* write register to "read-only" register; gpuif code will look at M3P bit only */
+ PKE_MEM_WRITE(me, GIF_REG_VIF_M3P, & gif_mode, 4);
/* done */
pke_pc_advance(me, 1);
diff --git a/sim/mips/sky-pke.h b/sim/mips/sky-pke.h
index 4816ce6..2e44ed4 100644
--- a/sim/mips/sky-pke.h
+++ b/sim/mips/sky-pke.h
@@ -45,6 +45,9 @@ typedef unsigned_4 quadword[4];
#define VU1_MEM0_SRCADDR_START 0x21008000
#define VU1_MEM1_SRCADDR_START 0x2100C000
+#define VU0_CIA (VU0_REGISTER_WINDOW_START + VU_REG_CIA)
+#define VU1_CIA (VU1_REGISTER_WINDOW_START + VU_REG_CIA)
+
/* GPUIF STAT register */
#define GPUIF_REG_STAT_APATH_E 11
#define GPUIF_REG_STAT_APATH_B 10
generated by cgit v1.1 at 2024-12-20 12:12:30 +0000