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-rw-r--r--sim/mn10300/ChangeLog25
-rw-r--r--sim/mn10300/interp.c108
-rw-r--r--sim/mn10300/simops.c502
3 files changed, 295 insertions, 340 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index ccfc55e..4ac5038 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,28 @@
+Tue May 20 17:51:30 1997 Jeffrey A Law (law@cygnus.com)
+
+ * interp.c: Replace all references to load_mem and store_mem
+ with references to load_byte, load_half, load_3_byte, load_word
+ and store_byte, store_half, store_3_byte, store_word.
+ (INLINE): Delete definition.
+ (load_mem_big): Likewise.
+ (max_mem): Make it global.
+ (dispatch): Make this function inline.
+ (load_mem, store_mem): Delete functions.
+ * mn10300_sim.h (INLINE): Define.
+ (RLW): Delete unused definition.
+ (load_mem, store_mem): Delete declarations.
+ (load_mem_big): New definition.
+ (load_byte, load_half, load_3_byte, load_word): New functions.
+ (store_byte, store_half, store_3_byte, store_word): New functions.
+ * simops.c: Replace all references to load_mem and store_mem
+ with references to load_byte, load_half, load_3_byte, load_word
+ and store_byte, store_half, store_3_byte, store_word.
+
+Tue May 20 10:21:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Add callback to arguments.
+ (sim_set_callbacks): Delete SIM_DESC argument.
+
Mon May 19 13:54:22 1997 Jeffrey A Law (law@cygnus.com)
* interp.c (dispatch): Make this an inline function.
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index affa4ab..7f29f76 100644
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -4,14 +4,6 @@
#include "mn10300_sim.h"
-#ifndef INLINE
-#ifdef __GNUC__
-#define INLINE inline
-#else
-#define INLINE
-#endif
-#endif
-
host_callback *mn10300_callback;
int mn10300_debug;
static SIM_OPEN_KIND sim_kind;
@@ -234,62 +226,6 @@ put_word (addr, data)
a[3] = (data >> 24) & 0xff;
}
-uint32
-load_mem (addr, len)
- SIM_ADDR addr;
- int len;
-{
- uint8 *p = addr + State.mem;
-
- if (addr > max_mem)
- abort ();
-
- switch (len)
- {
- case 1:
- return p[0];
- case 2:
- return p[1] << 8 | p[0];
- case 3:
- return p[2] << 16 | p[1] << 8 | p[0];
- case 4:
- return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
- default:
- abort ();
- }
-}
-
-void
-store_mem (addr, len, data)
- SIM_ADDR addr;
- int len;
- uint32 data;
-{
- uint8 *p = addr + State.mem;
-
- if (addr > max_mem)
- abort ();
-
- switch (len)
- {
- case 1:
- p[0] = data;
- return;
- case 2:
- p[0] = data;
- p[1] = data >> 8;
- return;
- case 4:
- p[0] = data;
- p[1] = data >> 8;
- p[2] = data >> 16;
- p[3] = data >> 24;
- return;
- default:
- abort ();
- }
-}
-
void
sim_size (power)
int power;
@@ -326,7 +262,7 @@ sim_write (sd, addr, buffer, size)
init_system ();
for (i = 0; i < size; i++)
- store_mem (addr + i, 1, buffer[i]);
+ store_byte (addr + i, buffer[i]);
return size;
}
@@ -348,8 +284,9 @@ compare_simops (arg1, arg2)
}
SIM_DESC
-sim_open (kind,argv)
+sim_open (kind,cb,argv)
SIM_OPEN_KIND kind;
+ host_callback *cb;
char **argv;
{
struct simops *s;
@@ -357,6 +294,8 @@ sim_open (kind,argv)
char **p;
int i;
+ mn10300_callback = cb;
+
/* Sort the opcode array from smallest opcode to largest.
This will generally improve simulator performance as the smaller
opcodes are generally preferred to the larger opcodes. */
@@ -749,9 +688,9 @@ sim_resume (sd, step, siggnal)
case 0x3a:
case 0x3b:
case 0xcc:
- insn = load_mem (PC, 1);
+ insn = load_byte (PC);
insn <<= 16;
- insn |= load_mem (PC + 1, 2);
+ insn |= load_half (PC + 1);
extension = 0;
dispatch (insn, extension, 3);
break;
@@ -777,7 +716,7 @@ sim_resume (sd, step, siggnal)
{
insn = inst;
insn <<= 16;
- insn |= load_mem (PC + 2, 2);
+ insn |= load_half (PC + 2);
extension = 0;
}
dispatch (insn, extension, 4);
@@ -785,18 +724,18 @@ sim_resume (sd, step, siggnal)
/* Five byte insns. */
case 0xcd:
- insn = load_mem (PC, 1);
+ insn = load_byte (PC);
insn <<= 24;
- insn |= (load_mem (PC + 1, 2) << 8);
- insn |= load_mem (PC + 3, 1);
- extension = load_mem (PC + 4, 1);
+ insn |= (load_half (PC + 1) << 8);
+ insn |= load_byte (PC + 3);
+ extension = load_byte (PC + 4);
dispatch (insn, extension, 5);
break;
case 0xdc:
- insn = load_mem (PC, 1);
+ insn = load_byte (PC);
insn <<= 24;
- extension = load_mem (PC + 1, 4);
+ extension = load_word (PC + 1);
insn |= (extension & 0xffffff00) >> 8;
extension &= 0xff;
dispatch (insn, extension, 5);
@@ -806,29 +745,29 @@ sim_resume (sd, step, siggnal)
case 0xfc:
case 0xfd:
insn = (inst << 16);
- extension = load_mem (PC + 2, 4);
+ extension = load_word (PC + 2);
insn |= ((extension & 0xffff0000) >> 16);
extension &= 0xffff;
dispatch (insn, extension, 6);
break;
case 0xdd:
- insn = load_mem (PC, 1) << 24;
- extension = load_mem (PC + 1, 4);
+ insn = load_byte (PC) << 24;
+ extension = load_word (PC + 1);
insn |= ((extension >> 8) & 0xffffff);
extension = (extension & 0xff) << 16;
- extension |= load_mem (PC + 5, 1) << 8;
- extension |= load_mem (PC + 6, 1);
+ extension |= load_byte (PC + 5) << 8;
+ extension |= load_byte (PC + 6);
dispatch (insn, extension, 7);
break;
case 0xfe:
insn = inst << 16;
- extension = load_mem (PC + 2, 4);
+ extension = load_word (PC + 2);
insn |= ((extension >> 16) & 0xffff);
extension <<= 8;
extension &= 0xffff00;
- extension |= load_mem (PC + 6, 1);
+ extension |= load_byte (PC + 6);
dispatch (insn, extension, 7);
break;
@@ -898,8 +837,7 @@ sim_kill (sd)
}
void
-sim_set_callbacks (sd, p)
- SIM_DESC sd;
+sim_set_callbacks (p)
host_callback *p;
{
mn10300_callback = p;
@@ -949,7 +887,7 @@ sim_read (sd, addr, buffer, size)
{
int i;
for (i = 0; i < size; i++)
- buffer[i] = load_mem (addr + i, 1);
+ buffer[i] = load_byte (addr + i);
return size;
}
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index dc1786b..8f86609 100644
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -110,7 +110,7 @@ void OP_70 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1 (insn)]
- = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
+ = load_word (State.regs[REG_A0 + REG0 (insn)]);
}
/* mov (d8,am), dn */
@@ -118,8 +118,7 @@ void OP_F80000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_8 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 4);
+ = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)));
}
/* mov (d16,am), dn */
@@ -127,8 +126,8 @@ void OP_FA000000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 4);
+ = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT16 (insn & 0xffff)));
}
/* mov (d32,am), dn */
@@ -136,8 +135,8 @@ void OP_FC000000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 4);
+ = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension));
}
/* mov (d8,sp), dn */
@@ -145,7 +144,7 @@ void OP_5800 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_8 (insn)]
- = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
+ = load_word (State.regs[REG_SP] + (insn & 0xff));
}
/* mov (d16,sp), dn */
@@ -153,7 +152,7 @@ void OP_FAB40000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
+ = load_word (State.regs[REG_SP] + (insn & 0xffff));
}
/* mov (d32,sp), dn */
@@ -161,7 +160,7 @@ void OP_FCB40000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
+ = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}
/* mov (di,am), dn */
@@ -169,15 +168,15 @@ void OP_F300 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_4 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 4);
+ = load_word ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]));
}
/* mov (abs16), dn */
void OP_300000 (insn, extension)
unsigned long insn, extension;
{
- State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
+ State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
}
/* mov (abs32), dn */
@@ -185,7 +184,7 @@ void OP_FCA40000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem ((((insn & 0xffff) << 16) + extension), 4);
+ = load_word ((((insn & 0xffff) << 16) + extension));
}
/* mov (am), an */
@@ -193,7 +192,7 @@ void OP_F000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG1 (insn)]
- = load_mem (State.regs[REG_A0 + REG0 (insn)], 4);
+ = load_word (State.regs[REG_A0 + REG0 (insn)]);
}
/* mov (d8,am), an */
@@ -201,8 +200,8 @@ void OP_F82000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG1_8 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 4);
+ = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
+ + SEXT8 (insn & 0xff)));
}
/* mov (d16,am), an */
@@ -210,8 +209,8 @@ void OP_FA200000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 4);
+ = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT16 (insn & 0xffff)));
}
/* mov (d32,am), an */
@@ -219,8 +218,8 @@ void OP_FC200000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 4);
+ = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension));
}
/* mov (d8,sp), an */
@@ -228,7 +227,7 @@ void OP_5C00 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG0_8 (insn)]
- = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
+ = load_word (State.regs[REG_SP] + (insn & 0xff));
}
/* mov (d16,sp), an */
@@ -236,7 +235,7 @@ void OP_FAB00000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG0_16 (insn)]
- = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
+ = load_word (State.regs[REG_SP] + (insn & 0xffff));
}
/* mov (d32,sp), an */
@@ -244,7 +243,7 @@ void OP_FCB00000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG0_16 (insn)]
- = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
+ = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}
/* mov (di,am), an */
@@ -252,15 +251,15 @@ void OP_F380 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG0_4 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 4);
+ = load_word ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]));
}
/* mov (abs16), an */
void OP_FAA00000 (insn, extension)
unsigned long insn, extension;
{
- State.regs[REG_A0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 4);
+ State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
}
/* mov (abs32), an */
@@ -268,7 +267,7 @@ void OP_FCA00000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_A0 + REG0_16 (insn)]
- = load_mem ((((insn & 0xffff) << 16) + extension), 4);
+ = load_word ((((insn & 0xffff) << 16) + extension));
}
/* mov (d8,am), sp */
@@ -276,180 +275,177 @@ void OP_F8F000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_SP]
- = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 4);
+ = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
+ + SEXT8 (insn & 0xff)));
}
/* mov dm, (an) */
void OP_60 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
- State.regs[REG_D0 + REG1 (insn)]);
+ store_word (State.regs[REG_A0 + REG0 (insn)],
+ State.regs[REG_D0 + REG1 (insn)]);
}
/* mov dm, (d8,an) */
void OP_F81000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 4,
- State.regs[REG_D0 + REG1_8 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+ State.regs[REG_D0 + REG1_8 (insn)]);
}
/* mov dm (d16,an) */
void OP_FA100000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 4,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* mov dm (d32,an) */
void OP_FC100000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 4,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* mov dm, (d8,sp) */
void OP_4200 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
- State.regs[REG_D0 + REG1_8 (insn)]);
+ store_word (State.regs[REG_SP] + (insn & 0xff),
+ State.regs[REG_D0 + REG1_8 (insn)]);
}
/* mov dm, (d16,sp) */
void OP_FA910000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_word (State.regs[REG_SP] + (insn & 0xffff),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* mov dm, (d32,sp) */
void OP_FC910000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* mov dm, (di,an) */
void OP_F340 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 4,
- State.regs[REG_D0 + REG0_4 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]),
+ State.regs[REG_D0 + REG0_4 (insn)]);
}
/* mov dm, (abs16) */
void OP_10000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + REG1_16 (insn)]);
+ store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
}
/* mov dm, (abs32) */
void OP_FC810000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + REG1_16 (insn)]);
+ store_word ((((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* mov am, (an) */
void OP_F010 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_A0 + REG0 (insn)], 4,
- State.regs[REG_A0 + REG1 (insn)]);
+ store_word (State.regs[REG_A0 + REG0 (insn)],
+ State.regs[REG_A0 + REG1 (insn)]);
}
/* mov am, (d8,an) */
void OP_F83000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 4,
- State.regs[REG_A0 + REG1_8 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+ State.regs[REG_A0 + REG1_8 (insn)]);
}
/* mov am, (d16,an) */
void OP_FA300000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 4,
- State.regs[REG_A0 + REG1_16 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+ State.regs[REG_A0 + REG1_16 (insn)]);
}
/* mov am, (d32,an) */
void OP_FC300000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 4,
- State.regs[REG_A0 + REG1_16 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension),
+ State.regs[REG_A0 + REG1_16 (insn)]);
}
/* mov am, (d8,sp) */
void OP_4300 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
- State.regs[REG_A0 + REG1_8 (insn)]);
+ store_word (State.regs[REG_SP] + (insn & 0xff),
+ State.regs[REG_A0 + REG1_8 (insn)]);
}
/* mov am, (d16,sp) */
void OP_FA900000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
- State.regs[REG_A0 + REG1_16 (insn)]);
+ store_word (State.regs[REG_SP] + (insn & 0xffff),
+ State.regs[REG_A0 + REG1_16 (insn)]);
}
/* mov am, (d32,sp) */
void OP_FC900000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
- State.regs[REG_A0 + REG1_16 (insn)]);
+ store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+ State.regs[REG_A0 + REG1_16 (insn)]);
}
/* mov am, (di,an) */
void OP_F3C0 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 4,
- State.regs[REG_A0 + REG0_4 (insn)]);
+ store_word ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]),
+ State.regs[REG_A0 + REG0_4 (insn)]);
}
/* mov am, (abs16) */
void OP_FA800000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + REG1_16 (insn)]);
+ store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]);
}
/* mov am, (abs32) */
void OP_FC800000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + REG1_16 (insn)]);
+ store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]);
}
/* mov sp, (d8,an) */
void OP_F8F400 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
- 4, State.regs[REG_SP]);
+ store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
+ State.regs[REG_SP]);
}
/* mov imm16, dn */
@@ -497,7 +493,7 @@ void OP_F040 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1 (insn)]
- = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
+ = load_byte (State.regs[REG_A0 + REG0 (insn)]);
}
/* movbu (d8,am), dn */
@@ -505,8 +501,8 @@ void OP_F84000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_8 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 1);
+ = load_byte ((State.regs[REG_A0 + REG0_8 (insn)]
+ + SEXT8 (insn & 0xff)));
}
/* movbu (d16,am), dn */
@@ -514,8 +510,8 @@ void OP_FA400000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 1);
+ = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT16 (insn & 0xffff)));
}
/* movbu (d32,am), dn */
@@ -523,8 +519,8 @@ void OP_FC400000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 1);
+ = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension));
}
/* movbu (d8,sp), dn */
@@ -532,7 +528,7 @@ void OP_F8B800 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_8 (insn)]
- = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
+ = load_byte ((State.regs[REG_SP] + (insn & 0xff)));
}
/* movbu (d16,sp), dn */
@@ -540,7 +536,7 @@ void OP_FAB80000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
+ = load_byte ((State.regs[REG_SP] + (insn & 0xffff)));
}
/* movbu (d32,sp), dn */
@@ -548,7 +544,7 @@ void OP_FCB80000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
+ = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}
/* movbu (di,am), dn */
@@ -556,15 +552,15 @@ void OP_F400 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_4 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 1);
+ = load_byte ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]));
}
/* movbu (abs16), dn */
void OP_340000 (insn, extension)
unsigned long insn, extension;
{
- State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 1);
+ State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
}
/* movbu (abs32), dn */
@@ -572,89 +568,87 @@ void OP_FCA80000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem ((((insn & 0xffff) << 16) + extension), 1);
+ = load_byte ((((insn & 0xffff) << 16) + extension));
}
/* movbu dm, (an) */
void OP_F050 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_A0 + REG0 (insn)], 1,
- State.regs[REG_D0 + REG1 (insn)]);
+ store_byte (State.regs[REG_A0 + REG0 (insn)],
+ State.regs[REG_D0 + REG1 (insn)]);
}
/* movbu dm, (d8,an) */
void OP_F85000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 1,
- State.regs[REG_D0 + REG1_8 (insn)]);
+ store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+ State.regs[REG_D0 + REG1_8 (insn)]);
}
/* movbu dm, (d16,an) */
void OP_FA500000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 1,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movbu dm, (d32,an) */
void OP_FC500000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 1,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movbu dm, (d8,sp) */
void OP_F89200 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
- State.regs[REG_D0 + REG1_8 (insn)]);
+ store_byte (State.regs[REG_SP] + (insn & 0xff),
+ State.regs[REG_D0 + REG1_8 (insn)]);
}
/* movbu dm, (d16,sp) */
void OP_FA920000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_byte (State.regs[REG_SP] + (insn & 0xffff),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movbu dm (d32,sp) */
void OP_FC920000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movbu dm, (di,an) */
void OP_F440 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 1,
- State.regs[REG_D0 + REG0_4 (insn)]);
+ store_byte ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]),
+ State.regs[REG_D0 + REG0_4 (insn)]);
}
/* movbu dm, (abs16) */
void OP_20000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + REG1_16 (insn)]);
+ store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movbu dm, (abs32) */
void OP_FC820000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + REG1_16 (insn)]);
+ store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movhu (am), dn */
@@ -662,7 +656,7 @@ void OP_F060 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1 (insn)]
- = load_mem (State.regs[REG_A0 + REG0 (insn)], 2);
+ = load_half (State.regs[REG_A0 + REG0 (insn)]);
}
/* movhu (d8,am), dn */
@@ -670,8 +664,8 @@ void OP_F86000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_8 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 2);
+ = load_half ((State.regs[REG_A0 + REG0_8 (insn)]
+ + SEXT8 (insn & 0xff)));
}
/* movhu (d16,am), dn */
@@ -679,8 +673,8 @@ void OP_FA600000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 2);
+ = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT16 (insn & 0xffff)));
}
/* movhu (d32,am), dn */
@@ -688,8 +682,8 @@ void OP_FC600000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG1_16 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 2);
+ = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension));
}
/* movhu (d8,sp) dn */
@@ -697,7 +691,7 @@ void OP_F8BC00 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_8 (insn)]
- = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
+ = load_half ((State.regs[REG_SP] + (insn & 0xff)));
}
/* movhu (d16,sp), dn */
@@ -705,7 +699,7 @@ void OP_FABC0000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
+ = load_half ((State.regs[REG_SP] + (insn & 0xffff)));
}
/* movhu (d32,sp), dn */
@@ -713,7 +707,7 @@ void OP_FCBC0000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
+ = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
}
/* movhu (di,am), dn */
@@ -721,15 +715,15 @@ void OP_F480 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_4 (insn)]
- = load_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 2);
+ = load_half ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]));
}
/* movhu (abs16), dn */
void OP_380000 (insn, extension)
unsigned long insn, extension;
{
- State.regs[REG_D0 + REG0_16 (insn)] = load_mem ((insn & 0xffff), 2);
+ State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff));
}
/* movhu (abs32), dn */
@@ -737,89 +731,87 @@ void OP_FCAC0000 (insn, extension)
unsigned long insn, extension;
{
State.regs[REG_D0 + REG0_16 (insn)]
- = load_mem ((((insn & 0xffff) << 16) + extension), 2);
+ = load_half ((((insn & 0xffff) << 16) + extension));
}
/* movhu dm, (an) */
void OP_F070 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_A0 + REG0 (insn)], 2,
- State.regs[REG_D0 + REG1 (insn)]);
+ store_half (State.regs[REG_A0 + REG0 (insn)],
+ State.regs[REG_D0 + REG1 (insn)]);
}
/* movhu dm, (d8,an) */
void OP_F87000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_8 (insn)]
- + SEXT8 (insn & 0xff)), 2,
- State.regs[REG_D0 + REG1_8 (insn)]);
+ store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
+ State.regs[REG_D0 + REG1_8 (insn)]);
}
/* movhu dm, (d16,an) */
void OP_FA700000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT16 (insn & 0xffff)), 2,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movhu dm, (d32,an) */
void OP_FC700000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + ((insn & 0xffff) << 16) + extension), 2,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_half ((State.regs[REG_A0 + REG0_16 (insn)]
+ + ((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movhu dm,(d8,sp) */
void OP_F89300 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
- State.regs[REG_D0 + REG1_8 (insn)]);
+ store_half (State.regs[REG_SP] + (insn & 0xff),
+ State.regs[REG_D0 + REG1_8 (insn)]);
}
/* movhu dm,(d16,sp) */
void OP_FA930000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_half (State.regs[REG_SP] + (insn & 0xffff),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movhu dm,(d32,sp) */
void OP_FC930000 (insn, extension)
unsigned long insn, extension;
{
- store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
- State.regs[REG_D0 + REG1_16 (insn)]);
+ store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
+ State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movhu dm, (di,an) */
void OP_F4C0 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((State.regs[REG_A0 + REG0 (insn)]
- + State.regs[REG_D0 + REG1 (insn)]), 2,
- State.regs[REG_D0 + REG0_4 (insn)]);
+ store_half ((State.regs[REG_A0 + REG0 (insn)]
+ + State.regs[REG_D0 + REG1 (insn)]),
+ State.regs[REG_D0 + REG0_4 (insn)]);
}
/* movhu dm, (abs16) */
void OP_30000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + REG1_16 (insn)]);
+ store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
}
/* movhu dm, (abs32) */
void OP_FC830000 (insn, extension)
unsigned long insn, extension;
{
- store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + REG1_16 (insn)]);
+ store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
}
/* ext dn */
@@ -873,43 +865,43 @@ void OP_CE00 (insn, extension)
if (mask & 0x8)
{
sp += 4;
- State.regs[REG_LAR] = load_mem (sp, 4);
+ State.regs[REG_LAR] = load_word (sp);
sp += 4;
- State.regs[REG_LIR] = load_mem (sp, 4);
+ State.regs[REG_LIR] = load_word (sp);
sp += 4;
- State.regs[REG_MDR] = load_mem (sp, 4);
+ State.regs[REG_MDR] = load_word (sp);
sp += 4;
- State.regs[REG_A0 + 1] = load_mem (sp, 4);
+ State.regs[REG_A0 + 1] = load_word (sp);
sp += 4;
- State.regs[REG_A0] = load_mem (sp, 4);
+ State.regs[REG_A0] = load_word (sp);
sp += 4;
- State.regs[REG_D0 + 1] = load_mem (sp, 4);
+ State.regs[REG_D0 + 1] = load_word (sp);
sp += 4;
- State.regs[REG_D0] = load_mem (sp, 4);
+ State.regs[REG_D0] = load_word (sp);
sp += 4;
}
if (mask & 0x10)
{
- State.regs[REG_A0 + 3] = load_mem (sp, 4);
+ State.regs[REG_A0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x20)
{
- State.regs[REG_A0 + 2] = load_mem (sp, 4);
+ State.regs[REG_A0 + 2] = load_word (sp);
sp += 4;
}
if (mask & 0x40)
{
- State.regs[REG_D0 + 3] = load_mem (sp, 4);
+ State.regs[REG_D0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x80)
{
- State.regs[REG_D0 + 2] = load_mem (sp, 4);
+ State.regs[REG_D0 + 2] = load_word (sp);
sp += 4;
}
@@ -929,43 +921,43 @@ void OP_CF00 (insn, extension)
if (mask & 0x80)
{
sp -= 4;
- store_mem (sp, 4, State.regs[REG_D0 + 2]);
+ store_word (sp, State.regs[REG_D0 + 2]);
}
if (mask & 0x40)
{
sp -= 4;
- store_mem (sp, 4, State.regs[REG_D0 + 3]);
+ store_word (sp, State.regs[REG_D0 + 3]);
}
if (mask & 0x20)
{
sp -= 4;
- store_mem (sp, 4, State.regs[REG_A0 + 2]);
+ store_word (sp, State.regs[REG_A0 + 2]);
}
if (mask & 0x10)
{
sp -= 4;
- store_mem (sp, 4, State.regs[REG_A0 + 3]);
+ store_word (sp, State.regs[REG_A0 + 3]);
}
if (mask & 0x8)
{
sp -= 4;
- store_mem (sp, 4, State.regs[REG_D0]);
+ store_word (sp, State.regs[REG_D0]);
sp -= 4;
- store_mem (sp, 4, State.regs[REG_D0 + 1]);
+ store_word (sp, State.regs[REG_D0 + 1]);
sp -= 4;
- store_mem (sp, 4, State.regs[REG_A0]);
+ store_word (sp, State.regs[REG_A0]);
sp -= 4;
- store_mem (sp, 4, State.regs[REG_A0 + 1]);
+ store_word (sp, State.regs[REG_A0 + 1]);
sp -= 4;
- store_mem (sp, 4, State.regs[REG_MDR]);
+ store_word (sp, State.regs[REG_MDR]);
sp -= 4;
- store_mem (sp, 4, State.regs[REG_LIR]);
+ store_word (sp, State.regs[REG_LIR]);
sp -= 4;
- store_mem (sp, 4, State.regs[REG_LAR]);
+ store_word (sp, State.regs[REG_LAR]);
sp -= 4;
}
@@ -1987,7 +1979,7 @@ void OP_FE020000 (insn, extension)
unsigned long temp;
int n, z;
- temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
+ temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
temp &= (extension & 0xff);
n = (temp & 0x80000000) != 0;
z = (temp == 0);
@@ -2002,8 +1994,8 @@ void OP_FAF80000 (insn, extension)
unsigned long temp;
int n, z;
- temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), 1);
+ temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT8 ((insn & 0xff00) >> 8)));
temp &= (insn & 0xff);
n = (temp & 0x80000000) != 0;
z = (temp == 0);
@@ -2018,10 +2010,10 @@ void OP_F080 (insn, extension)
unsigned long temp;
int z;
- temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
+ temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
temp |= State.regs[REG_D0 + REG1 (insn)];
- store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp);
+ store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
@@ -2033,10 +2025,10 @@ void OP_FE000000 (insn, extension)
unsigned long temp;
int z;
- temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
+ temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8)));
z = (temp & (extension & 0xff)) == 0;
temp |= (extension & 0xff);
- store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
+ store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
@@ -2048,12 +2040,12 @@ void OP_FAF00000 (insn, extension)
unsigned long temp;
int z;
- temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), 1);
+ temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT8 ((insn & 0xff00) >> 8)));
z = (temp & (insn & 0xff)) == 0;
temp |= (insn & 0xff);
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), 1, temp);
+ store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT8 ((insn & 0xff00) >> 8)), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
@@ -2065,10 +2057,10 @@ void OP_F090 (insn, extension)
unsigned long temp;
int z;
- temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
+ temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
- store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp);
+ store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
@@ -2080,10 +2072,10 @@ void OP_FE010000 (insn, extension)
unsigned long temp;
int z;
- temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
+ temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
z = (temp & (extension & 0xff)) == 0;
temp = temp & ~(extension & 0xff);
- store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
+ store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
@@ -2095,12 +2087,12 @@ void OP_FAF40000 (insn, extension)
unsigned long temp;
int z;
- temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), 1);
+ temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT8 ((insn & 0xff00) >> 8)));
z = (temp & (insn & 0xff)) == 0;
temp = temp & ~(insn & 0xff);
- store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
- + SEXT8 ((insn & 0xff00) >> 8)), 1, temp);
+ store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
+ + SEXT8 ((insn & 0xff00) >> 8)), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
@@ -2555,43 +2547,43 @@ void OP_CD000000 (insn, extension)
if (mask & 0x80)
{
adjust -= 4;
- State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0 + 2] = load_word (sp + adjust);
}
if (mask & 0x40)
{
adjust -= 4;
- State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0 + 3] = load_word (sp + adjust);
}
if (mask & 0x20)
{
adjust -= 4;
- State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0 + 2] = load_word (sp + adjust);
}
if (mask & 0x10)
{
adjust -= 4;
- State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0 + 3] = load_word (sp + adjust);
}
if (mask & 0x8)
{
adjust -= 4;
- State.regs[REG_D0] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0 + 1] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_A0] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0 + 1] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_MDR] = load_mem (sp + adjust, 4);
+ State.regs[REG_MDR] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_LIR] = load_mem (sp + adjust, 4);
+ State.regs[REG_LIR] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_LAR] = load_mem (sp + adjust, 4);
+ State.regs[REG_LAR] = load_word (sp + adjust);
adjust -= 4;
}
@@ -2621,43 +2613,43 @@ void OP_DD000000 (insn, extension)
if (mask & 0x80)
{
adjust -= 4;
- State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0 + 2] = load_word (sp + adjust);
}
if (mask & 0x40)
{
adjust -= 4;
- State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0 + 3] = load_word (sp + adjust);
}
if (mask & 0x20)
{
adjust -= 4;
- State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0 + 2] = load_word (sp + adjust);
}
if (mask & 0x10)
{
adjust -= 4;
- State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0 + 3] = load_word (sp + adjust);
}
if (mask & 0x8)
{
adjust -= 4;
- State.regs[REG_D0] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
+ State.regs[REG_D0 + 1] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_A0] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
+ State.regs[REG_A0 + 1] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_MDR] = load_mem (sp + adjust, 4);
+ State.regs[REG_MDR] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_LIR] = load_mem (sp + adjust, 4);
+ State.regs[REG_LIR] = load_word (sp + adjust);
adjust -= 4;
- State.regs[REG_LAR] = load_mem (sp + adjust, 4);
+ State.regs[REG_LAR] = load_word (sp + adjust);
adjust -= 4;
}
@@ -2730,43 +2722,43 @@ void OP_DF0000 (insn, extension)
if (mask & 0x8)
{
sp += 4;
- State.regs[REG_LAR] = load_mem (sp, 4);
+ State.regs[REG_LAR] = load_word (sp);
sp += 4;
- State.regs[REG_LIR] = load_mem (sp, 4);
+ State.regs[REG_LIR] = load_word (sp);
sp += 4;
- State.regs[REG_MDR] = load_mem (sp, 4);
+ State.regs[REG_MDR] = load_word (sp);
sp += 4;
- State.regs[REG_A0 + 1] = load_mem (sp, 4);
+ State.regs[REG_A0 + 1] = load_word (sp);
sp += 4;
- State.regs[REG_A0] = load_mem (sp, 4);
+ State.regs[REG_A0] = load_word (sp);
sp += 4;
- State.regs[REG_D0 + 1] = load_mem (sp, 4);
+ State.regs[REG_D0 + 1] = load_word (sp);
sp += 4;
- State.regs[REG_D0] = load_mem (sp, 4);
+ State.regs[REG_D0] = load_word (sp);
sp += 4;
}
if (mask & 0x10)
{
- State.regs[REG_A0 + 3] = load_mem (sp, 4);
+ State.regs[REG_A0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x20)
{
- State.regs[REG_A0 + 2] = load_mem (sp, 4);
+ State.regs[REG_A0 + 2] = load_word (sp);
sp += 4;
}
if (mask & 0x40)
{
- State.regs[REG_D0 + 3] = load_mem (sp, 4);
+ State.regs[REG_D0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x80)
{
- State.regs[REG_D0 + 2] = load_mem (sp, 4);
+ State.regs[REG_D0 + 2] = load_word (sp);
sp += 4;
}
@@ -2797,43 +2789,43 @@ void OP_DE0000 (insn, extension)
if (mask & 0x8)
{
sp += 4;
- State.regs[REG_LAR] = load_mem (sp, 4);
+ State.regs[REG_LAR] = load_word (sp);
sp += 4;
- State.regs[REG_LIR] = load_mem (sp, 4);
+ State.regs[REG_LIR] = load_word (sp);
sp += 4;
- State.regs[REG_MDR] = load_mem (sp, 4);
+ State.regs[REG_MDR] = load_word (sp);
sp += 4;
- State.regs[REG_A0 + 1] = load_mem (sp, 4);
+ State.regs[REG_A0 + 1] = load_word (sp);
sp += 4;
- State.regs[REG_A0] = load_mem (sp, 4);
+ State.regs[REG_A0] = load_word (sp);
sp += 4;
- State.regs[REG_D0 + 1] = load_mem (sp, 4);
+ State.regs[REG_D0 + 1] = load_word (sp);
sp += 4;
- State.regs[REG_D0] = load_mem (sp, 4);
+ State.regs[REG_D0] = load_word (sp);
sp += 4;
}
if (mask & 0x10)
{
- State.regs[REG_A0 + 3] = load_mem (sp, 4);
+ State.regs[REG_A0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x20)
{
- State.regs[REG_A0 + 2] = load_mem (sp, 4);
+ State.regs[REG_A0 + 2] = load_word (sp);
sp += 4;
}
if (mask & 0x40)
{
- State.regs[REG_D0 + 3] = load_mem (sp, 4);
+ State.regs[REG_D0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x80)
{
- State.regs[REG_D0 + 2] = load_mem (sp, 4);
+ State.regs[REG_D0 + 2] = load_word (sp);
sp += 4;
}
@@ -2897,8 +2889,8 @@ void OP_F020 (insn, extension)
/* Parameters. */
#define PARM1 (State.regs[1])
-#define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
-#define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
+#define PARM2 (load_word (State.regs[REG_SP] + 12))
+#define PARM3 (load_word (State.regs[REG_SP] + 16))
/* Registers set by trap 0 */
@@ -2946,7 +2938,7 @@ void OP_F020 (insn, extension)
case SYS_exit:
/* EXIT - caller can look in PARM1 to work out the
reason */
- if (PARM1 == 0xdead || PARM1 == 0x1)
+ if (PARM1 == 0xdead)
State.exception = SIGABRT;
else
State.exception = SIGQUIT;
@@ -2963,17 +2955,17 @@ void OP_F020 (insn, extension)
buf = PARM2;
/* Just wild-assed guesses. */
- store_mem (buf, 2, host_stat.st_dev);
- store_mem (buf + 2, 2, host_stat.st_ino);
- store_mem (buf + 4, 4, host_stat.st_mode);
- store_mem (buf + 8, 2, host_stat.st_nlink);
- store_mem (buf + 10, 2, host_stat.st_uid);
- store_mem (buf + 12, 2, host_stat.st_gid);
- store_mem (buf + 14, 2, host_stat.st_rdev);
- store_mem (buf + 16, 4, host_stat.st_size);
- store_mem (buf + 20, 4, host_stat.st_atime);
- store_mem (buf + 28, 4, host_stat.st_mtime);
- store_mem (buf + 36, 4, host_stat.st_ctime);
+ store_half (buf, host_stat.st_dev);
+ store_half (buf + 2, host_stat.st_ino);
+ store_word (buf + 4, host_stat.st_mode);
+ store_half (buf + 8, host_stat.st_nlink);
+ store_half (buf + 10, host_stat.st_uid);
+ store_half (buf + 12, host_stat.st_gid);
+ store_half (buf + 14, host_stat.st_rdev);
+ store_word (buf + 16, host_stat.st_size);
+ store_word (buf + 20, host_stat.st_atime);
+ store_word (buf + 28, host_stat.st_mtime);
+ store_word (buf + 36, host_stat.st_ctime);
}
break;
@@ -2993,10 +2985,10 @@ void OP_F020 (insn, extension)
{
struct tms tms;
RETVAL = times (&tms);
- store_mem (PARM1, 4, tms.tms_utime);
- store_mem (PARM1 + 4, 4, tms.tms_stime);
- store_mem (PARM1 + 8, 4, tms.tms_cutime);
- store_mem (PARM1 + 12, 4, tms.tms_cstime);
+ store_word (PARM1, tms.tms_utime);
+ store_word (PARM1 + 4, tms.tms_stime);
+ store_word (PARM1 + 8, tms.tms_cutime);
+ store_word (PARM1 + 12, tms.tms_cstime);
break;
}
#endif
@@ -3005,10 +2997,10 @@ void OP_F020 (insn, extension)
struct timeval t;
struct timezone tz;
RETVAL = gettimeofday (&t, &tz);
- store_mem (PARM1, 4, t.tv_sec);
- store_mem (PARM1 + 4, 4, t.tv_usec);
- store_mem (PARM2, 4, tz.tz_minuteswest);
- store_mem (PARM2 + 4, 4, tz.tz_dsttime);
+ store_word (PARM1, t.tv_sec);
+ store_word (PARM1 + 4, t.tv_usec);
+ store_word (PARM2, tz.tz_minuteswest);
+ store_word (PARM2 + 4, tz.tz_dsttime);
break;
}
#ifdef SYS_utime
generated by cgit v1.1 at 2024-12-25 12:57:41 +0000