diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/bfin/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/bfin/bfin-sim.c | 4 | ||||
| -rw-r--r-- | sim/testsuite/sim/bfin/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/testsuite/sim/bfin/vit_max2.s | 53 |
4 files changed, 63 insertions, 2 deletions
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 4d246ba..3c4e2c0 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,7 @@ +2011-09-28 Mike Frysinger <vapier@gentoo.org> + + * bfin-sim.c (decode_dsp32shift_0): Use STORE() for VIT_MAX insns. + 2011-07-05 Mike Frysinger <vapier@gentoo.org> * interp.c (sim_do_command): Delete. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index fe4dc26..82410f1 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -5516,7 +5516,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) out = sL; SET_AREG (0, acc0); - SET_DREG (dst0, REG_H_L (DREG (dst0), out)); + STORE (DREG (dst0), REG_H_L (DREG (dst0), out)); } else if ((sop == 2 || sop == 3) && sopcde == 9) { @@ -5553,7 +5553,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) out1 = s1L; SET_AREG (0, acc0); - SET_DREG (dst0, REG_H_L (out1 << 16, out0)); + STORE (DREG (dst0), REG_H_L (out1 << 16, out0)); } else if (sop == 0 && sopcde == 10) { diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog index ec487df..72c47e0 100644 --- a/sim/testsuite/sim/bfin/ChangeLog +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -1,3 +1,7 @@ +2011-09-28 Mike Frysinger <vapier@gentoo.org> + + * vit_max2.s: New tests for parallel VIT_MAX insns. + 2011-06-18 Robin Getz <robin.getz@analog.com> * random_0019.S, random_0020.S, random_0021.S, random_0022.S, diff --git a/sim/testsuite/sim/bfin/vit_max2.s b/sim/testsuite/sim/bfin/vit_max2.s new file mode 100644 index 0000000..b7c6a0e --- /dev/null +++ b/sim/testsuite/sim/bfin/vit_max2.s @@ -0,0 +1,53 @@ +# Blackfin testcase for parallel VIT_MAX (taken from PRM) +# mach: bfin + + .include "testutils.inc" + + start + + loadsym P0, scratch + + # Do parallel VIT_MAX's with stores to same reg; don't really + # care what the result is of VIT_MAX as long as it doesn't + # clobber the memory store. + + imm32 R1, 0xFFFF0000 + imm32 R2, 0x0000FFFF + imm32 R0, 0xFACE + R0 = VIT_MAX (R1, R2) (ASL) || W[P0] = R0.L; + imm32 R0, 0xFACE + R4 = W[P0]; + CC = R4 == R0; + IF !CC JUMP 1f; + + imm32 R5, 0xFEEDBEEF + imm32 R4, 0xDEAF0000 + imm32 R6, 0xFACE + R6 = VIT_MAX (R5, R4) (ASR) || W[P0] = R6.L; + imm32 R6, 0xFACE + R4 = W[P0]; + CC = R4 == R6; + IF !CC JUMP 1f; + + imm32 R3, 0xFFFF0000 + imm32 R1, 0xFACE + R1.L = VIT_MAX (R3) (ASL) || W[P0] = R1.L; + imm32 R1, 0xFACE + R4 = W[P0]; + CC = R4 == R1; + IF !CC JUMP 1f; + + imm32 R2, 0x1234FADE + imm32 R5, 0xFACE + R5.L = VIT_MAX (R2) (ASR) || W[P0] = R5.L; + imm32 R5, 0xFACE + R4 = W[P0]; + CC = R4 == R5; + IF !CC JUMP 1f; + + pass +1: fail + + .data +scratch: + .dw 0xffff |