diff options
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mips/ChangeLog | 14 | ||||
| -rw-r--r-- | sim/mips/configure.ac | 4 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 6 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 1 | ||||
| -rw-r--r-- | sim/mips/smartmips.igen | 123 |
5 files changed, 146 insertions, 2 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index f48219a..0a87ebd 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,6 +1,20 @@ 2006-08-29 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> + * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to + sim_igen_machine. + * configure: Regenerate. + * mips.igen (model): Add smartmips. + (MADDU): Increment ACX if carry. + (do_mult): Clear ACX. + (ROR,RORV): Add smartmips. + (include): Include smartmips.igen. + * sim-main.h (ACX): Set to REGISTERS[89]. + * smartmips.igen: New file. + +2006-08-29 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and mips3264r2.igen. Add missing dependency rules. * m16e.igen: Support for mips16e save/restore instructions. diff --git a/sim/mips/configure.ac b/sim/mips/configure.ac index f81abbb..19a9d49 100644 --- a/sim/mips/configure.ac +++ b/sim/mips/configure.ac @@ -146,13 +146,13 @@ case "${target}" in sim_m16_filter="16" ;; mipsisa32r2*-*-*) sim_gen=M16 - sim_igen_machine="-M mips32r2,mips16,mips16e,dsp" + sim_igen_machine="-M mips32r2,mips16,mips16e,dsp,smartmips" sim_m16_machine="-M mips16,mips16e,mips32r2" sim_igen_filter="32,f" sim_mach_default="mipsisa32r2" ;; mipsisa32*-*-*) sim_gen=M16 - sim_igen_machine="-M mips32,mips16,mips16e,dsp" + sim_igen_machine="-M mips32,mips16,mips16e,dsp,smartmips" sim_m16_machine="-M mips16,mips16e,mips32" sim_igen_filter="32,f" sim_mach_default="mipsisa32" diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index e179cf0..85d08ea 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -72,6 +72,7 @@ :model:::mips3d:mips3d: // mips3d.igen :model:::mdmx:mdmx: // mdmx.igen :model:::dsp:dsp: // dsp.igen +:model:::smartmips:smartmips: // smartmips.igen // Vendor Extensions // @@ -2457,6 +2458,7 @@ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); + ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ LO = EXTEND32 (temp); HI = EXTEND32 (VH4_8 (temp)); TRACE_ALU_RESULT2 (HI, LO); @@ -2658,6 +2660,7 @@ * ((signed64)(signed32) GPR[rt])); LO = EXTEND32 (VL4_8 (prod)); HI = EXTEND32 (VH4_8 (prod)); + ACX = 0; /* SmartMIPS */ if (rd != 0) GPR[rd] = LO; TRACE_ALU_RESULT2 (HI, LO); @@ -2850,6 +2853,7 @@ "ror r<RD>, r<RT>, <SHIFT>" *mips32r2: *mips64r2: +*smartmips: *vr5400: *vr5500: { @@ -2860,6 +2864,7 @@ "rorv r<RD>, r<RT>, r<RS>" *mips32r2: *mips64r2: +*smartmips: *vr5400: *vr5500: { @@ -5683,4 +5688,5 @@ :include:::tx.igen :include:::vr.igen :include:::dsp.igen +:include:::smartmips.igen diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 76e6374..b300f07 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -348,6 +348,7 @@ struct _sim_cpu { #define Debug (REGISTERS[86]) #define DEPC (REGISTERS[87]) #define EPC (REGISTERS[88]) +#define ACX (REGISTERS[89]) #define AC0LOIDX (33) /* Must be the same register as LO */ #define AC0HIIDX (34) /* Must be the same register as HI */ diff --git a/sim/mips/smartmips.igen b/sim/mips/smartmips.igen new file mode 100644 index 0000000..31d3a4b --- /dev/null +++ b/sim/mips/smartmips.igen @@ -0,0 +1,123 @@ +// -*- C -*- +// +// Simulator definition for the SmartMIPS extensions. +// Copyright (C) 2005 Free Software Foundation, Inc. +// Contributed by Nigel Stephens (nigel@mips.com) and +// David Ung (davidu@mips.com) of MIPS Technologies. +// +// This file is part of GDB, the GNU debugger. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +011100,5.BASE,5.INDEX,5.RD,00010,001000:SPECIAL:32::LWXS +"lwxs r<RD>, <INDEX>(r<BASE>)" +*smartmips: +{ + GPR[RD] = EXTEND32 (do_load(SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]<<2)); +} + +011100,5.RS,5.RT,00000,10001,000001:SPECIAL:32::MADDP +"maddp r<RS>, r<RT>" +*smartmips: +{ + unsigned64 res; + unsigned64 rs, rt; + int i; + + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + + res = 0; + rs = GPR[RS]; + rt = GPR[RT]; + for (i = 0; i < 32; i++) + { + if (rs & 1) + res ^= rt; + rs >>= 1; + rt <<= 1; + } + LO ^= EXTEND32 (VL4_8 (res)); + HI ^= EXTEND32 (VH4_8 (res)); + TRACE_ALU_RESULT2 (HI, LO); +} + + +000000,0000000000,5.RD,00001,010010:SPECIAL:32::MFLHXU +"mflhxu r<RD>" +*smartmips: +{ + check_mf_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT3 (ACX,HI,LO); + GPR[RD] = LO; + LO = HI; + HI = ACX; + ACX = 0; + TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RD]); +} + +000000,5.RS,000000000000001,010011:SPECIAL:32::MTLHX +"mtlhx r<RS>" +*smartmips: +{ + check_mf_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT3 (HI,LO,GPR[RS]); + ACX = HI; + HI = LO; + LO = GPR[RS]; + TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RS]); +} + +000000,5.RS,5.RT,00000,10001,011001:SPECIAL:32::MULTP +"multp r<RS>, r<RT>" +*smartmips: +{ + unsigned64 res; + unsigned64 rs, rt; + int i; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); + + res = 0; + rs = GPR[RS]; + rt = GPR[RT]; + for (i = 0; i < 32; i++) + { + if (rs & 1) + res ^= rt; + rs >>= 1; + rt <<= 1; + } + LO = EXTEND32 (VL4_8 (res)); + HI = EXTEND32 (VH4_8 (res)); + ACX = 0; + TRACE_ALU_RESULT2 (HI, LO); +} + +011100,5.RS,5.RT,00000,10010,000001:SPECIAL:32::PPERM +"pperm r<RS>, r<RT>" +*smartmips: +{ + int i; + ACX = (ACX << 6) | MSEXTRACTED(HI,26,31); + HI = EXTEND32 ((HI << 6) | MSEXTRACTED(LO,26,31)); + LO = EXTEND32 (LO << 6); + for (i = 0; i < 6; i++) { + int sbit = 5*i; + int ebit = sbit + 4; + int tbit = EXTRACTED(GPR[RT],sbit,ebit); + LO |= MSEXTRACTED(GPR[RS],tbit,tbit) << i; + } +} |