diff options
Diffstat (limited to 'sim')
38 files changed, 751 insertions, 132 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index c51cddd..f850276 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,28 @@ +2003-09-03 Andreas Schwab <schwab@suse.de> + + * Makefile.in (FLAGS_TO_PASS): Pass down $(bindir) and $(mandir). + +2003-08-29 Dave Brolley <brolley@redhat.com> + + * MAINTAINERS: Add myself as maintainer of the FRV port. + +2003-08-20 Michael Snyder <msnyder@redhat.com> + Dave Brolley <brolley@redhat.com> + + * frv/: New directory, simulator for the Fujitsu FRV. + * configure.in: Add frv configury. + * configure: Regenerate. + +2003-08-10 Ben Elliston <bje@wasabisystems.com> + + * MAINTAINERS: Update my mail address. + +2003-08-09 Andrew Cagney <cagney@redhat.com> + + * MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop + maintenance. List igen and sh maintainers. Mention that target + and global maintainers pick up the slack. + 2003-07-09 Michael Snyder <msnyder@redhat.com> * configure.in: Add testsuite to extra_subdirs for sh. diff --git a/sim/MAINTAINERS b/sim/MAINTAINERS index e54adb5..6e05721 100644 --- a/sim/MAINTAINERS +++ b/sim/MAINTAINERS @@ -10,10 +10,17 @@ gdb-patches@sources.redhat.com Maintainers for particular sims: arm Nick Clifton <nickc@redhat.com> +frv Dave Brolley <brolley@redhat.com> +igen (igen simulators) ppc Andrew Cagney <ac131313@redhat.com> -ppc Geoff Keating <geoffk@geoffk.org> m68hc11 Stephane Carrez <stcarrez@nerim.fr> -mips Andrew Cagney <ac131313@redhat.com> mips Chris Demetriou <cgd@broadcom.com> -common Ben Elliston <bje@redhat.com> +sh (global maintainers) +common Ben Elliston <bje@wasabisystems.com> common Frank Ch. Eigler <fche@redhat.com> +* (target, then global maintainers) + + Past sim maintainers: + +mips Andrew Cagney <ac131313@redhat.com> +ppc Geoff Keating <geoffk@geoffk.org> diff --git a/sim/Makefile.in b/sim/Makefile.in index 9a044f0..a46dda8 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -85,6 +85,8 @@ RUNTESTFLAGS= FLAGS_TO_PASS = \ "prefix=$(prefix)" \ "exec_prefix=$(exec_prefix)" \ + "bindir=$(bindir)" \ + "mandir=$(mandir)" \ "against=$(against)" \ "AR=$(AR)" \ "AR_FLAGS=$(AR_FLAGS)" \ diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index c7172f9..ca6d384 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,26 @@ +2003-09-08 Dave Brolley <brolley@redhat.com> + + On behalf of Doug Evans <dje@sebabeach.org> + * cgen.sh: New arg archfile. + * Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode, + cgen-cpu-decode,cgen-desc): Update call to cgen.sh. + +2003-08-28 Andrew Cagney <cagney@redhat.com> + + * dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof. + * sim-options.c (print_help): Cast the format with specifier to + "int". + +2003-08-20 Michael Snyder <msnyder@redhat.com> + Dave Brolley <brolley@redhat.com> + + * cgen-par.h (flags, word1): New target-specific + fields of CGEN_WRITE_QUEUE_ELEMENT. + (CGEN_WRITE_QUEUE_ELEMENT_FLAGS): New accessor macro. + (CGEN_WRITE_QUEUE_ELEMENT_WORD1): New accessor macro. + * gennltvals.sh: Add frv target. + * nltvals.def: Add frv target. + 2003-06-23 Michael Snyder <msnyder@redhat.com> * nrun.c (main): Delete h8/300 ifdef (sim now handles signals). diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in index 53f898a..cc93bde 100644 --- a/sim/common/Make-common.in +++ b/sim/common/Make-common.in @@ -674,31 +674,37 @@ CGEN_FLAGS_TO_PASS = \ cgen-arch: force $(SHELL) $(srccom)/cgen.sh arch $(srcdir) \ $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ - $(arch) "$(FLAGS)" ignored "$(isa)" $(mach) ignored ignored + $(arch) "$(FLAGS)" ignored "$(isa)" $(mach) ignored \ + $(archfile) ignored cgen-cpu: force $(SHELL) $(srccom)/cgen.sh cpu $(srcdir) \ $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ - $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" "$(EXTRAFILES)" + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) "$(EXTRAFILES)" cgen-defs: force $(SHELL) $(srccom)/cgen.sh defs $(srcdir) \ $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ - $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" ignored + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) ignored cgen-decode: force $(SHELL) $(srccom)/cgen.sh decode $(srcdir) \ $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ - $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" "$(EXTRAFILES)" + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) "$(EXTRAFILES)" cgen-cpu-decode: force $(SHELL) $(srccom)/cgen.sh cpu-decode $(srcdir) \ $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ - $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" "$(EXTRAFILES)" + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) "$(EXTRAFILES)" cgen-desc: force $(SHELL) $(srccom)/cgen.sh desc $(srcdir) \ $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ - $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" ignored + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) ignored ## End COMMON_POST_CONFIG_FRAG diff --git a/sim/common/cgen-par.h b/sim/common/cgen-par.h index 1b8a321..fad04b9 100644 --- a/sim/common/cgen-par.h +++ b/sim/common/cgen-par.h @@ -39,6 +39,8 @@ enum cgen_write_queue_kind { typedef struct { enum cgen_write_queue_kind kind; /* Used to select union member below. */ IADDR insn_address; /* Address of the insn performing the write. */ + unsigned32 flags; /* Target specific flags. */ + long word1; /* Target specific field. */ union { struct { BI *target; @@ -152,6 +154,8 @@ typedef struct { #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind) #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address) +#define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags) +#define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1) extern void cgen_write_queue_element_execute ( SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT * diff --git a/sim/common/cgen.sh b/sim/common/cgen.sh index bf467e1..172edcb 100644 --- a/sim/common/cgen.sh +++ b/sim/common/cgen.sh @@ -3,7 +3,7 @@ # # Usage: /bin/sh cgen.sh {"arch"|"cpu"|"decode"|"defs"|"cpu-decode"} \ # srcdir cgen cgendir cgenflags \ -# arch archflags cpu mach suffix extrafiles +# arch archflags cpu mach suffix archfile extrafiles # # We store the generated files in the source directory until we decide to # ship a Scheme interpreter (or other implementation) with gdb/binutils. @@ -24,6 +24,7 @@ isa=$9 # portably bring parameters beyond $9 into view shift ; mach=$9 shift ; suffix=$9 +shift ; archfile=$9 shift ; extrafiles=$9 rootdir=${srcdir}/../.. @@ -57,7 +58,7 @@ arch) ${cgenflags} \ -f "${archflags}" \ -m ${mach} \ - -a ${arch} \ + -a ${archfile} \ -i ${isa} \ -A tmp-arch.h1 \ -B tmp-arch.c1 \ @@ -111,7 +112,7 @@ cpu | decode | cpu-decode) ${cgenflags} \ -f "${archflags}" \ -m ${mach} \ - -a ${arch} \ + -a ${archfile} \ -i ${isa} \ ${fileopts} @@ -180,7 +181,7 @@ defs) ${cgenflags} \ -f "${archflags}" \ -m ${mach} \ - -a ${arch} \ + -a ${archfile} \ -i ${isa} \ -G tmp-defs.h1 sed $sedscript < tmp-defs.h1 > tmp-defs.h @@ -197,7 +198,7 @@ desc) ${cgenflags} \ -f "${archflags}" \ -m ${mach} \ - -a ${arch} \ + -a ${archfile} \ -i ${isa} \ -H tmp-desc.h1 \ -C tmp-desc.c1 \ diff --git a/sim/common/dv-glue.c b/sim/common/dv-glue.c index 560fd70..ab04fe7 100644 --- a/sim/common/dv-glue.c +++ b/sim/common/dv-glue.c @@ -221,7 +221,7 @@ hw_glue_finish (struct hw *me) if (glue->sizeof_output == 0) hw_abort (me, "at least one reg property size must be nonzero"); if (glue->sizeof_output % sizeof (unsigned_word) != 0) - hw_abort (me, "reg property size must be %d aligned", + hw_abort (me, "reg property size must be %ld aligned", sizeof (unsigned_word)); /* and the address */ hw_unit_address_to_attach_address (hw_parent (me), @@ -230,7 +230,7 @@ hw_glue_finish (struct hw *me) &glue->address, me); if (glue->address % (sizeof (unsigned_word) * max_nr_ports) != 0) - hw_abort (me, "reg property address must be %d aligned", + hw_abort (me, "reg property address must be %ld aligned", sizeof (unsigned_word) * max_nr_ports); glue->nr_outputs = glue->sizeof_output / sizeof (unsigned_word); glue->output = hw_zalloc (me, glue->sizeof_output); diff --git a/sim/common/gennltvals.sh b/sim/common/gennltvals.sh index fefd880..8e8ad54 100644 --- a/sim/common/gennltvals.sh +++ b/sim/common/gennltvals.sh @@ -41,6 +41,10 @@ dir=libgloss target=fr30 $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" +dir=libgloss target=frv +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + dir=libgloss/i960 target=i960 $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" @@ -64,3 +68,4 @@ $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ dir=libgloss/v850/sys target=v850 $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + diff --git a/sim/common/nltvals.def b/sim/common/nltvals.def index 14093ae..9139dc4 100644 --- a/sim/common/nltvals.def +++ b/sim/common/nltvals.def @@ -238,6 +238,32 @@ /* end fr30 sys target macros */ #endif #endif +#ifdef NL_TARGET_frv +#ifdef sys_defs +/* from syscall.h */ +/* begin frv sys target macros */ + { "SYS_argv", 13 }, + { "SYS_argvlen", 12 }, + { "SYS_chdir", 14 }, + { "SYS_chmod", 16 }, + { "SYS_close", 3 }, + { "SYS_exit", 1 }, + { "SYS_fstat", 10 }, + { "SYS_getpid", 8 }, + { "SYS_gettimeofday", 19 }, + { "SYS_kill", 9 }, + { "SYS_lseek", 6 }, + { "SYS_open", 2 }, + { "SYS_read", 4 }, + { "SYS_stat", 15 }, + { "SYS_time", 18 }, + { "SYS_times", 20 }, + { "SYS_unlink", 7 }, + { "SYS_utime", 17 }, + { "SYS_write", 5 }, +/* end frv sys target macros */ +#endif +#endif #ifdef NL_TARGET_i960 #ifdef sys_defs /* from syscall.h */ diff --git a/sim/common/sim-options.c b/sim/common/sim-options.c index 8c16d56..df12a63 100644 --- a/sim/common/sim-options.c +++ b/sim/common/sim-options.c @@ -769,7 +769,10 @@ print_help (SIM_DESC sd, sim_cpu *cpu, const struct option_list *ol, int is_comm end --; if (end == chp) end = chp + doc_width - 1; - sim_io_printf (sd, "%.*s\n%*s", end - chp, chp, indent, ""); + /* The cast should be ok - its distances between to + points in a string. */ + sim_io_printf (sd, "%.*s\n%*s", (int) (end - chp), chp, indent, + ""); chp = end; while (isspace (*chp) && *chp != '\0') chp++; diff --git a/sim/configure b/sim/configure index d6382b6..b342d39 100755 --- a/sim/configure +++ b/sim/configure @@ -1430,6 +1430,9 @@ case "${target}" in sim_target=h8300 extra_subdirs="${extra_subdirs} testsuite" ;; + frv-*-*) sim_target=frv + extra_subdirs="${extra_subdirs} testsuite" + ;; h8500-*-*) sim_target=h8500 ;; i960-*-*) sim_target=i960 ;; m32r-*-*) sim_target=m32r ;; diff --git a/sim/configure.in b/sim/configure.in index da2f20a..f9ec687 100644 --- a/sim/configure.in +++ b/sim/configure.in @@ -69,6 +69,9 @@ case "${target}" in sim_target=h8300 extra_subdirs="${extra_subdirs} testsuite" ;; + frv-*-*) sim_target=frv + extra_subdirs="${extra_subdirs} testsuite" + ;; h8500-*-*) sim_target=h8500 ;; i960-*-*) sim_target=i960 ;; m32r-*-*) sim_target=m32r ;; diff --git a/sim/i960/ChangeLog b/sim/i960/ChangeLog index 1f61c31..becf43f 100644 --- a/sim/i960/ChangeLog +++ b/sim/i960/ChangeLog @@ -1,3 +1,8 @@ +2003-09-08 Dave Brolley <brolley@redhat.com> + + On behalf of Doug Evans <dje@sebabeach.org> + * Makefile.in (stamp-arch,stamp-cpu, stamp-desc): Pass archfile to cgen. + 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. diff --git a/sim/i960/Makefile.in b/sim/i960/Makefile.in index b1e0abe..4fc24d4 100644 --- a/sim/i960/Makefile.in +++ b/sim/i960/Makefile.in @@ -107,19 +107,24 @@ CGEN_MAINT = ; @true stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/i960.cpu $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \ + archfile=$(CGEN_CPU_DIR)/i960.cpu \ FLAGS="with-scache with-profile=fn" touch stamp-arch arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/i960.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=i960base mach=i960:ka_sa,i960:ca SUFFIX= FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" + cpu=i960base mach=i960:ka_sa,i960:ca SUFFIX= \ + archfile=$(CGEN_CPU_DIR)/i960.cpu \ + FLAGS="with-scache with-profile=fn" \ + EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" touch stamp-cpu cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \ $(CGEN_CPU_DIR)/sparc.cpu $(CGEN_CPU_DIR)/sparccom.cpu $(CGEN_CPU_DIR)/i960.cpu $(CGEN_CPU_DIR)/i960.cpu $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \ - cpu=i960 mach=all + cpu=i960 mach=all \ + archfile=$(CGEN_CPU_DIR)/i960.cpu touch stamp-desc i960-desc.c i960-desc.h i960-opc.h: $(CGEN_MAINT) stamp-desc diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index b4097db..b6d7c24 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,8 @@ +2003-09-08 Dave Brolley <brolley@redhat.com> + + On behalf of Doug Evans <dje@sebabeach.org> + * Makefile.in (stamp-arch,stamp-cpu,stamp-xcpu): Pass archfile to cgen. + 2003-02-27 Andrew Cagney <cagney@redhat.com> * sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd. diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in index 7f40a85..18d9d3f 100644 --- a/sim/m32r/Makefile.in +++ b/sim/m32r/Makefile.in @@ -126,6 +126,7 @@ CGEN_MAINT = ; @true stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \ + archfile=$(CGEN_CPU_DIR)/m32r.cpu \ FLAGS="with-scache with-profile=fn" touch stamp-arch arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch @@ -133,6 +134,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ cpu=m32rbf mach=m32r SUFFIX= \ + archfile=$(CGEN_CPU_DIR)/m32r.cpu \ FLAGS="with-scache with-profile=fn" \ EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" touch stamp-cpu @@ -140,6 +142,9 @@ cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)" + cpu=m32rxf mach=m32rx SUFFIX=x \ + archfile=$(CGEN_CPU_DIR)/m32r.cpu \ + FLAGS="with-scache with-profile=fn" \ + EXTRAFILES="$(CGEN_CPU_SEMSW)" touch stamp-xcpu cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog index 9c34d47..3d019d7 100644 --- a/sim/m68hc11/ChangeLog +++ b/sim/m68hc11/ChangeLog @@ -1,3 +1,57 @@ +2003-08-08 Stephane Carrez <stcarrez@nerim.fr> + + * dv-m68hc11tim.c (cycle_to_string): Add flags parameter to better + control the translation. + (m68hc11tim_print_timer): Update cycle_to_string conversion. + (m68hc11tim_timer_event): Fix handling of output + compare register with its interrupts. + (m68hc11tim_io_write_buffer): Check output compare + after setting M6811_TMSK1. + (m68hc11tim_io_read_buffer): Fix compilation warning. + * dv-m68hc11.c (m68hc11_option_handler): Likewise. + * dv-m68hc11spi.c (m68hc11spi_info): Likewise. + * dv-m68hc11sio.c (m68hc11sio_info): Likewise. + * interrupts.c (interrupts_info): Likewise. + (interrupts_reset): Recognize bootstrap mode. + * sim-main.h (PRINT_CYCLE, PRINT_TIME): New defines. + (_sim_cpu): Add cpu_start_mode. + (cycle_to_string): Add flags member. + * m68hc11_sim.c (OPTION_CPU_BOOTSTRAP): New option. + (cpu_options): Declare new option bootstrap. + (cpu_option_handler): Handle it. + (cpu_info): Update call to cycle_to_string. + +2003-08-08 Stephane Carrez <stcarrez@nerim.fr> + + * sim-main.h (phys_to_virt): Use memory bank parameters to translate + the physical address in virtual address. + (struct _sim_cpu): Add memory bank members. + * m68hc11_sim.c (cpu_initialize): Clear memory bank parameters. + * interp.c (sim_hw_configure): Create memory bank according to memory + bank parameters. + (sim_get_bank_parameters): New function to obtain memory bank config + from the symbol table. + (sim_prepare_for_program): Call it to obtain the memory bank parameters. + (sim_open): Call sim_prepare_for_program. + * dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters + to check if address is within bank window. + (m68hc11cpu_io_read_buffer): Likewise. + (attach_m68hc11_regs): Map the memory bank according to memory bank + parameters. + +2003-08-08 Stephane Carrez <stcarrez@nerim.fr>, + + * sim-main.h (PAGE_REGNUM, Z_REGNUM): Use same numbering as gdb. + +2003-08-08 Stephane Carrez <stcarrez@nerim.fr>, + Gary Piercey <gpiercey@northstar-technical.com> + + * m68hc11_sim.c (print_io_word): New function to print 16-bit value. + * sim-main.h (print_io_word): Declare. + * dv-m68hc11tim.c (tmsk1_desc): New description table for TMSK1. + (tflg1_desc): Likewise for TFLG1. + (m68hc11tim_info): Print input and output compare registers + 2003-03-02 Stephane Carrez <stcarrez@nerim.fr> * Makefile.in (SIM_EXTRA_CFLAGS): Set WITH_TARGET_ADDRESS_BITSIZE diff --git a/sim/m68hc11/dv-m68hc11.c b/sim/m68hc11/dv-m68hc11.c index 669a045..5cc7161 100644 --- a/sim/m68hc11/dv-m68hc11.c +++ b/sim/m68hc11/dv-m68hc11.c @@ -1,5 +1,5 @@ /* dv-m68hc11.c -- CPU 68HC11&68HC12 as a device. - Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) (From a driver model Contributed by Cygnus Solutions.) @@ -324,8 +324,8 @@ attach_m68hc11_regs (struct hw *me, if (hw_find_property (me, "use_bank") != NULL) hw_attach_address (hw_parent (me), 0, exec_map, - 0x08000, - 0x04000, + cpu->bank_start, + cpu->bank_end - cpu->bank_start, me); cpu_mode = "expanded"; @@ -808,13 +808,15 @@ m68hc11_option_handler (SIM_DESC sd, sim_cpu *cpu, " %d %d %35.35s\n", osc->name, freq, cur_value, next_value, - cycle_to_string (cpu, t)); + cycle_to_string (cpu, t, + PRINT_TIME | PRINT_CYCLE)); else sim_io_printf (sd, " %4.4s %8.8s hz " " %d %d %35.35s\n", osc->name, freq, cur_value, next_value, - cycle_to_string (cpu, t)); + cycle_to_string (cpu, t, + PRINT_TIME | PRINT_CYCLE)); } } break; @@ -843,7 +845,7 @@ m68hc11cpu_io_read_buffer (struct hw *me, sd = hw_system (me); cpu = STATE_CPU (sd, 0); - if (base >= 0x8000 && base < 0xc000) + if (base >= cpu->bank_start && base < cpu->bank_end) { address_word virt_addr = phys_to_virt (cpu, base); if (virt_addr != base) @@ -864,7 +866,7 @@ m68hc11cpu_io_read_buffer (struct hw *me, break; memcpy (dest, &cpu->ios[base], 1); - dest++; + dest = (char*) dest + 1; base++; byte++; nr_bytes--; @@ -1091,7 +1093,7 @@ m68hc11cpu_io_write_buffer (struct hw *me, sd = hw_system (me); cpu = STATE_CPU (sd, 0); - if (base >= 0x8000 && base < 0xc000) + if (base >= cpu->bank_start && base < cpu->bank_end) { address_word virt_addr = phys_to_virt (cpu, base); if (virt_addr != base) @@ -1113,7 +1115,7 @@ m68hc11cpu_io_write_buffer (struct hw *me, val = *((uint8*) source); m68hc11cpu_io_write (me, cpu, base, val); - source++; + source = (char*) source + 1; base++; byte++; nr_bytes--; diff --git a/sim/m68hc11/dv-m68hc11sio.c b/sim/m68hc11/dv-m68hc11sio.c index ec7a46d..655a6db 100644 --- a/sim/m68hc11/dv-m68hc11sio.c +++ b/sim/m68hc11/dv-m68hc11sio.c @@ -463,7 +463,8 @@ m68hc11sio_info (struct hw *me) n = (clock_cycle - t) / controller->baud_cycle; n = controller->data_length - n; sim_io_printf (sd, " Transmit finished in %s (%d bit%s)\n", - cycle_to_string (cpu, t), n, (n > 1 ? "s" : "")); + cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE), + n, (n > 1 ? "s" : "")); } if (controller->rx_poll_event) { @@ -471,7 +472,7 @@ m68hc11sio_info (struct hw *me) t = hw_event_remain_time (me, controller->rx_poll_event); sim_io_printf (sd, " Receive finished in %s\n", - cycle_to_string (cpu, t)); + cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } } diff --git a/sim/m68hc11/dv-m68hc11spi.c b/sim/m68hc11/dv-m68hc11spi.c index 5f5e0bb..619a2d3 100644 --- a/sim/m68hc11/dv-m68hc11spi.c +++ b/sim/m68hc11/dv-m68hc11spi.c @@ -1,6 +1,6 @@ /* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI - Copyright (C) 2000, 2002 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) (From a driver model Contributed by Cygnus Solutions.) This file is part of the program GDB, the GNU debugger. @@ -358,11 +358,11 @@ m68hc11spi_info (struct hw *me) controller->tx_bit + 1); t = hw_event_remain_time (me, controller->spi_event); sim_io_printf (sd, " SPI current bit-cycle finished in %s\n", - cycle_to_string (cpu, t)); + cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); t += (controller->tx_bit + 1) * 2 * controller->clock; sim_io_printf (sd, " SPI operation finished in %s\n", - cycle_to_string (cpu, t)); + cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } } diff --git a/sim/m68hc11/dv-m68hc11tim.c b/sim/m68hc11/dv-m68hc11tim.c index 3edcac0..0456f67 100644 --- a/sim/m68hc11/dv-m68hc11tim.c +++ b/sim/m68hc11/dv-m68hc11tim.c @@ -1,6 +1,6 @@ /* dv-m68hc11tim.c -- Simulation of the 68HC11 timer devices. - Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright (C) 1999, 2000, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) (From a driver model Contributed by Cygnus Solutions.) This file is part of the program GDB, the GNU debugger. @@ -25,7 +25,7 @@ #include "sim-main.h" #include "hw-main.h" #include "sim-assert.h" - +#include <limits.h> /* DEVICE @@ -250,7 +250,9 @@ m68hc11tim_timer_event (struct hw *me, void *data) unsigned mask; unsigned flags; unsigned long tcnt_internal; - unsigned long tcnt; + unsigned long tcnt, tcnt_prev; + signed64 tcnt_insn_end; + signed64 tcnt_insn_start; int i; sim_events *events; @@ -289,11 +291,8 @@ m68hc11tim_timer_event (struct hw *me, void *data) break; case OVERFLOW_EVENT: - /* Compute the 68HC11 internal free running counter. - There may be 'nr_ticks_to_process' pending cycles that are - not (yet) taken into account by 'sim_events_time'. */ - tcnt_internal = sim_events_time (sd) - controller->tcnt_adjust; - tcnt_internal += events->nr_ticks_to_process; + /* Compute the 68HC11 internal free running counter. */ + tcnt_internal = (cpu->cpu_absolute_cycle - controller->tcnt_adjust); /* We must take into account the prescaler that comes before the counter (it's a power of 2). */ @@ -316,22 +315,22 @@ m68hc11tim_timer_event (struct hw *me, void *data) break; case COMPARE_EVENT: - eventp = &controller->cmp_timer_event; + /* Compute value of TCNT register (64-bit precision) at beginning + and end of instruction. */ + tcnt_insn_end = (cpu->cpu_absolute_cycle - controller->tcnt_adjust); + tcnt_insn_start = (tcnt_insn_end - cpu->cpu_current_cycle); + + /* TCNT value at beginning of current instruction. */ + tcnt_prev = (tcnt_insn_start / controller->clock_prescaler) & 0x0ffff; - /* Compute the 68HC11 internal free running counter. - There may be 'nr_ticks_to_process' pending cycles that are - not (yet) taken into account by 'sim_events_time'. */ - events = STATE_EVENTS (sd); - tcnt_internal = sim_events_time (sd) - controller->tcnt_adjust; - tcnt_internal += events->nr_ticks_to_process; + /* TCNT value at end of current instruction. */ + tcnt = (tcnt_insn_end / controller->clock_prescaler) & 0x0ffff; /* We must take into account the prescaler that comes before the counter (it's a power of 2). */ + tcnt_internal = tcnt_insn_end; tcnt_internal &= 0x0ffff * controller->clock_prescaler; - /* Get current visible TCNT register value. */ - tcnt = tcnt_internal / controller->clock_prescaler; - flags = cpu->ios[M6811_TMSK1]; mask = 0x80; delay = 65536 * controller->clock_prescaler; @@ -342,12 +341,28 @@ m68hc11tim_timer_event (struct hw *me, void *data) for (i = M6811_TOC1; i <= M6811_TOC5; i += 2, mask >>= 1) { unsigned long compare; - - compare = (cpu->ios[i] << 8) + cpu->ios[i+1]; - if (compare == tcnt && (flags & mask)) + + compare = (cpu->ios[i] << 8) + cpu->ios[i + 1]; + + /* See if compare is reached; handle wrap arround. */ + if ((compare >= tcnt_prev && compare <= tcnt && tcnt_prev < tcnt) + || (compare >= tcnt_prev && tcnt_prev > tcnt) + || (compare < tcnt && tcnt_prev > tcnt)) { + unsigned dt; + + if (compare > tcnt) + dt = 0x10000 - compare - tcnt; + else + dt = tcnt - compare; + cpu->ios[M6811_TFLG1] |= mask; - check_interrupt++; + + /* Raise interrupt now at the correct CPU cycle so that + we can find the interrupt latency. */ + cpu->cpu_absolute_cycle -= dt; + interrupts_update_pending (&cpu->cpu_interrupts); + cpu->cpu_absolute_cycle += dt; } /* Compute how many times for the next match. @@ -359,14 +374,18 @@ m68hc11tim_timer_event (struct hw *me, void *data) else compare = compare - tcnt_internal + 65536 * controller->clock_prescaler; - + if (compare < delay) delay = compare; } /* Deactivate the compare timer if no output compare is enabled. */ - if ((flags & 0xF0) == 0) + if ((flags & 0xF8) == 0) delay = 0; + else + delay += events->nr_ticks_to_process; + + eventp = &controller->cmp_timer_event; break; default: @@ -394,6 +413,30 @@ m68hc11tim_timer_event (struct hw *me, void *data) /* Descriptions of the Timer I/O ports. These descriptions are only used to give information of the Timer device under GDB. */ +io_reg_desc tmsk1_desc[] = { + { M6811_OC1I, "OC1I ", "Timer Output Compare 1 Interrupt Enable" }, + { M6811_OC2I, "OC2I ", "Timer Output Compare 2 Interrupt Enable" }, + { M6811_OC3I, "OC3I ", "Timer Output Compare 3 Interrupt Enable" }, + { M6811_OC4I, "OC4I ", "Timer Output Compare 4 Interrupt Enable" }, + { M6811_OC5I, "OC5I ", "Timer Input Capture 4 / Output Compare 5 Enable" }, + { M6811_IC1I, "IC1I ", "Timer Input Capture 1 Interrupt Enable" }, + { M6811_IC2I, "IC2I ", "Timer Input Capture 2 Interrupt Enable" }, + { M6811_IC3I, "IC3I ", "Timer Input Capture 3 Interrupt Enable" }, + { 0, 0, 0 } +}; + +io_reg_desc tflg1_desc[] = { + { M6811_OC1F, "OC1F ", "Timer Output Compare 1 Interrupt Flag" }, + { M6811_OC2F, "OC2F ", "Timer Output Compare 2 Interrupt Flag" }, + { M6811_OC3F, "OC3F ", "Timer Output Compare 3 Interrupt Flag" }, + { M6811_OC4F, "OC4F ", "Timer Output Compare 4 Interrupt Flag" }, + { M6811_OC5F, "OC5F ", "Timer Input Capture 4 / Output Compare 5 Flag" }, + { M6811_IC1F, "IC1F ", "Timer Input Capture 1 Interrupt Flag" }, + { M6811_IC2F, "IC2F ", "Timer Input Capture 2 Interrupt Flag" }, + { M6811_IC3F, "IC3F ", "Timer Input Capture 3 Interrupt Flag" }, + { 0, 0, 0 } +}; + io_reg_desc tmsk2_desc[] = { { M6811_TOI, "TOI ", "Timer Overflow Interrupt Enable" }, { M6811_RTII, "RTII ", "RTI Interrupt Enable" }, @@ -433,22 +476,35 @@ to_realtime (sim_cpu *cpu, signed64 t) } const char* -cycle_to_string (sim_cpu *cpu, signed64 t) +cycle_to_string (sim_cpu *cpu, signed64 t, int flags) { - double dt; - char tbuf[32]; + char time_buf[32]; + char cycle_buf[32]; static char buf[64]; - dt = to_realtime (cpu, t); - if (dt < 0.001) - sprintf (tbuf, "(%3.1f us)", dt * 1000000.0); - else if (dt < 1.0) - sprintf (tbuf, "(%3.1f ms)", dt * 1000.0); - else - sprintf (tbuf, "(%3.1f s)", dt); + time_buf[0] = 0; + cycle_buf[0] = 0; + if (flags & PRINT_TIME) + { + double dt; + + dt = to_realtime (cpu, t); + if (dt < 0.001) + sprintf (time_buf, " (%3.1f us)", dt * 1000000.0); + else if (dt < 1.0) + sprintf (time_buf, " (%3.1f ms)", dt * 1000.0); + else + sprintf (time_buf, " (%3.1f s)", dt); + } + + if (flags & PRINT_CYCLE) + sprintf (cycle_buf, " cycle%s", + (t > 1 ? "s" : "")); - sprintf (buf, "%llu cycle%s %10.10s", t, - (t > 1 ? "s" : ""), tbuf); + if (t < LONG_MAX) + sprintf (buf, "%9lu%s%s", (unsigned long) t, cycle_buf, time_buf); + else + sprintf (buf, "%llu%s%s", t, cycle_buf, time_buf); return buf; } @@ -472,7 +528,7 @@ m68hc11tim_print_timer (struct hw *me, const char *name, t = hw_event_remain_time (me, event); sim_io_printf (sd, " Next %s interrupt in %s\n", - name, cycle_to_string (cpu, t)); + name, cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } } @@ -484,6 +540,7 @@ m68hc11tim_info (struct hw *me) sim_cpu *cpu; struct m68hc11tim *controller; uint8 val; + uint16 val16; sd = hw_system (me); cpu = STATE_CPU (sd, 0); @@ -493,6 +550,56 @@ m68hc11tim_info (struct hw *me) base = cpu_get_io_base (cpu); + /* Info for TIC1 */ + val16 = (cpu->ios[M6811_TIC1_H] << 8) + cpu->ios[M6811_TIC1_L]; + print_io_word (sd, "TIC1 ", 0, val16, base + M6811_TIC1); + sim_io_printf (sd, "\n"); + + /* Info for TIC2 */ + val16 = (cpu->ios[M6811_TIC2_H] << 8) + cpu->ios[M6811_TIC2_L]; + print_io_word (sd, "TIC2 ", 0, val16, base + M6811_TIC2); + sim_io_printf (sd, "\n"); + + /* Info for TIC3 */ + val16 = (cpu->ios[M6811_TIC3_H] << 8) + cpu->ios[M6811_TIC3_L]; + print_io_word (sd, "TIC3 ", 0, val16, base + M6811_TIC3); + sim_io_printf (sd, "\n"); + + /* Info for TOC1 */ + val16 = (cpu->ios[M6811_TOC1_H] << 8) + cpu->ios[M6811_TOC1_L]; + print_io_word (sd, "TOC1 ", 0, val16, base + M6811_TOC1); + sim_io_printf (sd, "\n"); + + /* Info for TOC2 */ + val16 = (cpu->ios[M6811_TOC2_H] << 8) + cpu->ios[M6811_TOC2_L]; + print_io_word (sd, "TOC2 ", 0, val16, base + M6811_TOC2); + sim_io_printf (sd, "\n"); + + /* Info for TOC3 */ + val16 = (cpu->ios[M6811_TOC3_H] << 8) + cpu->ios[M6811_TOC3_L]; + print_io_word (sd, "TOC3 ", 0, val16, base + M6811_TOC3); + sim_io_printf (sd, "\n"); + + /* Info for TOC4 */ + val16 = (cpu->ios[M6811_TOC4_H] << 8) + cpu->ios[M6811_TOC4_L]; + print_io_word (sd, "TOC4 ", 0, val16, base + M6811_TOC4); + sim_io_printf (sd, "\n"); + + /* Info for TOC5 */ + val16 = (cpu->ios[M6811_TOC5_H] << 8) + cpu->ios[M6811_TOC5_L]; + print_io_word (sd, "TOC5 ", 0, val16, base + M6811_TOC5); + sim_io_printf (sd, "\n"); + + /* Info for TMSK1 */ + val = cpu->ios[M6811_TMSK1]; + print_io_byte (sd, "TMSK1 ", tmsk1_desc, val, base + M6811_TMSK1); + sim_io_printf (sd, "\n"); + + /* Info for TFLG1 */ + val = cpu->ios[M6811_TFLG1]; + print_io_byte (sd, "TFLG1", tflg1_desc, val, base + M6811_TFLG1); + sim_io_printf (sd, "\n"); + val = cpu->ios[M6811_TMSK2]; print_io_byte (sd, "TMSK2 ", tmsk2_desc, val, base + M6811_TMSK2); sim_io_printf (sd, "\n"); @@ -568,7 +675,7 @@ m68hc11tim_io_read_buffer (struct hw *me, break; } *((unsigned8*) dest) = val; - dest++; + dest = (char*) dest + 1; base++; nr_bytes--; cnt++; @@ -679,6 +786,7 @@ m68hc11tim_io_write_buffer (struct hw *me, case M6811_TMSK1: cpu->ios[M6811_TMSK1] = val; interrupts_update_pending (&cpu->cpu_interrupts); + reset_compare = 1; break; case M6811_TFLG1: @@ -695,7 +803,7 @@ m68hc11tim_io_write_buffer (struct hw *me, cpu->ios[base] = val; reset_compare = 1; break; - + case M6811_TCTL1: case M6811_TCTL2: cpu->ios[base] = val; @@ -709,7 +817,7 @@ m68hc11tim_io_write_buffer (struct hw *me, base++; nr_bytes--; cnt++; - source++; + source = (char*) source + 1; } /* Re-compute the next timer compare event. */ diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c index 3da382d..b80bc94 100644 --- a/sim/m68hc11/interp.c +++ b/sim/m68hc11/interp.c @@ -1,5 +1,5 @@ /* interp.c -- Simulator for Motorola 68HC11/68HC12 - Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, the GNU debugger. @@ -25,6 +25,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "hw-tree.h" #include "hw-device.h" #include "hw-ports.h" +#include "elf32-m68hc1x.h" #ifndef MONITOR_BASE # define MONITOR_BASE (0x0C000) @@ -194,8 +195,17 @@ sim_hw_configure (SIM_DESC sd) sim_do_commandf (sd, "memory region 0x000@%d,0x8000", M6811_RAM_LEVEL); sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F"); + if (cpu->bank_start < cpu->bank_end) + { + sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000", + cpu->bank_virtual, M6811_RAM_LEVEL); + sim_hw_parse (sd, "/m68hc11/use_bank 1"); + } } - + if (cpu->cpu_start_mode) + { + sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode); + } if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0) { sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5"); @@ -242,14 +252,16 @@ sim_hw_configure (SIM_DESC sd) { /* Allocate core external memory. */ sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx", - 0xC000, M6811_RAM_LEVEL, 0x4000); + 0x8000, M6811_RAM_LEVEL, 0x8000); sim_do_commandf (sd, "memory region 0x000@%d,0x8000", M6811_RAM_LEVEL); - sim_do_commandf (sd, "memory region 0x01000000@%d,0x100000", - M6811_RAM_LEVEL); - + if (cpu->bank_start < cpu->bank_end) + { + sim_do_commandf (sd, "memory region 0x%lx@%d,0x100000", + cpu->bank_virtual, M6811_RAM_LEVEL); + sim_hw_parse (sd, "/m68hc12/use_bank 1"); + } sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF"); - sim_hw_parse (sd, "/m68hc12/use_bank 1"); } if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg")) @@ -294,19 +306,77 @@ sim_hw_configure (SIM_DESC sd) return 1; } +/* Get the memory bank parameters by looking at the global symbols + defined by the linker. */ static int -sim_prepare_for_program (SIM_DESC sd, struct bfd* abfd) +sim_get_bank_parameters (SIM_DESC sd, bfd* abfd) { sim_cpu *cpu; + long symsize; + long symbol_count, i; + unsigned size; + asymbol** asymbols; + asymbol** current; cpu = STATE_CPU (sd, 0); - if (!sim_hw_configure (sd)) - return SIM_RC_FAIL; + symsize = bfd_get_symtab_upper_bound (abfd); + if (symsize < 0) + { + sim_io_eprintf (sd, "Cannot read symbols of program"); + return 0; + } + asymbols = (asymbol **) xmalloc (symsize); + symbol_count = bfd_canonicalize_symtab (abfd, asymbols); + if (symbol_count < 0) + { + sim_io_eprintf (sd, "Cannot read symbols of program"); + return 0; + } + + size = 0; + for (i = 0, current = asymbols; i < symbol_count; i++, current++) + { + const char* name = bfd_asymbol_name (*current); + + if (strcmp (name, BFD_M68HC11_BANK_START_NAME) == 0) + { + cpu->bank_start = bfd_asymbol_value (*current); + } + else if (strcmp (name, BFD_M68HC11_BANK_SIZE_NAME) == 0) + { + size = bfd_asymbol_value (*current); + } + else if (strcmp (name, BFD_M68HC11_BANK_VIRTUAL_NAME) == 0) + { + cpu->bank_virtual = bfd_asymbol_value (*current); + } + } + free (asymbols); + + cpu->bank_end = cpu->bank_start + size; + cpu->bank_shift = 0; + for (; size > 1; size >>= 1) + cpu->bank_shift++; + + return 0; +} + +static int +sim_prepare_for_program (SIM_DESC sd, bfd* abfd) +{ + sim_cpu *cpu; + int elf_flags = 0; + + cpu = STATE_CPU (sd, 0); if (abfd != NULL) { asection *s; + + if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) + elf_flags = elf_elfheader (abfd)->e_flags; + cpu->cpu_elf_start = bfd_get_start_address (abfd); /* See if any section sets the reset address */ cpu->cpu_use_elf_start = 1; @@ -331,8 +401,17 @@ sim_prepare_for_program (SIM_DESC sd, struct bfd* abfd) } } } + + if (elf_flags & E_M68HC12_BANKS) + { + if (sim_get_bank_parameters (sd, abfd) != 0) + sim_io_eprintf (sd, "Memory bank parameters are not initialized\n"); + } } + if (!sim_hw_configure (sd)) + return SIM_RC_FAIL; + /* reset all state information */ sim_board_reset (sd); @@ -341,7 +420,7 @@ sim_prepare_for_program (SIM_DESC sd, struct bfd* abfd) SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *callback, - struct bfd *abfd, char **argv) + bfd *abfd, char **argv) { SIM_DESC sd; sim_cpu *cpu; @@ -398,8 +477,11 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, free_state (sd); return 0; } - - sim_hw_configure (sd); + if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } /* Fudge our descriptor. */ return sd; diff --git a/sim/m68hc11/interrupts.c b/sim/m68hc11/interrupts.c index 5844c74..b466d69 100644 --- a/sim/m68hc11/interrupts.c +++ b/sim/m68hc11/interrupts.c @@ -1,6 +1,6 @@ /* interrupts.c -- 68HC11 Interrupts Emulation - Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. @@ -166,6 +166,20 @@ interrupts_reset (struct interrupts *interrupts) memset (interrupts->interrupts, 0, sizeof (interrupts->interrupts)); + + /* In bootstrap mode, initialize the vector table to point + to the RAM location. */ + if (interrupts->cpu->cpu_mode == M6811_SMOD) + { + bfd_vma addr = interrupts->vectors_addr; + uint16 vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1); + for (i = 0; i < M6811_INT_NUMBER; i++) + { + memory_write16 (interrupts->cpu, addr, vector); + addr += 2; + vector += 3; + } + } } static int @@ -517,7 +531,7 @@ interrupts_raise (struct interrupts *interrupts, enum M6811_INT number) void interrupts_info (SIM_DESC sd, struct interrupts *interrupts) { - signed64 t; + signed64 t, prev_interrupt; int i; sim_io_printf (sd, "Interrupts Info:\n"); @@ -533,21 +547,25 @@ interrupts_info (SIM_DESC sd, struct interrupts *interrupts) interrupts->max_mask_cycles = t; sim_io_printf (sd, " Current interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); } t = interrupts->min_mask_cycles == CYCLES_MAX ? interrupts->max_mask_cycles : interrupts->min_mask_cycles; sim_io_printf (sd, " Shortest interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); t = interrupts->max_mask_cycles; sim_io_printf (sd, " Longest interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); t = interrupts->last_mask_cycles; sim_io_printf (sd, " Last interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); if (interrupts->xirq_start_mask_cycle >= 0) { @@ -558,22 +576,26 @@ interrupts_info (SIM_DESC sd, struct interrupts *interrupts) interrupts->xirq_max_mask_cycles = t; sim_io_printf (sd, " XIRQ Current interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); } t = interrupts->xirq_min_mask_cycles == CYCLES_MAX ? interrupts->xirq_max_mask_cycles : interrupts->xirq_min_mask_cycles; sim_io_printf (sd, " XIRQ Min interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); t = interrupts->xirq_max_mask_cycles; sim_io_printf (sd, " XIRQ Max interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); t = interrupts->xirq_last_mask_cycles; sim_io_printf (sd, " XIRQ Last interrupts masked sequence: %s\n", - cycle_to_string (interrupts->cpu, t)); + cycle_to_string (interrupts->cpu, t, + PRINT_TIME | PRINT_CYCLE)); if (interrupts->pending_mask) { @@ -590,6 +612,9 @@ interrupts_info (SIM_DESC sd, struct interrupts *interrupts) sim_io_printf (sd, "\n"); } + prev_interrupt = 0; + sim_io_printf (sd, "N Interrupt Cycle Taken Latency" + " Delta between interrupts\n"); for (i = 0; i < MAX_INT_HISTORY; i++) { int which; @@ -604,10 +629,18 @@ interrupts_info (SIM_DESC sd, struct interrupts *interrupts) break; dt = h->taken_cycle - h->raised_cycle; - sim_io_printf (sd, "%2d %-10.10s %30.30s ", i, + sim_io_printf (sd, "%2d %-9.9s %15.15s ", i, interrupt_names[h->type], - cycle_to_string (interrupts->cpu, h->taken_cycle)); - sim_io_printf (sd, "%s\n", - cycle_to_string (interrupts->cpu, dt)); + cycle_to_string (interrupts->cpu, h->taken_cycle, 0)); + sim_io_printf (sd, "%15.15s", + cycle_to_string (interrupts->cpu, dt, 0)); + if (prev_interrupt) + { + dt = prev_interrupt - h->taken_cycle; + sim_io_printf (sd, " %s", + cycle_to_string (interrupts->cpu, dt, PRINT_TIME)); + } + sim_io_printf (sd, "\n"); + prev_interrupt = h->taken_cycle; } } diff --git a/sim/m68hc11/m68hc11_sim.c b/sim/m68hc11/m68hc11_sim.c index fe5985f..444147b 100644 --- a/sim/m68hc11/m68hc11_sim.c +++ b/sim/m68hc11/m68hc11_sim.c @@ -1,5 +1,5 @@ /* m6811_cpu.c -- 68HC11&68HC12 CPU Emulation - Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. @@ -27,6 +27,7 @@ enum { OPTION_CPU_RESET = OPTION_START, OPTION_EMUL_OS, OPTION_CPU_CONFIG, + OPTION_CPU_BOOTSTRAP, OPTION_CPU_MODE }; @@ -46,6 +47,10 @@ static const OPTION cpu_options[] = '\0', NULL, "Specify the initial CPU configuration register", cpu_option_handler }, + { {"bootstrap", no_argument, NULL, OPTION_CPU_BOOTSTRAP }, + '\0', NULL, "Start the processing in bootstrap mode", + cpu_option_handler }, + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } }; @@ -77,7 +82,11 @@ cpu_option_handler (SIM_DESC sd, sim_cpu *cpu, else cpu->cpu_use_local_config = 0; break; - + + case OPTION_CPU_BOOTSTRAP: + cpu->cpu_start_mode = "bootstrap"; + break; + case OPTION_CPU_MODE: break; } @@ -464,6 +473,9 @@ cpu_initialize (SIM_DESC sd, sim_cpu *cpu) cpu->cpu_use_elf_start = 0; cpu->cpu_elf_start = 0; cpu->cpu_use_local_config = 0; + cpu->bank_start = 0; + cpu->bank_end = 0; + cpu->bank_shift = 0; cpu->cpu_config = M6811_NOSEC | M6811_NOCOP | M6811_ROMON | M6811_EEON; interrupts_initialize (sd, cpu); @@ -582,6 +594,15 @@ print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc, } void +print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc, + uint16 val, uint16 addr) +{ + sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%04x ", name, addr, val); + if (desc) + print_io_reg_desc (sd, desc, val, 0); +} + +void cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val) { cpu_set_ccr_V (proc, 0); @@ -1037,7 +1058,8 @@ cpu_info (SIM_DESC sd, sim_cpu *cpu) { sim_io_printf (sd, "CPU info:\n"); sim_io_printf (sd, " Absolute cycle: %s\n", - cycle_to_string (cpu, cpu->cpu_absolute_cycle)); + cycle_to_string (cpu, cpu->cpu_absolute_cycle, + PRINT_TIME | PRINT_CYCLE)); sim_io_printf (sd, " Syscall emulation: %s\n", cpu->cpu_emul_syscall ? "yes, via 0xcd <n>" : "no"); diff --git a/sim/m68hc11/sim-main.h b/sim/m68hc11/sim-main.h index c8933a0..a4bd3a6 100644 --- a/sim/m68hc11/sim-main.h +++ b/sim/m68hc11/sim-main.h @@ -1,5 +1,5 @@ /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12 - Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, the GNU debugger. @@ -79,8 +79,8 @@ enum cpu_type #define A_REGNUM 5 #define B_REGNUM 6 #define PSW_REGNUM 7 -#define Z_REGNUM 8 -#define PAGE_REGNUM 9 +#define PAGE_REGNUM 8 +#define Z_REGNUM 9 typedef struct m6811_regs { unsigned short d; @@ -108,6 +108,8 @@ extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val, int mode); extern void print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc, uint8 val, uint16 addr); +extern void print_io_word (SIM_DESC sd, const char *name, + io_reg_desc *desc, uint16 val, uint16 addr); /* List of special 68HC11&68HC12 instructions that are not handled by the @@ -198,6 +200,7 @@ struct _sim_cpu { /* The mode in which the CPU is configured (MODA and MODB pins). */ unsigned int cpu_mode; + const char* cpu_start_mode; /* The cpu being configured. */ enum cpu_type cpu_type; @@ -208,6 +211,14 @@ struct _sim_cpu { uint8 ios[MAX_PORTS]; + /* Memory bank parameters which describe how the memory bank window + is mapped in memory and how to convert it in virtual address. */ + uint16 bank_start; + uint16 bank_end; + address_word bank_virtual; + unsigned bank_shift; + + struct hw *hw_cpu; /* ... base type ... */ @@ -235,7 +246,7 @@ struct _sim_cpu { #define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp) #define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF) #define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF) -#define cpu_get_page(PROC) (PROC->cpu_regs.page) +#define cpu_get_page(PROC) ((PROC)->cpu_regs.page) /* 68HC12 specific and Motorola internal registers. */ #define cpu_get_tmp3(PROC) (0) @@ -244,7 +255,7 @@ struct _sim_cpu { #define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL)) #define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL)) #define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL)) -#define cpu_set_page(PROC,VAL) ((PROC->cpu_regs.page) = (VAL)) +#define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL)) /* 68HC12 specific and Motorola internal registers. */ #define cpu_set_tmp3(PROC,VAL) (0) @@ -295,9 +306,10 @@ extern void cpu_memory_exception (struct _sim_cpu *proc, inline address_word phys_to_virt (sim_cpu *cpu, address_word addr) { - if (addr >= 0x8000 && addr < 0xc000) - return ((address_word) (addr) - 0x8000) - + (((address_word) cpu->cpu_regs.page) << 14) + 0x01000000; + if (addr >= cpu->bank_start && addr < cpu->bank_end) + return ((address_word) (addr - cpu->bank_start) + + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift) + + cpu->bank_virtual); else return (address_word) (addr); } @@ -580,7 +592,9 @@ extern void sim_set_profile (int n); extern void sim_set_profile_size (int n); extern void sim_board_reset (SIM_DESC sd); -extern const char *cycle_to_string (sim_cpu *cpu, signed64 t); +#define PRINT_TIME 0x01 +#define PRINT_CYCLE 0x02 +extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags); #endif diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 9a5b602..5602ce8 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,12 @@ +2003-08-28 Andrew Cagney <cagney@redhat.com> + + * dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to + "long". + (read_status_reg): Cast "serial_reg" to "long". + * dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to + "long". + (do_counter6_event, write_mode_reg, write_tm6md): Ditto. + 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_open, sim_create_inferior, sim_open) diff --git a/sim/mn10300/dv-mn103ser.c b/sim/mn10300/dv-mn103ser.c index 7f20ed1..bba20c9 100644 --- a/sim/mn10300/dv-mn103ser.c +++ b/sim/mn10300/dv-mn103ser.c @@ -240,7 +240,7 @@ do_polling_event (struct hw *me, void *data) { struct mn103ser *serial = hw_data(me); - int serial_reg = (int) data; + long serial_reg = (long) data; char c; int count; @@ -421,7 +421,7 @@ read_status_reg (struct hw *me, serial->device[serial_reg].event = hw_event_queue_schedule (me, 1000, do_polling_event, - (void *)serial_reg); + (void *) (long) serial_reg); } if ( nr_bytes == 1 ) diff --git a/sim/mn10300/dv-mn103tim.c b/sim/mn10300/dv-mn103tim.c index 9b1e0d2..a6272d8 100644 --- a/sim/mn10300/dv-mn103tim.c +++ b/sim/mn10300/dv-mn103tim.c @@ -568,7 +568,7 @@ do_counter_event (struct hw *me, void *data) { struct mn103tim *timers = hw_data(me); - int timer_nr = (int) data; + long timer_nr = (long) data; int next_timer; /* Check if counting is still enabled. */ @@ -609,7 +609,7 @@ do_counter6_event (struct hw *me, void *data) { struct mn103tim *timers = hw_data(me); - int timer_nr = (int) data; + long timer_nr = (long) data; int next_timer; /* Check if counting is still enabled. */ @@ -705,7 +705,7 @@ write_base_reg (struct hw *me, static void write_mode_reg (struct hw *me, struct mn103tim *timers, - int timer_nr, + long timer_nr, const void *source, unsigned nr_bytes) /* for timers 0 to 5 */ @@ -716,7 +716,8 @@ write_mode_reg (struct hw *me, if ( nr_bytes != 1 ) { - hw_abort (me, "bad write size of %d bytes to TM%dMD.", nr_bytes, timer_nr); + hw_abort (me, "bad write size of %d bytes to TM%ldMD.", nr_bytes, + timer_nr); } mode_val = *(unsigned8 *)source; @@ -742,7 +743,7 @@ write_mode_reg (struct hw *me, { if ( timer_nr == 0 || timer_nr == 4 ) { - hw_abort(me, "Timer %d cannot be cascaded.", timer_nr); + hw_abort(me, "Timer %ld cannot be cascaded.", timer_nr); } } else @@ -839,7 +840,7 @@ write_tm6md (struct hw *me, { unsigned8 mode_val0 = 0x00, mode_val1 = 0x00; unsigned32 div_ratio; - int timer_nr = 6; + long timer_nr = 6; unsigned_word offset = address - timers->block[0].base; diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index b34adb5..7ab1394 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,3 +1,13 @@ +2003-08-11 Shrinivas Atre <shrinivasa@KPITCummins.com> + * sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and + correction for MAC.W handler + * sim/sh/interp.c ( macl ): New Function. Implementation of + MAC.L handler. + +2003-08-07 Michael Snyder <msnyder@redhat.com> + + * gencode.c (expand_ppi_code): Comment spelling fix. + 2003-07-25 Michael Snyder <msnyder@redhat.com> * gencode.c (pshl): Change < to <= (shift by 16 is allowed). diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index d078fc6..a4a1c2d 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -580,12 +580,11 @@ op tab[] = }, { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111", - "trap (255, R0, PC, memory, maskl, maskw, endianw);", - "/* FIXME: mac.l support */", + "macl(&R0,memory,n,m);", }, { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111", - "macw(R0,memory,n,m,endianw);", + "macw(&R0,memory,n,m,endianw);", }, { "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....", @@ -2324,7 +2323,7 @@ gendefines () static int ppi_index; -/* Take an ppi code, expand all varying fields in it and fill all the +/* Take a ppi code, expand all varying fields in it and fill all the right entries in 'table' with the opcode index. */ static void diff --git a/sim/sh/interp.c b/sim/sh/interp.c index 887b7a6..91899f4 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -169,6 +169,7 @@ static char **prog_argv; #if 1 static int maskw = 0; +static int maskl = 0; #endif static SIM_OPEN_KIND sim_kind; @@ -651,6 +652,7 @@ rbat_fast (memory, x, maskb) #define RUWAT(x) (RWAT(x) & 0xffff) #define RSWAT(x) ((short)(RWAT(x))) +#define RSLAT(x) ((long)(RLAT(x))) #define RSBAT(x) (SEXT(RBAT(x))) #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl))) @@ -1348,6 +1350,56 @@ macw (regs, memory, n, m, endianw) MACL = sum; } +static void +macl (regs, memory, n, m) + int *regs; + unsigned char *memory; + int m, n; +{ + long tempm, tempn; + long prod, macl, mach, sum; + long long ans,ansl,ansh,t; + unsigned long long high,low,combine; + union mac64 + { + long m[2]; /* mach and macl*/ + long long m64; /* 64 bit MAC */ + }mac64; + + tempm = RSLAT(regs[m]); + regs[m] += 4; + + tempn = RSLAT(regs[n]); + regs[n] += 4; + + mach = MACH; + macl = MACL; + + mac64.m[0] = macl; + mac64.m[1] = mach; + + ans = (long long)tempm * (long long)tempn; /* Multiply 32bit * 32bit */ + + mac64.m64 += ans; /* Accumulate 64bit + 64 bit */ + + macl = mac64.m[0]; + mach = mac64.m[1]; + + if (S) /* Store only 48 bits of the result */ + { + if (mach < 0) /* Result is negative */ + { + mach = mach & 0x0000ffff; /* Mask higher 16 bits */ + mach |= 0xffff8000; /* Sign extend higher 16 bits */ + } + else + mach = mach & 0x00007fff; /* Postive Result */ + } + + MACL = macl; + MACH = mach; +} + static struct loop_bounds get_loop_bounds (rs, re, memory, mem_end, maskw, endianw) int rs, re; diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index 301fe81..ec6b7e3 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,31 @@ +2003-09-11 Michael Snyder <msnyder@redhat.com> + + * sim/testsuite/sim/frv/movgs.cgs: Change lcr to spr[273], + which according to the comments seems to be the intent. + +2003-09-09 Dave Brolley <brolley@redhat.com> + + * sim/frv/maddaccs.cgs: move to fr400 subdirectory. + * sim/frv/msubaccs.cgs: move to fr400 subdirectory. + * sim/frv/masaccs.cgs: move to fr400 subdirectory. + +2003-09-03 Michael Snyder <msnyder@redhat.com> + + * sim/frv/fr500/mclracc.cgs: Change mach to 'all', to be + consistent with other tests in the directory. + +2003-09-03 Michael Snyder <msnyder@redhat.com> + + * sim/frv/interrupts/Ipipe-fr400.cgs: New file. + * sim/frv/interrupts/Ipipe-fr500.cgs: New file. + * sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above). + +2003-08-20 Michael Snyder <msnyder@redhat.com> + On behalf of Dave Brolley + + * sim/frv: New testsuite. + * frv-elf: New testsuite. + 2003-07-09 Michael Snyder <msnyder@redhat.com> * sim/sh: New directory. Tests for Renesas sh family. diff --git a/sim/testsuite/lib/sim-defs.exp b/sim/testsuite/lib/sim-defs.exp index 42374e0..017fcef 100644 --- a/sim/testsuite/lib/sim-defs.exp +++ b/sim/testsuite/lib/sim-defs.exp @@ -331,20 +331,20 @@ proc slurp_options { file } { # whitespace is ignored anywhere except within the options list; # option names are alphabetic only set pat "^#${ws}(\[a-zA-Z\]*)\\(?(\[^):\]*)\\)?$ws:${ws}(.*)$ws\$" - # Allow comment as first line of file. - set firstline 1 + # Allow arbitrary lines until the first option is seen. + set seen_opt 0 while { [gets $f line] != -1 } { set line [string trim $line] # Whitespace here is space-tab. if [regexp $pat $line xxx opt_name opt_machs opt_val] { # match! lappend opt_array [list $opt_name $opt_machs $opt_val] + set seen_opt 1 } else { - if { ! $firstline } { + if { $seen_opt } { break } } - set firstline 0 } close $f return $opt_array diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index 78fe7e2..6f528ef 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,3 +1,15 @@ +2003-09-05 Andrew Cagney <cagney@redhat.com> + Nick Clifton <nickc@redhat.com> + + * interp.c (sim_open): Accept bfd_mach_v850e1. + * v850-dc: Add entry for v850e1. + * v850.igen: Add support for v850e1. + Add code for DBTRAP and DBRET instructions. + (dbtrap): Create a separate v850e1 specific instruction. + Only generate a trap if the target is not the v850e1. + Otherwise treat it as a special kind of branch. + (break): Mark as v850/v850e specific. + 2003-05-16 Ian Lance Taylor <ian@airs.com> * Makefile.in (SHELL): Make sure this is defined. diff --git a/sim/v850/interp.c b/sim/v850/interp.c index 62a4616..1ca248c 100644 --- a/sim/v850/interp.c +++ b/sim/v850/interp.c @@ -277,6 +277,7 @@ sim_open (kind, cb, abfd, argv) { case bfd_mach_v850: case bfd_mach_v850e: + case bfd_mach_v850e1: STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT | PSW_CY | PSW_OV | PSW_S | PSW_Z); break; diff --git a/sim/v850/v850-dc b/sim/v850/v850-dc index 1d061ec..29fa127 100644 --- a/sim/v850/v850-dc +++ b/sim/v850/v850-dc @@ -11,6 +11,7 @@ switch,combine : 4 : 0 : : : : 1 : V,VII : switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e + switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e1 # for opcode 63, 127, 1087 et.al. diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 3f14957..4796ea5 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -12,6 +12,8 @@ :option:::multi-sim:true :model:::v850e:v850e: +:option:::multi-sim:true +:model:::v850e1:v850e1: // Cache macros @@ -156,6 +158,7 @@ ddddd,1011,ddd,cccc:III:::Bcond // BSH rrrrr,11111100000 + wwwww,01101000010:XII:::bsh *v850e +*v850e1 "bsh r<reg2>, r<reg3>" { unsigned32 value; @@ -178,6 +181,7 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh // BSW rrrrr,11111100000 + wwwww,01101000000:XII:::bsw *v850e +*v850e1 "bsw r<reg2>, r<reg3>" { #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) @@ -203,6 +207,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw // CALLT 0000001000,iiiiii:II:::callt *v850e +*v850e1 "callt <imm6>" { unsigned32 adr; @@ -225,6 +230,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 *v850e +*v850e1 "clr1 r<reg2>, [r<reg1>]" { COMPAT_2 (OP_E407E0 ()); @@ -234,6 +240,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 // CTRET 0000011111100000 + 0000000101000100:X:::ctret *v850e +*v850e1 "ctret" { nia = (CTPC & ~1); @@ -244,6 +251,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 // CMOV rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov *v850e +*v850e1 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>" { int cond = condition_met (cccc); @@ -254,6 +262,7 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov *v850e +*v850e1 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>" { int cond = condition_met (cccc); @@ -291,6 +300,7 @@ rrrrr,010011,iiiii:II:::cmp // "dispose <imm5>, <list12>" 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose *v850e +*v850e1 "dispose <imm5>, <list12>":RRRRR == 0 "dispose <imm5>, <list12>, [reg1]" { @@ -322,6 +332,7 @@ rrrrr,010011,iiiii:II:::cmp // DIV rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div *v850e +*v850e1 "div r<reg1>, r<reg2>, r<reg3>" { COMPAT_2 (OP_2C007E0 ()); @@ -378,6 +389,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh *v850e +*v850e1 "divh r<reg1>, r<reg2>, r<reg3>" { COMPAT_2 (OP_28007E0 ()); @@ -387,6 +399,7 @@ rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh // DIVHU rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu *v850e +*v850e1 "divhu r<reg1>, r<reg2>, r<reg3>" { COMPAT_2 (OP_28207E0 ()); @@ -396,6 +409,7 @@ rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu // DIVU rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu *v850e +*v850e1 "divu r<reg1>, r<reg2>, r<reg3>" { COMPAT_2 (OP_2C207E0 ()); @@ -423,6 +437,7 @@ rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu // HSW rrrrr,11111100000 + wwwww,01101000100:XII:::hsw *v850e +*v850e1 "hsw r<reg2>, r<reg3>" { unsigned32 value; @@ -497,6 +512,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu *v850e +*v850e1 "ld.bu <disp16>[r<reg1>], r<reg2>" { COMPAT_2 (OP_10780 ()); @@ -504,6 +520,7 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu *v850e +*v850e1 "ld.hu <disp16>[r<reg1>], r<reg2>" { COMPAT_2 (OP_107E0 ()); @@ -544,6 +561,7 @@ rrrrr!0,010000,iiiii:II:::mov 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov *v850e +*v850e1 "mov <imm32>, r<reg1>" { SAVE_2; @@ -577,6 +595,7 @@ rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi // MUL rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul *v850e +*v850e1 "mul r<reg1>, r<reg2>, r<reg3>" { COMPAT_2 (OP_22007E0 ()); @@ -584,6 +603,7 @@ rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul *v850e +*v850e1 "mul <imm9>, r<reg2>, r<reg3>" { COMPAT_2 (OP_24007E0 ()); @@ -617,6 +637,7 @@ rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi // MULU rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu *v850e +*v850e1 "mulu r<reg1>, r<reg2>, r<reg3>" { COMPAT_2 (OP_22207E0 ()); @@ -624,6 +645,7 @@ rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu *v850e +*v850e1 "mulu <imm9>, r<reg2>, r<reg3>" { COMPAT_2 (OP_24207E0 ()); @@ -658,6 +680,7 @@ rrrrr,000001,RRRRR:I:::not rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 *v850e +*v850e1 "not1 r<reg2>, r<reg1>" { COMPAT_2 (OP_E207E0 ()); @@ -686,6 +709,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori // PREPARE 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare *v850e +*v850e1 "prepare <list12>, <imm5>" { int i; @@ -710,6 +734,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 *v850e +*v850e1 "prepare <list12>, <imm5>, sp" { COMPAT_2 (OP_30780 ()); @@ -717,6 +742,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 *v850e +*v850e1 "prepare <list12>, <imm5>, <uimm16>" { COMPAT_2 (OP_B0780 ()); @@ -724,6 +750,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 *v850e +*v850e1 "prepare <list12>, <imm5>, <uimm16>" { COMPAT_2 (OP_130780 ()); @@ -731,6 +758,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 *v850e +*v850e1 "prepare <list12>, <imm5>, <uimm32>" { COMPAT_2 (OP_1B0780 ()); @@ -780,6 +808,7 @@ rrrrr,010101,iiiii:II:::sar // SASF rrrrr,1111110,cccc + 0000001000000000:IX:::sasf *v850e +*v850e1 "sasf %s<cccc>, r<reg2>" { COMPAT_2 (OP_20007E0 ()); @@ -848,6 +877,7 @@ rrrrr,1111110,cccc + 0000000000000000:IX:::setf rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 *v850e +*v850e1 "set1 r<reg2>, [r<reg1>]" { COMPAT_2 (OP_E007E0 ()); @@ -935,6 +965,7 @@ rrrrr,1010,dddddd,0:IV:::sld.w rrrrr!0,0000110,dddd:IV:::sld.bu *v850e +*v850e1 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US) "sld.bu <disp4>[ep], r<reg2>" { @@ -955,6 +986,7 @@ rrrrr!0,0000110,dddd:IV:::sld.bu rrrrr!0,0000111,dddd:IV:::sld.hu *v850e +*v850e1 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US) "sld.hu <disp5>[ep], r<reg2>" { @@ -1037,6 +1069,7 @@ rrrrr,001100,RRRRR:I:::subr // SWITCH 00000000010,RRRRR:I:::switch *v850e +*v850e1 "switch r<reg1>" { unsigned long adr; @@ -1050,6 +1083,7 @@ rrrrr,001100,RRRRR:I:::subr // SXB 00000000101,RRRRR:I:::sxb *v850e +*v850e1 "sxb r<reg1>" { TRACE_ALU_INPUT1 (GR[reg1]); @@ -1060,6 +1094,7 @@ rrrrr,001100,RRRRR:I:::subr // SXH 00000000111,RRRRR:I:::sxh *v850e +*v850e1 "sxh r<reg1>" { TRACE_ALU_INPUT1 (GR[reg1]); @@ -1090,6 +1125,7 @@ rrrrr,001011,RRRRR:I:::tst rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 *v850e +*v850e1 "tst1 r<reg2>, [r<reg1>]" { COMPAT_2 (OP_E607E0 ()); @@ -1112,6 +1148,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori // ZXB 00000000100,RRRRR:I:::zxb *v850e +*v850e1 "zxb r<reg1>" { TRACE_ALU_INPUT1 (GR[reg1]); @@ -1122,6 +1159,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori // ZXH 00000000110,RRRRR:I:::zxh *v850e +*v850e1 "zxh r<reg1>" { TRACE_ALU_INPUT1 (GR[reg1]); @@ -1132,12 +1170,36 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori // Right field must be zero so that it doesn't clash with DIVH // Left field must be non-zero so that it doesn't clash with SWITCH 11111,000010,00000:I:::break +*v850 +*v850e { sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); } +11111,000010,00000:I:::dbtrap +*v850e1 +"dbtrap" +{ + DBPC = cia + 2; + DBPSW = PSW; + PSW = PSW | (PSW_NP | PSW_EP | PSW_ID); + PC = 0x00000060; + nia = 0x00000060; + TRACE_BRANCH0 (); +} + // New breakpoint: 0x7E0 0x7E0 00000,111111,00000 + 00000,11111,100000:X:::ilgop { sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); } + +// Return from debug trap: 0x146007e0 +0000011111100000 + 0000000101000110:X:::dbret +*v850e1 +"dbret" +{ + nia = DBPC; + PSW = DBPSW; + TRACE_BRANCH1 (PSW); +} |