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-rw-r--r--sim/testsuite/sim/aarch64/ChangeLog9
-rw-r--r--sim/testsuite/sim/aarch64/fcvtz.s1
-rw-r--r--sim/testsuite/sim/aarch64/fstur.s1
-rw-r--r--sim/testsuite/sim/aarch64/ldn_multiple.s136
-rw-r--r--sim/testsuite/sim/aarch64/ldn_single.s2
-rw-r--r--sim/testsuite/sim/aarch64/ldnr.s2
-rw-r--r--sim/testsuite/sim/aarch64/mla.s2
-rw-r--r--sim/testsuite/sim/aarch64/mls.s2
-rw-r--r--sim/testsuite/sim/aarch64/stn_multiple.s171
-rw-r--r--sim/testsuite/sim/aarch64/stn_single.s24
-rw-r--r--sim/testsuite/sim/aarch64/sumulh.s3
-rw-r--r--sim/testsuite/sim/aarch64/uzp.s2
12 files changed, 341 insertions, 14 deletions
diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog
index cf0da6d..f4671da 100644
--- a/sim/testsuite/sim/aarch64/ChangeLog
+++ b/sim/testsuite/sim/aarch64/ChangeLog
@@ -1,3 +1,12 @@
+2017-04-22 Jim Wilson <jim.wilson@linaro.org>
+
+ * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
+ data.
+ * sumulh.s: Delete unnecessary data alignment.
+ * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
+ arguments to match change.
+ * ldn_multiple.s, stn_multiple.s: New.
+
2017-04-08 Jim Wilson <jim.wilson@linaro.org>
* fcvtl.s: New.
diff --git a/sim/testsuite/sim/aarch64/fcvtz.s b/sim/testsuite/sim/aarch64/fcvtz.s
index 9bb6f9b..311fc2e 100644
--- a/sim/testsuite/sim/aarch64/fcvtz.s
+++ b/sim/testsuite/sim/aarch64/fcvtz.s
@@ -8,6 +8,7 @@
# For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX.
.data
+ .align 4
fm1p5:
.word 3217031168
fimax:
diff --git a/sim/testsuite/sim/aarch64/fstur.s b/sim/testsuite/sim/aarch64/fstur.s
index 2206ae5..80e5c67 100644
--- a/sim/testsuite/sim/aarch64/fstur.s
+++ b/sim/testsuite/sim/aarch64/fstur.s
@@ -8,6 +8,7 @@
.include "testutils.inc"
.data
+ .align 4
fm1:
.word 3212836864
fmax:
diff --git a/sim/testsuite/sim/aarch64/ldn_multiple.s b/sim/testsuite/sim/aarch64/ldn_multiple.s
new file mode 100644
index 0000000..285ef7e
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/ldn_multiple.s
@@ -0,0 +1,136 @@
+# mach: aarch64
+
+# Check the load multiple structure instructions: ld1, ld2, ld3, ld4.
+# Check the addressing modes: no offset, post-index immediate offset,
+# post-index register offset.
+
+.include "testutils.inc"
+
+ .data
+ .align 4
+input:
+ .word 0x04030201
+ .word 0x08070605
+ .word 0x0c0b0a09
+ .word 0x100f0e0d
+ .word 0xfcfdfeff
+ .word 0xf8f9fafb
+ .word 0xf4f5f6f7
+ .word 0xf0f1f2f3
+
+ start
+ adrp x0, input
+ add x0, x0, :lo12:input
+
+ mov x2, x0
+ mov x3, #16
+ ld1 {v0.16b}, [x2], 16
+ ld1 {v1.8h}, [x2], x3
+ addv b4, v0.16b
+ addv b5, v1.16b
+ mov x4, v4.d[0]
+ cmp x4, #136
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #120
+ bne .Lfailure
+
+ mov x2, x0
+ mov x3, #16
+ ld2 {v0.8b, v1.8b}, [x2], x3
+ ld2 {v2.4h, v3.4h}, [x2], 16
+ addv b4, v0.8b
+ addv b5, v1.8b
+ addv b6, v2.8b
+ addv b7, v3.8b
+ mov x4, v4.d[0]
+ cmp x4, #64
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #72
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #196
+ bne .Lfailure
+ mov x7, v7.d[0]
+ cmp x7, #180
+ bne .Lfailure
+
+ mov x2, x0
+ ld3 {v0.2s, v1.2s, v2.2s}, [x2]
+ addv b4, v0.8b
+ addv b5, v1.8b
+ addv b6, v2.8b
+ mov x4, v4.d[0]
+ cmp x4, #68
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #16
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #16
+ bne .Lfailure
+
+ mov x2, x0
+ ld4 {v0.4h, v1.4h, v2.4h, v3.4h}, [x2]
+ addv b4, v0.8b
+ addv b5, v1.8b
+ addv b6, v2.8b
+ addv b7, v3.8b
+ mov x4, v4.d[0]
+ cmp x4, #0
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #0
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #0
+ bne .Lfailure
+ mov x7, v7.d[0]
+ cmp x7, #0
+ bne .Lfailure
+
+ mov x2, x0
+ ld1 {v0.4s, v1.4s}, [x2]
+ addv b4, v0.16b
+ addv b5, v1.16b
+ mov x4, v4.d[0]
+ cmp x4, #136
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #120
+ bne .Lfailure
+
+ mov x2, x0
+ ld1 {v0.1d, v1.1d, v2.1d}, [x2]
+ addv b4, v0.8b
+ addv b5, v1.8b
+ addv b6, v2.8b
+ mov x4, v4.d[0]
+ cmp x4, #36
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #100
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #220
+ bne .Lfailure
+
+ mov x2, x0
+ ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x2]
+ addv b4, v0.8b
+ addv b5, v1.8b
+ addv b6, v2.8b
+ mov x4, v4.d[0]
+ cmp x4, #36
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #100
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #220
+ bne .Lfailure
+
+ pass
+.Lfailure:
+ fail
diff --git a/sim/testsuite/sim/aarch64/ldn_single.s b/sim/testsuite/sim/aarch64/ldn_single.s
index 4c460fb..9681520 100644
--- a/sim/testsuite/sim/aarch64/ldn_single.s
+++ b/sim/testsuite/sim/aarch64/ldn_single.s
@@ -7,6 +7,8 @@
.include "testutils.inc"
+ .data
+ .align 4
input:
.word 0x04030201
.word 0x08070605
diff --git a/sim/testsuite/sim/aarch64/ldnr.s b/sim/testsuite/sim/aarch64/ldnr.s
index a4bfffa..7126c46 100644
--- a/sim/testsuite/sim/aarch64/ldnr.s
+++ b/sim/testsuite/sim/aarch64/ldnr.s
@@ -7,6 +7,8 @@
.include "testutils.inc"
+ .data
+ .align 4
input:
.word 0x04030201
.word 0x08070605
diff --git a/sim/testsuite/sim/aarch64/mla.s b/sim/testsuite/sim/aarch64/mla.s
index e0065e7..e3ea836 100644
--- a/sim/testsuite/sim/aarch64/mla.s
+++ b/sim/testsuite/sim/aarch64/mla.s
@@ -4,6 +4,8 @@
.include "testutils.inc"
+ .data
+ .align 4
input:
.word 0x04030201
.word 0x08070605
diff --git a/sim/testsuite/sim/aarch64/mls.s b/sim/testsuite/sim/aarch64/mls.s
index a34a1aa..5c9e225 100644
--- a/sim/testsuite/sim/aarch64/mls.s
+++ b/sim/testsuite/sim/aarch64/mls.s
@@ -4,6 +4,8 @@
.include "testutils.inc"
+ .data
+ .align 4
input:
.word 0x04030201
.word 0x08070605
diff --git a/sim/testsuite/sim/aarch64/stn_multiple.s b/sim/testsuite/sim/aarch64/stn_multiple.s
new file mode 100644
index 0000000..1a3f24d
--- /dev/null
+++ b/sim/testsuite/sim/aarch64/stn_multiple.s
@@ -0,0 +1,171 @@
+# mach: aarch64
+
+# Check the store multiple structure instructions: st1, st2, st3, st4.
+# Check the addressing modes: no offset, post-index immediate offset,
+# post-index register offset.
+
+.include "testutils.inc"
+
+ .data
+ .align 4
+input:
+ .word 0x04030201
+ .word 0x08070605
+ .word 0x0c0b0a09
+ .word 0x100f0e0d
+ .word 0xfcfdfeff
+ .word 0xf8f9fafb
+ .word 0xf4f5f6f7
+ .word 0xf0f1f2f3
+output:
+ .zero 64
+
+ start
+ adrp x0, input
+ add x0, x0, :lo12:input
+ adrp x1, output
+ add x1, x1, :lo12:output
+
+ mov x2, x0
+ ldr q0, [x2], 16
+ ldr q1, [x2]
+ mov x2, x0
+ ldr q2, [x2], 16
+ ldr q3, [x2]
+
+ mov x2, x1
+ mov x3, #16
+ st1 {v0.16b}, [x2], 16
+ st1 {v1.8h}, [x2], x3
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ mov x4, v4.d[0]
+ cmp x4, #136
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #120
+ bne .Lfailure
+
+ mov x2, x1
+ mov x3, #16
+ st2 {v0.8b, v1.8b}, [x2], 16
+ st2 {v2.4h, v3.4h}, [x2], x3
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ mov x4, v4.d[0]
+ cmp x4, #0
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #0
+ bne .Lfailure
+
+ mov x2, x1
+ st3 {v0.4s, v1.4s, v2.4s}, [x2]
+ ldr q4, [x2], 16
+ ldr q5, [x2], 16
+ ldr q6, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ addv b6, v6.16b
+ mov x4, v4.d[0]
+ cmp x4, #36
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #0
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #100
+ bne .Lfailure
+
+ mov x2, x1
+ st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
+ ldr q4, [x2], 16
+ ldr q5, [x2], 16
+ ldr q6, [x2], 16
+ ldr q7, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ addv b6, v6.16b
+ addv b7, v7.16b
+ mov x4, v4.d[0]
+ cmp x4, #0
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #0
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #0
+ bne .Lfailure
+ mov x7, v7.d[0]
+ cmp x7, #0
+ bne .Lfailure
+
+ pass
+
+ mov x2, x1
+ st1 {v0.2s, v1.2s}, [x2], 16
+ st1 {v2.1d, v3.1d}, [x2]
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ mov x4, v4.d[0]
+ cmp x4, #0
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #0
+ bne .Lfailure
+
+ mov x2, x1
+ st1 {v0.2d, v1.2d, v2.2d}, [x2]
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2], 16
+ ldr q6, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ addv b6, v6.16b
+ mov x4, v4.d[0]
+ cmp x4, #136
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #120
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #136
+ bne .Lfailure
+
+ mov x2, x1
+ st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
+ mov x2, x1
+ ldr q4, [x2], 16
+ ldr q5, [x2], 16
+ ldr q6, [x2], 16
+ ldr q7, [x2]
+ addv b4, v4.16b
+ addv b5, v5.16b
+ addv b6, v6.16b
+ addv b7, v7.16b
+ mov x4, v4.d[0]
+ cmp x4, #136
+ bne .Lfailure
+ mov x5, v5.d[0]
+ cmp x5, #120
+ bne .Lfailure
+ mov x6, v6.d[0]
+ cmp x6, #136
+ bne .Lfailure
+ mov x7, v7.d[0]
+ cmp x7, #120
+ bne .Lfailure
+
+ pass
+.Lfailure:
+ fail
diff --git a/sim/testsuite/sim/aarch64/stn_single.s b/sim/testsuite/sim/aarch64/stn_single.s
index 2bd19cf..a24b084 100644
--- a/sim/testsuite/sim/aarch64/stn_single.s
+++ b/sim/testsuite/sim/aarch64/stn_single.s
@@ -7,6 +7,8 @@
.include "testutils.inc"
+ .data
+ .align 4
input:
.word 0x04030201
.word 0x08070605
@@ -26,10 +28,10 @@ output:
add x1, x1, :lo12:output
mov x2, x0
- ldr q0, [x2], 8
+ ldr q0, [x2], 16
ldr q1, [x2]
mov x2, x0
- ldr q2, [x2], 8
+ ldr q2, [x2], 16
ldr q3, [x2]
mov x2, x1
@@ -61,9 +63,9 @@ output:
addv b5, v5.16b
mov x5, v4.d[0]
mov x6, v5.d[0]
- cmp x5, #136
+ cmp x5, #200
bne .Lfailure
- cmp x6, #8
+ cmp x6, #72
bne .Lfailure
mov x2, x1
@@ -82,11 +84,11 @@ output:
mov x4, v4.d[0]
mov x5, v5.d[0]
mov x6, v6.d[0]
- cmp x4, #88
+ cmp x4, #120
bne .Lfailure
- cmp x5, #200
+ cmp x5, #8
bne .Lfailure
- cmp x6, #248
+ cmp x6, #24
bne .Lfailure
mov x2, x1
@@ -108,13 +110,13 @@ output:
mov x5, v5.d[0]
mov x6, v6.d[0]
mov x7, v7.d[0]
- cmp x4, #104
+ cmp x4, #168
bne .Lfailure
- cmp x5, #168
+ cmp x5, #232
bne .Lfailure
- cmp x6, #232
+ cmp x6, #40
bne .Lfailure
- cmp x7, #40
+ cmp x7, #104
bne .Lfailure
pass
diff --git a/sim/testsuite/sim/aarch64/sumulh.s b/sim/testsuite/sim/aarch64/sumulh.s
index 17f1ecd..d75e0c6 100644
--- a/sim/testsuite/sim/aarch64/sumulh.s
+++ b/sim/testsuite/sim/aarch64/sumulh.s
@@ -6,9 +6,6 @@
.include "testutils.inc"
- .data
- .align 4
-
start
mov x0, #-2
diff --git a/sim/testsuite/sim/aarch64/uzp.s b/sim/testsuite/sim/aarch64/uzp.s
index 55e2cd7..851005e 100644
--- a/sim/testsuite/sim/aarch64/uzp.s
+++ b/sim/testsuite/sim/aarch64/uzp.s
@@ -4,6 +4,8 @@
.include "testutils.inc"
+ .data
+ .align 4
input1:
.word 0x04030201
.word 0x08070605
generated by cgit v1.1 at 2024-11-28 03:09:40 +0000