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-rw-r--r--sim/testsuite/frv/srlcc.cgs38
1 files changed, 38 insertions, 0 deletions
diff --git a/sim/testsuite/frv/srlcc.cgs b/sim/testsuite/frv/srlcc.cgs
new file mode 100644
index 0000000..1450a4b
--- /dev/null
+++ b/sim/testsuite/frv/srlcc.cgs
@@ -0,0 +1,38 @@
+# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1
+# mach: all
+
+ .include "testutils.inc"
+
+ start
+
+ .global srlcc
+srlcc:
+ set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x05,0 ; Set mask opposite of expected
+ srlcc gr8,gr7,gr8,icc0
+ test_icc 1 0 0 0 icc0
+ test_gr_limmed 0x8000,0x0000,gr8
+
+ set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0f,0 ; Set mask opposite of expected
+ srlcc gr8,gr7,gr8,icc0
+ test_icc 0 0 1 0 icc0
+ test_gr_limmed 0x4000,0x0000,gr8
+
+ set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
+ set_gr_limmed 0x8000,0x0000,gr8
+ set_icc 0x0f,0 ; Set mask opposite of expected
+ srlcc gr8,gr7,gr8,icc0
+ test_icc 0 0 1 0 icc0
+ test_gr_immed 1,gr8
+
+ set_gr_limmed 0xdead,0xbeff,gr7 ; clear register
+ set_gr_limmed 0x4000,0x0000,gr8
+ set_icc 0x0a,0 ; Set mask opposite of expected
+ srlcc gr8,gr7,gr8,icc0
+ test_icc 0 1 1 1 icc0
+ test_gr_immed 0x00000000,gr8
+
+ pass