diff options
Diffstat (limited to 'sim/sparc')
42 files changed, 0 insertions, 38142 deletions
diff --git a/sim/sparc/.Sanitize b/sim/sparc/.Sanitize deleted file mode 100644 index 2701b95..0000000 --- a/sim/sparc/.Sanitize +++ /dev/null @@ -1,99 +0,0 @@ -# Sanitize.in for sim/sparc - -# Each directory to survive it's way into a release will need a file -# like this one called "./.Sanitize". All keyword lines must exist, -# and must exist in the order specified by this file. Each directory -# in the tree will be processed, top down, in the following order. - -# Hash started lines like this one are comments and will be deleted -# before anything else is done. Blank lines will also be squashed -# out. - -# The lines between the "Do-first:" line and the "Things-to-keep:" -# line are executed as a /bin/sh shell script before anything else is -# done in this - -Do-first: - -# All files listed between the "Things-to-keep:" line and the -# "Files-to-sed:" line will be kept. All other files will be removed. -# Directories listed in this section will have their own Sanitize -# called. Directories not listed will be removed in their entirety -# with rm -rf. - -Things-to-keep: - -ChangeLog -Makefile.in -acconfig.h -arch.c -arch.h -config.in -configure -configure.in -cpu32.c -cpu32.h -cpu64.c -cpu64.h -cpuall.h -decode32.c -decode32.h -decode64.c -decode64.h -dev32.c -dev32.h -dev64.c -dev64.h -mloop32.in -mloop64.in -model32.c -model64.c -regs32.h -regs64.h -sem32.c -sem64.c -sim-if.c -sim-main.h -sparc-sim.h -sparc.c -sparc32.c -sparc64.c -tconfig.in -trap32.c -trap32.h -trap64.c -trap64.h - -Things-to-lose: - -Do-last: - -cygnus_files="ChangeLog Makefile.in" -if ( echo $* | grep keep\-cygnus > /dev/null ) ; then - for i in $cygnus_files ; do - if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Keeping cygnus stuff in $i - fi - fi - done -else - for i in $cygnus_files ; do - if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then - if [ -n "${verbose}" ] ; then - echo Removing traces of \"cygnus\" from $i... - fi - cp $i new - sed '/start\-sanitize\-cygnus/,/end-\sanitize\-cygnus/d' < $i > new - if [ -n "${safe}" -a ! -f .Recover/$i ] ; then - if [ -n "${verbose}" ] ; then - echo Caching $i in .Recover... - fi - mv $i .Recover - fi - mv new $i - fi - done -fi - -# End of file. diff --git a/sim/sparc/ChangeLog b/sim/sparc/ChangeLog deleted file mode 100644 index b686496..0000000 --- a/sim/sparc/ChangeLog +++ /dev/null @@ -1,32 +0,0 @@ -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * Makefile.in (SPARC64_OBJS): Add dev64.o. - (CPU_OBJS): New variable. - (SIM_OBJS): Add sparc-desc.o. - (SIM_EXTRA_DEPS): Replace cpu-opc.h with sparc-desc.h. - (sim-core.o): Add dev64.h dependency. - (dev64.o): Add rule. - (stamp-arch,stamp-cpu32): Update FLAGS variable, option syntax changed. - (stamp-cpu64): Ditto. - (stamp-desc): New rule. - * configure.in (sim_link_files,sim_link_links): Delete. - Set cpu_objs to one of SPARC32_OBJS,SPARC64_OBJS. - * configure: Rebuild. - * acconfig.h: Rebuild. - * config.in: Rebuild. - * dev64.c: New file. - * dev64.h: New file. - * sparc64.c: New file. - * trap64.h: New file. - * arch.c,arch.h,cpuall.h: Rebuild. - * cpu32.c,decode32.c,decode32.h,model32.c,sem32.c: Rebuild. - * sim-if.c (sparc_disassemble_insn): New function. - (sim_open): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. - Set disassembler. - (sim_close): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. - * sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include - sparc-desc.h,sparc-opc.h,sparc-sim.h. - -1999-02-02 Doug Evans <devans@casey.cygnus.com> - - * Directory created. diff --git a/sim/sparc/Makefile.in b/sim/sparc/Makefile.in deleted file mode 100644 index 5c33f89..0000000 --- a/sim/sparc/Makefile.in +++ /dev/null @@ -1,152 +0,0 @@ -# Makefile template for Configure for the sparc simulator -# Copyright (C) 1999 Cygnus Solutions. - -## COMMON_PRE_CONFIG_FRAG - -SPARC32_OBJS = sparc32.o trap32.o dev32.o cpu32.o decode32.o model32.o mloop32.o sem32.o -SPARC64_OBJS = sparc64.o trap64.o dev64.o cpu64.o decode64.o model64.o mloop64.o sem64.o - -# Set to one of SPARC32_OBJS/SPARC64_OBJS. -CPU_OBJS = @cpu_objs@ - -SIM_OBJS = \ - $(SIM_NEW_COMMON_OBJS) \ - sim-cpu.o \ - sim-hload.o \ - sim-hrw.o \ - sim-model.o \ - sim-reg.o \ - cgen-utils.o cgen-trace.o cgen-scache.o \ - cgen-run.o sim-reason.o sim-engine.o sim-stop.o \ - sim-if.o sparc.o arch.o sparc-desc.o \ - $(CPU_OBJS) - -# Extra headers included by sim-main.h. -# This plus sim_main_headers is used by Make-common.in for files in common. -SIM_EXTRA_DEPS = \ - $(CGEN_INCLUDE_DEPS) \ - arch.h cpuall.h sparc-desc.h -# sparc-sim.h kept out for now (too much unnecessary recompilation) - -SIM_EXTRA_CFLAGS = - -SIM_RUN_OBJS = nrun.o -SIM_EXTRA_CLEAN = sparc-clean - -# This selects the sparc newlib/libgloss syscall definitions. -NL_TARGET = -DNL_TARGET_sparc - -## COMMON_POST_CONFIG_FRAG - -arch = sparc - -sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h \ - dev32.h dev64.h -sparc.o: sparc.c $(SIM_MAIN_DEPS) \ - $(srcdir)/../common/cgen-mem.h \ - $(srcdir)/../common/cgen-ops.h -arch.o: arch.c $(SIM_MAIN_DEPS) - -# sparc32 objs - -SPARC32_INCLUDE_DEPS = \ - $(CGEN_MAIN_CPU_DEPS) \ - cpu32.h decode32.h eng32.h \ - regs32.h trap32.h - -sparc32.o: sparc32.c $(SPARC32_INCLUDE_DEPS) -trap32.o: trap32.c $(SPARC32_INCLUDE_DEPS) -dev32.o: dev32.c $(SPARC32_INCLUDE_DEPS) dev32.h - -# FIXME: Use of `mono' is wip. -# FIXME: Add -fast when switching from -simple to -pbb. -# FIXME: Add -switch sem32-switch.c at same time. -mloop32.c eng32.h: stamp-mloop32 -stamp-mloop32: $(srcdir)/../common/genmloop.sh mloop32.in Makefile - $(SHELL) $(srccom)/genmloop.sh \ - -mono -simple \ - -cpu sparc32 -infile $(srcdir)/mloop32.in - $(SHELL) $(srcroot)/move-if-change eng.hin eng32.h - $(SHELL) $(srcroot)/move-if-change mloop.cin mloop32.c - touch stamp-mloop32 -mloop32.o: mloop32.c sem32-switch.c $(SPARC32_INCLUDE_DEPS) - -cpu32.o: cpu32.c $(SPARC32_INCLUDE_DEPS) -decode32.o: decode32.c $(SPARC32_INCLUDE_DEPS) -model32.o: model32.c $(SPARC32_INCLUDE_DEPS) -sem32.o: sem32.c $(SPARC32_INCLUDE_DEPS) - -# sparc64 objs - -SPARC64_INCLUDE_DEPS = \ - $(CGEN_MAIN_CPU_DEPS) \ - cpu64.h decode64.h eng64.h \ - regs64.h trap64.h - -sparc64.o: sparc64.c $(SPARC64_INCLUDE_DEPS) -trap64.o: trap64.c $(SPARC64_INCLUDE_DEPS) -dev64.o: dev64.c $(SPARC32_INCLUDE_DEPS) dev64.h - -# FIXME: Use of `mono' is wip. -mloop64.c eng64.h: stamp-mloop64 -stamp-mloop64: $(srcdir)/../common/genmloop.sh mloop64.in Makefile - $(SHELL) $(srccom)/genmloop.sh \ - -mono -fast -pbb -switch sem64-switch.c \ - -cpu sparc64 -infile $(srcdir)/mloop64.in - $(SHELL) $(srcroot)/move-if-change eng.hin eng64.h - $(SHELL) $(srcroot)/move-if-change mloop.cin mloop64.c - touch stamp-mloop64 -mloop64.o: mloop64.c sem64-switch.c $(SPARC64_INCLUDE_DEPS) - -cpu64.o: cpu64.c $(SPARC64_INCLUDE_DEPS) -decode64.o: decode64.c $(SPARC64_INCLUDE_DEPS) -model64.o: model64.c $(SPARC64_INCLUDE_DEPS) - -sparc-clean: - rm -f mloop32.c eng32.h stamp-mloop32 - rm -f mloop64.c eng64.h stamp-mloop64 - rm -f stamp-arch stamp-cpu32 stamp-cpu64 stamp-desc - rm -f tmp-* - -# cgen support - -stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) \ - $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu \ - $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu - $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \ - mach=sparc-v8,sparclite,sparc-v9 \ - FLAGS="copyright=cygnus package=cygsim" - touch stamp-arch -arch.h arch.c cpuall.h: $(CGEN_MAIN) stamp-arch - @true - -# Add with-scache to FLAGS when switching to -pbb. -stamp-cpu32: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \ - $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu - $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=sparc32 mach=sparc-v8,sparclite SUFFIX=32 \ - FLAGS="with-profile=fn copyright=cygnus package=cygsim" \ - EXTRAFILES="$(CGEN_CPU_SEM)" - touch stamp-cpu32 -cpu32.h decode32.h decode32.c model32.c sem32.c sem32-switch.c: $(CGEN_MAINT) stamp-cpu32 - @true - -# Add with-scache to FLAGS when switching to -pbb. -stamp-cpu64: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \ - $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc64.cpu - $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=sparc64 mach=sparc-v9 SUFFIX=64 \ - FLAGS="with-profile=fn copyright=cygnus package=cygsim" \ - EXTRAFILES="$(CGEN_CPU_SEM)" - touch stamp-cpu64 -cpu64.h decode64.h decode64.c model64.c sem64.c sem64-switch.c: $(CGEN_MAINT) stamp-cpu64 - @true - -stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \ - $(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu - $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \ - cpu=sparc mach=all \ - FLAGS="copyright=cygnus package=cygsim" - touch stamp-desc -sparc-desc.c sparc-desc.h sparc-opc: $(CGEN_MAINT) stamp-desc - @true diff --git a/sim/sparc/acconfig.h b/sim/sparc/acconfig.h deleted file mode 100644 index 27a2a2f..0000000 --- a/sim/sparc/acconfig.h +++ /dev/null @@ -1,18 +0,0 @@ - -/* Define to 1 if NLS is requested. */ -#undef ENABLE_NLS - -/* Define as 1 if you have catgets and don't want to use GNU gettext. */ -#undef HAVE_CATGETS - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT - -/* Define as 1 if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES - -/* Define if sparc64 target. */ -#undef SPARC64_P diff --git a/sim/sparc/arch.c b/sim/sparc/arch.c deleted file mode 100644 index 5970e8c..0000000 --- a/sim/sparc/arch.c +++ /dev/null @@ -1,2428 +0,0 @@ -/* Simulator support for sparc. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#include "sim-main.h" -#include "bfd.h" - -const MACH *sim_machs[] = -{ -#ifdef HAVE_CPU_SPARC32 - & sparc_v8_mach, -#endif -#ifdef HAVE_CPU_SPARC32 - & sparclite_mach, -#endif -#ifdef HAVE_CPU_SPARC64 - & sparc_v9_mach, -#endif - 0 -}; - -/* Get the value of h-pc. */ - -USI -a_sparc_h_pc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_pc_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_pc_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_pc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pc. */ - -void -a_sparc_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_pc_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_pc_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_pc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-npc. */ - -SI -a_sparc_h_npc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_npc_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_npc_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_npc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-npc. */ - -void -a_sparc_h_npc_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_npc_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_npc_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_npc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-gr. */ - -SI -a_sparc_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_gr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_gr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_gr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-gr. */ - -void -a_sparc_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_gr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_gr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_gr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-icc-c. */ - -BI -a_sparc_h_icc_c_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_icc_c_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_icc_c_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_icc_c_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-icc-c. */ - -void -a_sparc_h_icc_c_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_icc_c_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_icc_c_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_icc_c_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-icc-n. */ - -BI -a_sparc_h_icc_n_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_icc_n_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_icc_n_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_icc_n_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-icc-n. */ - -void -a_sparc_h_icc_n_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_icc_n_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_icc_n_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_icc_n_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-icc-v. */ - -BI -a_sparc_h_icc_v_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_icc_v_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_icc_v_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_icc_v_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-icc-v. */ - -void -a_sparc_h_icc_v_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_icc_v_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_icc_v_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_icc_v_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-icc-z. */ - -BI -a_sparc_h_icc_z_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_icc_z_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_icc_z_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_icc_z_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-icc-z. */ - -void -a_sparc_h_icc_z_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_icc_z_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_icc_z_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_icc_z_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-xcc-c. */ - -BI -a_sparc_h_xcc_c_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_xcc_c_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_xcc_c_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_xcc_c_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-xcc-c. */ - -void -a_sparc_h_xcc_c_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_xcc_c_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_xcc_c_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_xcc_c_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-xcc-n. */ - -BI -a_sparc_h_xcc_n_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_xcc_n_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_xcc_n_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_xcc_n_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-xcc-n. */ - -void -a_sparc_h_xcc_n_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_xcc_n_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_xcc_n_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_xcc_n_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-xcc-v. */ - -BI -a_sparc_h_xcc_v_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_xcc_v_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_xcc_v_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_xcc_v_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-xcc-v. */ - -void -a_sparc_h_xcc_v_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_xcc_v_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_xcc_v_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_xcc_v_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-xcc-z. */ - -BI -a_sparc_h_xcc_z_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_xcc_z_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_xcc_z_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_xcc_z_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-xcc-z. */ - -void -a_sparc_h_xcc_z_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_xcc_z_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_xcc_z_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_xcc_z_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-y. */ - -SI -a_sparc_h_y_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_y_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_y_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_y_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-y. */ - -void -a_sparc_h_y_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_y_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_y_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_y_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-asr. */ - -SI -a_sparc_h_asr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_asr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_asr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_asr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-asr. */ - -void -a_sparc_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_asr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_asr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_asr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-annul-p. */ - -BI -a_sparc_h_annul_p_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_annul_p_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_annul_p_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_annul_p_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-annul-p. */ - -void -a_sparc_h_annul_p_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_annul_p_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_annul_p_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_annul_p_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fr. */ - -SF -a_sparc_h_fr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_fr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_fr_get (current_cpu, regno); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-fr. */ - -void -a_sparc_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_fr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_fr_set (current_cpu, regno, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-psr. */ - -USI -a_sparc_h_psr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_psr_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_psr_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_psr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-psr. */ - -void -a_sparc_h_psr_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_psr_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_psr_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_psr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-s. */ - -BI -a_sparc_h_s_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_s_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_s_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_s_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-s. */ - -void -a_sparc_h_s_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_s_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_s_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_s_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ps. */ - -BI -a_sparc_h_ps_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_ps_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_ps_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_ps_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ps. */ - -void -a_sparc_h_ps_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_ps_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_ps_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_ps_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-pil. */ - -UQI -a_sparc_h_pil_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_pil_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_pil_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_pil_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pil. */ - -void -a_sparc_h_pil_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_pil_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_pil_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_pil_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-et. */ - -BI -a_sparc_h_et_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_et_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_et_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_et_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-et. */ - -void -a_sparc_h_et_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_et_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_et_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_et_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tbr. */ - -SI -a_sparc_h_tbr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_tbr_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_tbr_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tbr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tbr. */ - -void -a_sparc_h_tbr_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_tbr_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_tbr_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tbr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cwp. */ - -UQI -a_sparc_h_cwp_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_cwp_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_cwp_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_cwp_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cwp. */ - -void -a_sparc_h_cwp_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_cwp_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_cwp_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_cwp_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-wim. */ - -USI -a_sparc_h_wim_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_wim_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_wim_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_wim_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-wim. */ - -void -a_sparc_h_wim_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_wim_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_wim_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_wim_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ag. */ - -QI -a_sparc_h_ag_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_ag_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_ag_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_ag_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ag. */ - -void -a_sparc_h_ag_set (SIM_CPU *current_cpu, QI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_ag_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_ag_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_ag_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ec. */ - -BI -a_sparc_h_ec_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_ec_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_ec_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_ec_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ec. */ - -void -a_sparc_h_ec_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_ec_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_ec_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_ec_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ef. */ - -BI -a_sparc_h_ef_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_ef_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_ef_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_ef_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ef. */ - -void -a_sparc_h_ef_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_ef_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_ef_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_ef_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr. */ - -USI -a_sparc_h_fsr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - return sparc32_h_fsr_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - return sparc32_h_fsr_get (current_cpu); -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr. */ - -void -a_sparc_h_fsr_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc : - sparc32_h_fsr_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC32 - case bfd_mach_sparc_sparclite : - sparc32_h_fsr_set (current_cpu, newval); - break; -#endif -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ver. */ - -UDI -a_sparc_h_ver_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_ver_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ver. */ - -void -a_sparc_h_ver_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_ver_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-pstate. */ - -UDI -a_sparc_h_pstate_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_pstate_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pstate. */ - -void -a_sparc_h_pstate_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_pstate_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tba. */ - -UDI -a_sparc_h_tba_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tba_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tba. */ - -void -a_sparc_h_tba_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tba_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tt. */ - -UDI -a_sparc_h_tt_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tt_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tt. */ - -void -a_sparc_h_tt_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tt_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-asi. */ - -UQI -a_sparc_h_asi_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_asi_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-asi. */ - -void -a_sparc_h_asi_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_asi_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tl. */ - -UQI -a_sparc_h_tl_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tl_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tl. */ - -void -a_sparc_h_tl_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tl_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tpc. */ - -UDI -a_sparc_h_tpc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tpc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tpc. */ - -void -a_sparc_h_tpc_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tpc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tnpc. */ - -UDI -a_sparc_h_tnpc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tnpc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tnpc. */ - -void -a_sparc_h_tnpc_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tnpc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tstate. */ - -UDI -a_sparc_h_tstate_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tstate_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tstate. */ - -void -a_sparc_h_tstate_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tstate_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tick. */ - -UDI -a_sparc_h_tick_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_tick_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tick. */ - -void -a_sparc_h_tick_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_tick_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cansave. */ - -UDI -a_sparc_h_cansave_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_cansave_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cansave. */ - -void -a_sparc_h_cansave_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_cansave_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-canrestore. */ - -UDI -a_sparc_h_canrestore_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_canrestore_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-canrestore. */ - -void -a_sparc_h_canrestore_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_canrestore_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-otherwin. */ - -UDI -a_sparc_h_otherwin_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_otherwin_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-otherwin. */ - -void -a_sparc_h_otherwin_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_otherwin_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cleanwin. */ - -UDI -a_sparc_h_cleanwin_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_cleanwin_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cleanwin. */ - -void -a_sparc_h_cleanwin_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_cleanwin_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-wstate. */ - -UDI -a_sparc_h_wstate_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_wstate_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-wstate. */ - -void -a_sparc_h_wstate_set (SIM_CPU *current_cpu, UDI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_wstate_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fcc0. */ - -UQI -a_sparc_h_fcc0_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fcc0_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fcc0. */ - -void -a_sparc_h_fcc0_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fcc0_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fcc1. */ - -UQI -a_sparc_h_fcc1_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fcc1_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fcc1. */ - -void -a_sparc_h_fcc1_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fcc1_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fcc2. */ - -UQI -a_sparc_h_fcc2_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fcc2_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fcc2. */ - -void -a_sparc_h_fcc2_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fcc2_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fcc3. */ - -UQI -a_sparc_h_fcc3_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fcc3_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fcc3. */ - -void -a_sparc_h_fcc3_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fcc3_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-rd. */ - -UQI -a_sparc_h_fsr_rd_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_rd_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-rd. */ - -void -a_sparc_h_fsr_rd_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_rd_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-tem. */ - -UQI -a_sparc_h_fsr_tem_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_tem_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-tem. */ - -void -a_sparc_h_fsr_tem_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_tem_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-ns. */ - -BI -a_sparc_h_fsr_ns_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_ns_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-ns. */ - -void -a_sparc_h_fsr_ns_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_ns_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-ver. */ - -UQI -a_sparc_h_fsr_ver_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_ver_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-ver. */ - -void -a_sparc_h_fsr_ver_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_ver_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-ftt. */ - -UQI -a_sparc_h_fsr_ftt_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_ftt_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-ftt. */ - -void -a_sparc_h_fsr_ftt_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_ftt_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-qne. */ - -BI -a_sparc_h_fsr_qne_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_qne_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-qne. */ - -void -a_sparc_h_fsr_qne_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_qne_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-aexc. */ - -UQI -a_sparc_h_fsr_aexc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_aexc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-aexc. */ - -void -a_sparc_h_fsr_aexc_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_aexc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fsr-cexc. */ - -UQI -a_sparc_h_fsr_cexc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fsr_cexc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fsr-cexc. */ - -void -a_sparc_h_fsr_cexc_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fsr_cexc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fpsr-fef. */ - -BI -a_sparc_h_fpsr_fef_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fpsr_fef_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fpsr-fef. */ - -void -a_sparc_h_fpsr_fef_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fpsr_fef_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fpsr-du. */ - -BI -a_sparc_h_fpsr_du_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fpsr_du_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fpsr-du. */ - -void -a_sparc_h_fpsr_du_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fpsr_du_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fpsr-dl. */ - -BI -a_sparc_h_fpsr_dl_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fpsr_dl_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fpsr-dl. */ - -void -a_sparc_h_fpsr_dl_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fpsr_dl_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-fpsr. */ - -UQI -a_sparc_h_fpsr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - return sparc64_h_fpsr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-fpsr. */ - -void -a_sparc_h_fpsr_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_SPARC64 - case bfd_mach_sparc_v9 : - sparc64_h_fpsr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - diff --git a/sim/sparc/arch.h b/sim/sparc/arch.h deleted file mode 100644 index 704f9b3..0000000 --- a/sim/sparc/arch.h +++ /dev/null @@ -1,149 +0,0 @@ -/* Simulator header for sparc. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef SPARC_ARCH_H -#define SPARC_ARCH_H - -#define TARGET_BIG_ENDIAN 1 - -/* Cover fns for register access. */ -USI a_sparc_h_pc_get (SIM_CPU *); -void a_sparc_h_pc_set (SIM_CPU *, USI); -SI a_sparc_h_npc_get (SIM_CPU *); -void a_sparc_h_npc_set (SIM_CPU *, SI); -SI a_sparc_h_gr_get (SIM_CPU *, UINT); -void a_sparc_h_gr_set (SIM_CPU *, UINT, SI); -BI a_sparc_h_icc_c_get (SIM_CPU *); -void a_sparc_h_icc_c_set (SIM_CPU *, BI); -BI a_sparc_h_icc_n_get (SIM_CPU *); -void a_sparc_h_icc_n_set (SIM_CPU *, BI); -BI a_sparc_h_icc_v_get (SIM_CPU *); -void a_sparc_h_icc_v_set (SIM_CPU *, BI); -BI a_sparc_h_icc_z_get (SIM_CPU *); -void a_sparc_h_icc_z_set (SIM_CPU *, BI); -BI a_sparc_h_xcc_c_get (SIM_CPU *); -void a_sparc_h_xcc_c_set (SIM_CPU *, BI); -BI a_sparc_h_xcc_n_get (SIM_CPU *); -void a_sparc_h_xcc_n_set (SIM_CPU *, BI); -BI a_sparc_h_xcc_v_get (SIM_CPU *); -void a_sparc_h_xcc_v_set (SIM_CPU *, BI); -BI a_sparc_h_xcc_z_get (SIM_CPU *); -void a_sparc_h_xcc_z_set (SIM_CPU *, BI); -SI a_sparc_h_y_get (SIM_CPU *); -void a_sparc_h_y_set (SIM_CPU *, SI); -SI a_sparc_h_asr_get (SIM_CPU *, UINT); -void a_sparc_h_asr_set (SIM_CPU *, UINT, SI); -BI a_sparc_h_annul_p_get (SIM_CPU *); -void a_sparc_h_annul_p_set (SIM_CPU *, BI); -SF a_sparc_h_fr_get (SIM_CPU *, UINT); -void a_sparc_h_fr_set (SIM_CPU *, UINT, SF); -USI a_sparc_h_psr_get (SIM_CPU *); -void a_sparc_h_psr_set (SIM_CPU *, USI); -BI a_sparc_h_s_get (SIM_CPU *); -void a_sparc_h_s_set (SIM_CPU *, BI); -BI a_sparc_h_ps_get (SIM_CPU *); -void a_sparc_h_ps_set (SIM_CPU *, BI); -UQI a_sparc_h_pil_get (SIM_CPU *); -void a_sparc_h_pil_set (SIM_CPU *, UQI); -BI a_sparc_h_et_get (SIM_CPU *); -void a_sparc_h_et_set (SIM_CPU *, BI); -SI a_sparc_h_tbr_get (SIM_CPU *); -void a_sparc_h_tbr_set (SIM_CPU *, SI); -UQI a_sparc_h_cwp_get (SIM_CPU *); -void a_sparc_h_cwp_set (SIM_CPU *, UQI); -USI a_sparc_h_wim_get (SIM_CPU *); -void a_sparc_h_wim_set (SIM_CPU *, USI); -QI a_sparc_h_ag_get (SIM_CPU *); -void a_sparc_h_ag_set (SIM_CPU *, QI); -BI a_sparc_h_ec_get (SIM_CPU *); -void a_sparc_h_ec_set (SIM_CPU *, BI); -BI a_sparc_h_ef_get (SIM_CPU *); -void a_sparc_h_ef_set (SIM_CPU *, BI); -USI a_sparc_h_fsr_get (SIM_CPU *); -void a_sparc_h_fsr_set (SIM_CPU *, USI); -UDI a_sparc_h_ver_get (SIM_CPU *); -void a_sparc_h_ver_set (SIM_CPU *, UDI); -UDI a_sparc_h_pstate_get (SIM_CPU *); -void a_sparc_h_pstate_set (SIM_CPU *, UDI); -UDI a_sparc_h_tba_get (SIM_CPU *); -void a_sparc_h_tba_set (SIM_CPU *, UDI); -UDI a_sparc_h_tt_get (SIM_CPU *); -void a_sparc_h_tt_set (SIM_CPU *, UDI); -UQI a_sparc_h_asi_get (SIM_CPU *); -void a_sparc_h_asi_set (SIM_CPU *, UQI); -UQI a_sparc_h_tl_get (SIM_CPU *); -void a_sparc_h_tl_set (SIM_CPU *, UQI); -UDI a_sparc_h_tpc_get (SIM_CPU *); -void a_sparc_h_tpc_set (SIM_CPU *, UDI); -UDI a_sparc_h_tnpc_get (SIM_CPU *); -void a_sparc_h_tnpc_set (SIM_CPU *, UDI); -UDI a_sparc_h_tstate_get (SIM_CPU *); -void a_sparc_h_tstate_set (SIM_CPU *, UDI); -UDI a_sparc_h_tick_get (SIM_CPU *); -void a_sparc_h_tick_set (SIM_CPU *, UDI); -UDI a_sparc_h_cansave_get (SIM_CPU *); -void a_sparc_h_cansave_set (SIM_CPU *, UDI); -UDI a_sparc_h_canrestore_get (SIM_CPU *); -void a_sparc_h_canrestore_set (SIM_CPU *, UDI); -UDI a_sparc_h_otherwin_get (SIM_CPU *); -void a_sparc_h_otherwin_set (SIM_CPU *, UDI); -UDI a_sparc_h_cleanwin_get (SIM_CPU *); -void a_sparc_h_cleanwin_set (SIM_CPU *, UDI); -UDI a_sparc_h_wstate_get (SIM_CPU *); -void a_sparc_h_wstate_set (SIM_CPU *, UDI); -UQI a_sparc_h_fcc0_get (SIM_CPU *); -void a_sparc_h_fcc0_set (SIM_CPU *, UQI); -UQI a_sparc_h_fcc1_get (SIM_CPU *); -void a_sparc_h_fcc1_set (SIM_CPU *, UQI); -UQI a_sparc_h_fcc2_get (SIM_CPU *); -void a_sparc_h_fcc2_set (SIM_CPU *, UQI); -UQI a_sparc_h_fcc3_get (SIM_CPU *); -void a_sparc_h_fcc3_set (SIM_CPU *, UQI); -UQI a_sparc_h_fsr_rd_get (SIM_CPU *); -void a_sparc_h_fsr_rd_set (SIM_CPU *, UQI); -UQI a_sparc_h_fsr_tem_get (SIM_CPU *); -void a_sparc_h_fsr_tem_set (SIM_CPU *, UQI); -BI a_sparc_h_fsr_ns_get (SIM_CPU *); -void a_sparc_h_fsr_ns_set (SIM_CPU *, BI); -UQI a_sparc_h_fsr_ver_get (SIM_CPU *); -void a_sparc_h_fsr_ver_set (SIM_CPU *, UQI); -UQI a_sparc_h_fsr_ftt_get (SIM_CPU *); -void a_sparc_h_fsr_ftt_set (SIM_CPU *, UQI); -BI a_sparc_h_fsr_qne_get (SIM_CPU *); -void a_sparc_h_fsr_qne_set (SIM_CPU *, BI); -UQI a_sparc_h_fsr_aexc_get (SIM_CPU *); -void a_sparc_h_fsr_aexc_set (SIM_CPU *, UQI); -UQI a_sparc_h_fsr_cexc_get (SIM_CPU *); -void a_sparc_h_fsr_cexc_set (SIM_CPU *, UQI); -BI a_sparc_h_fpsr_fef_get (SIM_CPU *); -void a_sparc_h_fpsr_fef_set (SIM_CPU *, BI); -BI a_sparc_h_fpsr_du_get (SIM_CPU *); -void a_sparc_h_fpsr_du_set (SIM_CPU *, BI); -BI a_sparc_h_fpsr_dl_get (SIM_CPU *); -void a_sparc_h_fpsr_dl_set (SIM_CPU *, BI); -UQI a_sparc_h_fpsr_get (SIM_CPU *); -void a_sparc_h_fpsr_set (SIM_CPU *, UQI); - -/* Enum declaration for model types. */ -typedef enum model_type { - MODEL_SPARC32_DEF, MODEL_SPARC64_DEF, MODEL_MAX -} MODEL_TYPE; - -#define MAX_MODELS ((int) MODEL_MAX) - -/* Enum declaration for unit types. */ -typedef enum unit_type { - UNIT_NONE, UNIT_SPARC32_DEF_U_EXEC, UNIT_SPARC64_DEF_U_EXEC, UNIT_MAX -} UNIT_TYPE; - -#define MAX_UNITS (1) - -#endif /* SPARC_ARCH_H */ diff --git a/sim/sparc/config.in b/sim/sparc/config.in deleted file mode 100644 index 106929f..0000000 --- a/sim/sparc/config.in +++ /dev/null @@ -1,49 +0,0 @@ -/* config.in. Generated automatically from configure.in by autoheader. */ - -/* Define if you have the <stdlib.h> header file. */ -#undef HAVE_STDLIB_H - -/* Define if you have the <string.h> header file. */ -#undef HAVE_STRING_H - -/* Define if you have the <strings.h> header file. */ -#undef HAVE_STRINGS_H - -/* Define if you have the <unistd.h> header file. */ -#undef HAVE_UNISTD_H - -/* Define if you have the <alloca.h> header file. */ -#undef HAVE_ALLOCA_H - -/* Define if you have the <time.h> header file. */ -#undef HAVE_TIME_H - -/* Define if you have the <sys/time.h> header file. - This is needed by sys/resource.h. */ -#undef HAVE_SYS_TIME_H - -/* Define if you have the <sys/resource.h> header file. */ -#undef HAVE_SYS_RESOURCE_H - -/* Define if you have the getrusage function. */ -#undef HAVE_GETRUSAGE - -/* Define if you have the time function. */ -#undef HAVE_TIME - -/* Define as the return type of signal handlers (int or void). */ -#undef RETSIGTYPE - -/* Define if your processor stores words with the most significant - byte first (like Motorola and SPARC, unlike Intel and VAX). */ -#undef WORDS_BIGENDIAN - -/* Change autoconf's value into ours. */ -#ifdef WORDS_BIGENDIAN -#define HOST_BIG_ENDIAN 1 -#else -#define HOST_BIG_ENDIAN 0 -#endif - -/* Defined if --enable-sim-cache provided. */ -#undef CONFIG_SIM_CACHE_SIZE diff --git a/sim/sparc/configure b/sim/sparc/configure deleted file mode 100755 index a02c0d7..0000000 --- a/sim/sparc/configure +++ /dev/null @@ -1,4255 +0,0 @@ -#! /bin/sh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -sim_inline="-DDEFAULT_INLINE=0" - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# This file is derived from `gettext.m4'. The difference is that the -# included macros assume Cygnus-style source and build trees. - -# Macro to add for using GNU gettext. -# Ulrich Drepper <drepper@cygnus.com>, 1995. -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -# serial 3 - - - - - -# Search path for a program which passes the given test. -# Ulrich Drepper <drepper@cygnus.com>, 1996. -# -# This file file be copied and used freely without restrictions. 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-} - -/* Set a value for h-pc. */ - -void -sparc32_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - CPU (h_pc) = newval; -} - -/* Get the value of h-npc. */ - -SI -sparc32_h_npc_get (SIM_CPU *current_cpu) -{ - return CPU (h_npc); -} - -/* Set a value for h-npc. */ - -void -sparc32_h_npc_set (SIM_CPU *current_cpu, SI newval) -{ - CPU (h_npc) = newval; -} - -/* Get the value of h-gr. */ - -SI -sparc32_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - return GET_H_GR (regno); -} - -/* Set a value for h-gr. */ - -void -sparc32_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - SET_H_GR (regno, newval); -} - -/* Get the value of h-icc-c. */ - -BI -sparc32_h_icc_c_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_c); -} - -/* Set a value for h-icc-c. */ - -void -sparc32_h_icc_c_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_c) = newval; -} - -/* Get the value of h-icc-n. */ - -BI -sparc32_h_icc_n_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_n); -} - -/* Set a value for h-icc-n. */ - -void -sparc32_h_icc_n_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_n) = newval; -} - -/* Get the value of h-icc-v. */ - -BI -sparc32_h_icc_v_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_v); -} - -/* Set a value for h-icc-v. */ - -void -sparc32_h_icc_v_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_v) = newval; -} - -/* Get the value of h-icc-z. */ - -BI -sparc32_h_icc_z_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_z); -} - -/* Set a value for h-icc-z. */ - -void -sparc32_h_icc_z_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_z) = newval; -} - -/* Get the value of h-xcc-c. */ - -BI -sparc32_h_xcc_c_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_c); -} - -/* Set a value for h-xcc-c. */ - -void -sparc32_h_xcc_c_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_c) = newval; -} - -/* Get the value of h-xcc-n. */ - -BI -sparc32_h_xcc_n_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_n); -} - -/* Set a value for h-xcc-n. */ - -void -sparc32_h_xcc_n_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_n) = newval; -} - -/* Get the value of h-xcc-v. */ - -BI -sparc32_h_xcc_v_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_v); -} - -/* Set a value for h-xcc-v. */ - -void -sparc32_h_xcc_v_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_v) = newval; -} - -/* Get the value of h-xcc-z. */ - -BI -sparc32_h_xcc_z_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_z); -} - -/* Set a value for h-xcc-z. */ - -void -sparc32_h_xcc_z_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_z) = newval; -} - -/* Get the value of h-y. */ - -SI -sparc32_h_y_get (SIM_CPU *current_cpu) -{ - return GET_H_Y (); -} - -/* Set a value for h-y. */ - -void -sparc32_h_y_set (SIM_CPU *current_cpu, SI newval) -{ - SET_H_Y (newval); -} - -/* Get the value of h-asr. */ - -SI -sparc32_h_asr_get (SIM_CPU *current_cpu, UINT regno) -{ - return CPU (h_asr[regno]); -} - -/* Set a value for h-asr. */ - -void -sparc32_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - CPU (h_asr[regno]) = newval; -} - -/* Get the value of h-annul-p. */ - -BI -sparc32_h_annul_p_get (SIM_CPU *current_cpu) -{ - return CPU (h_annul_p); -} - -/* Set a value for h-annul-p. */ - -void -sparc32_h_annul_p_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_annul_p) = newval; -} - -/* Get the value of h-fr. */ - -SF -sparc32_h_fr_get (SIM_CPU *current_cpu, UINT regno) -{ - return CPU (h_fr[regno]); -} - -/* Set a value for h-fr. */ - -void -sparc32_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) -{ - CPU (h_fr[regno]) = newval; -} - -/* Get the value of h-psr. */ - -USI -sparc32_h_psr_get (SIM_CPU *current_cpu) -{ - return GET_H_PSR (); -} - -/* Set a value for h-psr. */ - -void -sparc32_h_psr_set (SIM_CPU *current_cpu, USI newval) -{ - SET_H_PSR (newval); -} - -/* Get the value of h-s. */ - -BI -sparc32_h_s_get (SIM_CPU *current_cpu) -{ - return CPU (h_s); -} - -/* Set a value for h-s. */ - -void -sparc32_h_s_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_s) = newval; -} - -/* Get the value of h-ps. */ - -BI -sparc32_h_ps_get (SIM_CPU *current_cpu) -{ - return CPU (h_ps); -} - -/* Set a value for h-ps. */ - -void -sparc32_h_ps_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_ps) = newval; -} - -/* Get the value of h-pil. */ - -UQI -sparc32_h_pil_get (SIM_CPU *current_cpu) -{ - return CPU (h_pil); -} - -/* Set a value for h-pil. */ - -void -sparc32_h_pil_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_pil) = newval; -} - -/* Get the value of h-et. */ - -BI -sparc32_h_et_get (SIM_CPU *current_cpu) -{ - return CPU (h_et); -} - -/* Set a value for h-et. */ - -void -sparc32_h_et_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_et) = newval; -} - -/* Get the value of h-tbr. */ - -SI -sparc32_h_tbr_get (SIM_CPU *current_cpu) -{ - return GET_H_TBR (); -} - -/* Set a value for h-tbr. */ - -void -sparc32_h_tbr_set (SIM_CPU *current_cpu, SI newval) -{ - SET_H_TBR (newval); -} - -/* Get the value of h-cwp. */ - -UQI -sparc32_h_cwp_get (SIM_CPU *current_cpu) -{ - return GET_H_CWP (); -} - -/* Set a value for h-cwp. */ - -void -sparc32_h_cwp_set (SIM_CPU *current_cpu, UQI newval) -{ - SET_H_CWP (newval); -} - -/* Get the value of h-wim. */ - -USI -sparc32_h_wim_get (SIM_CPU *current_cpu) -{ - return GET_H_WIM (); -} - -/* Set a value for h-wim. */ - -void -sparc32_h_wim_set (SIM_CPU *current_cpu, USI newval) -{ - SET_H_WIM (newval); -} - -/* Get the value of h-ag. */ - -QI -sparc32_h_ag_get (SIM_CPU *current_cpu) -{ - return CPU (h_ag); -} - -/* Set a value for h-ag. */ - -void -sparc32_h_ag_set (SIM_CPU *current_cpu, QI newval) -{ - CPU (h_ag) = newval; -} - -/* Get the value of h-ec. */ - -BI -sparc32_h_ec_get (SIM_CPU *current_cpu) -{ - return CPU (h_ec); -} - -/* Set a value for h-ec. */ - -void -sparc32_h_ec_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_ec) = newval; -} - -/* Get the value of h-ef. */ - -BI -sparc32_h_ef_get (SIM_CPU *current_cpu) -{ - return CPU (h_ef); -} - -/* Set a value for h-ef. */ - -void -sparc32_h_ef_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_ef) = newval; -} - -/* Get the value of h-fsr. */ - -USI -sparc32_h_fsr_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr); -} - -/* Set a value for h-fsr. */ - -void -sparc32_h_fsr_set (SIM_CPU *current_cpu, USI newval) -{ - CPU (h_fsr) = newval; -} - -/* Record trace results for INSN. */ - -void -sparc32_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, - int *indices, TRACE_RECORD *tr) -{ -} diff --git a/sim/sparc/cpu32.h b/sim/sparc/cpu32.h deleted file mode 100644 index c822a3d..0000000 --- a/sim/sparc/cpu32.h +++ /dev/null @@ -1,618 +0,0 @@ -/* CPU family header for sparc32. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef CPU_SPARC32_H -#define CPU_SPARC32_H - -/* Maximum number of instructions that are fetched at a time. - This is for LIW type instructions sets (e.g. m32r). */ -#define MAX_LIW_INSNS 1 - -/* Maximum number of instructions that can be executed in parallel. */ -#define MAX_PARALLEL_INSNS 1 - -/* CPU state information. */ -typedef struct { - /* Hardware elements. */ - struct { - /* program counter */ - USI h_pc; -#define GET_H_PC() CPU (h_pc) -#define SET_H_PC(x) (CPU (h_pc) = (x)) - /* next pc */ - SI h_npc; -#define GET_H_NPC() CPU (h_npc) -#define SET_H_NPC(x) (CPU (h_npc) = (x)) -/* GET_H_GR macro user-written */ -/* SET_H_GR macro user-written */ - /* icc carry bit */ - BI h_icc_c; -#define GET_H_ICC_C() CPU (h_icc_c) -#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x)) - /* icc negative bit */ - BI h_icc_n; -#define GET_H_ICC_N() CPU (h_icc_n) -#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x)) - /* icc overflow bit */ - BI h_icc_v; -#define GET_H_ICC_V() CPU (h_icc_v) -#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x)) - /* icc zero bit */ - BI h_icc_z; -#define GET_H_ICC_Z() CPU (h_icc_z) -#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x)) - /* xcc carry bit */ - BI h_xcc_c; -#define GET_H_XCC_C() CPU (h_xcc_c) -#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x)) - /* xcc negative bit */ - BI h_xcc_n; -#define GET_H_XCC_N() CPU (h_xcc_n) -#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x)) - /* xcc overflow bit */ - BI h_xcc_v; -#define GET_H_XCC_V() CPU (h_xcc_v) -#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x)) - /* xcc zero bit */ - BI h_xcc_z; -#define GET_H_XCC_Z() CPU (h_xcc_z) -#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x)) -/* GET_H_Y macro user-written */ -/* SET_H_Y macro user-written */ - /* ancilliary state registers */ - SI h_asr[32]; -#define GET_H_ASR(a1) CPU (h_asr)[a1] -#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x)) - /* annul next insn? - assists execution */ - BI h_annul_p; -#define GET_H_ANNUL_P() CPU (h_annul_p) -#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x)) - /* floating point regs */ - SF h_fr[32]; -#define GET_H_FR(a1) CPU (h_fr)[a1] -#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) - /* psr register */ - USI h_psr; -/* GET_H_PSR macro user-written */ -/* SET_H_PSR macro user-written */ - /* supervisor bit */ - BI h_s; -#define GET_H_S() CPU (h_s) -#define SET_H_S(x) (CPU (h_s) = (x)) - /* previous supervisor bit */ - BI h_ps; -#define GET_H_PS() CPU (h_ps) -#define SET_H_PS(x) (CPU (h_ps) = (x)) - /* processor interrupt level */ - UQI h_pil; -#define GET_H_PIL() CPU (h_pil) -#define SET_H_PIL(x) (CPU (h_pil) = (x)) - /* enable traps bit */ - BI h_et; -#define GET_H_ET() CPU (h_et) -#define SET_H_ET(x) (CPU (h_et) = (x)) - /* tbr register */ - SI h_tbr; -/* GET_H_TBR macro user-written */ -/* SET_H_TBR macro user-written */ - /* current window pointer */ - UQI h_cwp; -/* GET_H_CWP macro user-written */ -/* SET_H_CWP macro user-written */ - /* window invalid mask */ - USI h_wim; -/* GET_H_WIM macro user-written */ -/* SET_H_WIM macro user-written */ - /* alternate global indicator */ - QI h_ag; -#define GET_H_AG() CPU (h_ag) -#define SET_H_AG(x) (CPU (h_ag) = (x)) - /* enable coprocessor bit */ - BI h_ec; -#define GET_H_EC() CPU (h_ec) -#define SET_H_EC(x) (CPU (h_ec) = (x)) - /* enable fpu bit */ - BI h_ef; -#define GET_H_EF() CPU (h_ef) -#define SET_H_EF(x) (CPU (h_ef) = (x)) - /* floating point status register */ - USI h_fsr; -#define GET_H_FSR() CPU (h_fsr) -#define SET_H_FSR(x) (CPU (h_fsr) = (x)) - } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) -} SPARC32_CPU_DATA; - -/* Cover fns for register access. */ -USI sparc32_h_pc_get (SIM_CPU *); -void sparc32_h_pc_set (SIM_CPU *, USI); -SI sparc32_h_npc_get (SIM_CPU *); -void sparc32_h_npc_set (SIM_CPU *, SI); -SI sparc32_h_gr_get (SIM_CPU *, UINT); -void sparc32_h_gr_set (SIM_CPU *, UINT, SI); -BI sparc32_h_icc_c_get (SIM_CPU *); -void sparc32_h_icc_c_set (SIM_CPU *, BI); -BI sparc32_h_icc_n_get (SIM_CPU *); -void sparc32_h_icc_n_set (SIM_CPU *, BI); -BI sparc32_h_icc_v_get (SIM_CPU *); -void sparc32_h_icc_v_set (SIM_CPU *, BI); -BI sparc32_h_icc_z_get (SIM_CPU *); -void sparc32_h_icc_z_set (SIM_CPU *, BI); -BI sparc32_h_xcc_c_get (SIM_CPU *); -void sparc32_h_xcc_c_set (SIM_CPU *, BI); -BI sparc32_h_xcc_n_get (SIM_CPU *); -void sparc32_h_xcc_n_set (SIM_CPU *, BI); -BI sparc32_h_xcc_v_get (SIM_CPU *); -void sparc32_h_xcc_v_set (SIM_CPU *, BI); -BI sparc32_h_xcc_z_get (SIM_CPU *); -void sparc32_h_xcc_z_set (SIM_CPU *, BI); -SI sparc32_h_y_get (SIM_CPU *); -void sparc32_h_y_set (SIM_CPU *, SI); -SI sparc32_h_asr_get (SIM_CPU *, UINT); -void sparc32_h_asr_set (SIM_CPU *, UINT, SI); -BI sparc32_h_annul_p_get (SIM_CPU *); -void sparc32_h_annul_p_set (SIM_CPU *, BI); -SF sparc32_h_fr_get (SIM_CPU *, UINT); -void sparc32_h_fr_set (SIM_CPU *, UINT, SF); -USI sparc32_h_psr_get (SIM_CPU *); -void sparc32_h_psr_set (SIM_CPU *, USI); -BI sparc32_h_s_get (SIM_CPU *); -void sparc32_h_s_set (SIM_CPU *, BI); -BI sparc32_h_ps_get (SIM_CPU *); -void sparc32_h_ps_set (SIM_CPU *, BI); -UQI sparc32_h_pil_get (SIM_CPU *); -void sparc32_h_pil_set (SIM_CPU *, UQI); -BI sparc32_h_et_get (SIM_CPU *); -void sparc32_h_et_set (SIM_CPU *, BI); -SI sparc32_h_tbr_get (SIM_CPU *); -void sparc32_h_tbr_set (SIM_CPU *, SI); -UQI sparc32_h_cwp_get (SIM_CPU *); -void sparc32_h_cwp_set (SIM_CPU *, UQI); -USI sparc32_h_wim_get (SIM_CPU *); -void sparc32_h_wim_set (SIM_CPU *, USI); -QI sparc32_h_ag_get (SIM_CPU *); -void sparc32_h_ag_set (SIM_CPU *, QI); -BI sparc32_h_ec_get (SIM_CPU *); -void sparc32_h_ec_set (SIM_CPU *, BI); -BI sparc32_h_ef_get (SIM_CPU *); -void sparc32_h_ef_set (SIM_CPU *, BI); -USI sparc32_h_fsr_get (SIM_CPU *); -void sparc32_h_fsr_set (SIM_CPU *, USI); - -/* These must be hand-written. */ -extern CPUREG_FETCH_FN sparc32_fetch_register; -extern CPUREG_STORE_FN sparc32_store_register; - -typedef struct { - int empty; -} MODEL_SPARC32_DEF_DATA; - -/* The ARGBUF struct. */ -struct argbuf { - /* These are the baseclass definitions. */ - IADDR addr; - const IDESC *idesc; - char trace_p; - char profile_p; - /* cpu specific data follows */ - CGEN_INSN_INT insn; - int written; -}; - -/* A cached insn. - - ??? SCACHE used to contain more than just argbuf. We could delete the - type entirely and always just use ARGBUF, but for future concerns and as - a level of abstraction it is left in. */ - -struct scache { - struct argbuf argbuf; -}; - -/* Macros to simplify extraction, reading and semantic code. - These define and assign the local vars that contain the insn's fields. */ - -#define EXTRACT_IFMT_EMPTY_VARS \ - /* Instruction fields. */ \ - unsigned int length; -#define EXTRACT_IFMT_EMPTY_CODE \ - length = 0; \ - -#define EXTRACT_IFMT_RD_ASR_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_RD_ASR_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_WR_ASR_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_WR_ASR_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_WR_ASR_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_WR_ASR_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_RD_PSR_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_RD_PSR_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_WR_PSR_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_WR_PSR_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_WR_PSR_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_WR_PSR_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDSTUB_REG_REG_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDSTUB_REG_REG_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDSTUB_REG_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDSTUB_REG_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - UINT f_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDD_REG_REG_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDD_REG_REG_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDD_REG_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDD_REG_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - UINT f_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - UINT f_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_SETHI_VARS \ - /* Instruction fields. */ \ - INT f_hi22; \ - UINT f_op2; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_SETHI_CODE \ - length = 4; \ - f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_UNIMP_VARS \ - /* Instruction fields. */ \ - INT f_imm22; \ - UINT f_op2; \ - UINT f_rd_res; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_UNIMP_CODE \ - length = 4; \ - f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_CALL_VARS \ - /* Instruction fields. */ \ - SI f_disp30; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_CALL_CODE \ - length = 4; \ - f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_BA_VARS \ - /* Instruction fields. */ \ - SI f_disp22; \ - UINT f_op2; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_BA_CODE \ - length = 4; \ - f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_TA_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_TA_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_TA_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_TA_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -/* Collection of various things for the trace handler to use. */ - -typedef struct trace_record { - IADDR pc; - /* FIXME:wip */ -} TRACE_RECORD; - -#endif /* CPU_SPARC32_H */ diff --git a/sim/sparc/cpu64.c b/sim/sparc/cpu64.c deleted file mode 100644 index 8d27e75..0000000 --- a/sim/sparc/cpu64.c +++ /dev/null @@ -1,759 +0,0 @@ -/* Misc. support for CPU family sparc64. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc64 -#define WANT_CPU_SPARC64 - -#include "sim-main.h" - -/* Get the value of h-pc. */ - -USI -sparc64_h_pc_get (SIM_CPU *current_cpu) -{ - return CPU (h_pc); -} - -/* Set a value for h-pc. */ - -void -sparc64_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - CPU (h_pc) = newval; -} - -/* Get the value of h-npc. */ - -SI -sparc64_h_npc_get (SIM_CPU *current_cpu) -{ - return CPU (h_npc); -} - -/* Set a value for h-npc. */ - -void -sparc64_h_npc_set (SIM_CPU *current_cpu, SI newval) -{ - CPU (h_npc) = newval; -} - -/* Get the value of h-gr. */ - -SI -sparc64_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - return GET_H_GR (regno); -} - -/* Set a value for h-gr. */ - -void -sparc64_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - SET_H_GR (regno, newval); -} - -/* Get the value of h-icc-c. */ - -BI -sparc64_h_icc_c_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_c); -} - -/* Set a value for h-icc-c. */ - -void -sparc64_h_icc_c_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_c) = newval; -} - -/* Get the value of h-icc-n. */ - -BI -sparc64_h_icc_n_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_n); -} - -/* Set a value for h-icc-n. */ - -void -sparc64_h_icc_n_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_n) = newval; -} - -/* Get the value of h-icc-v. */ - -BI -sparc64_h_icc_v_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_v); -} - -/* Set a value for h-icc-v. */ - -void -sparc64_h_icc_v_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_v) = newval; -} - -/* Get the value of h-icc-z. */ - -BI -sparc64_h_icc_z_get (SIM_CPU *current_cpu) -{ - return CPU (h_icc_z); -} - -/* Set a value for h-icc-z. */ - -void -sparc64_h_icc_z_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_icc_z) = newval; -} - -/* Get the value of h-xcc-c. */ - -BI -sparc64_h_xcc_c_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_c); -} - -/* Set a value for h-xcc-c. */ - -void -sparc64_h_xcc_c_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_c) = newval; -} - -/* Get the value of h-xcc-n. */ - -BI -sparc64_h_xcc_n_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_n); -} - -/* Set a value for h-xcc-n. */ - -void -sparc64_h_xcc_n_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_n) = newval; -} - -/* Get the value of h-xcc-v. */ - -BI -sparc64_h_xcc_v_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_v); -} - -/* Set a value for h-xcc-v. */ - -void -sparc64_h_xcc_v_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_v) = newval; -} - -/* Get the value of h-xcc-z. */ - -BI -sparc64_h_xcc_z_get (SIM_CPU *current_cpu) -{ - return CPU (h_xcc_z); -} - -/* Set a value for h-xcc-z. */ - -void -sparc64_h_xcc_z_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_xcc_z) = newval; -} - -/* Get the value of h-y. */ - -SI -sparc64_h_y_get (SIM_CPU *current_cpu) -{ - return GET_H_Y (); -} - -/* Set a value for h-y. */ - -void -sparc64_h_y_set (SIM_CPU *current_cpu, SI newval) -{ - SET_H_Y (newval); -} - -/* Get the value of h-asr. */ - -SI -sparc64_h_asr_get (SIM_CPU *current_cpu, UINT regno) -{ - return CPU (h_asr[regno]); -} - -/* Set a value for h-asr. */ - -void -sparc64_h_asr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - CPU (h_asr[regno]) = newval; -} - -/* Get the value of h-annul-p. */ - -BI -sparc64_h_annul_p_get (SIM_CPU *current_cpu) -{ - return CPU (h_annul_p); -} - -/* Set a value for h-annul-p. */ - -void -sparc64_h_annul_p_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_annul_p) = newval; -} - -/* Get the value of h-fr. */ - -SF -sparc64_h_fr_get (SIM_CPU *current_cpu, UINT regno) -{ - return CPU (h_fr[regno]); -} - -/* Set a value for h-fr. */ - -void -sparc64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) -{ - CPU (h_fr[regno]) = newval; -} - -/* Get the value of h-ver. */ - -UDI -sparc64_h_ver_get (SIM_CPU *current_cpu) -{ - return CPU (h_ver); -} - -/* Set a value for h-ver. */ - -void -sparc64_h_ver_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_ver) = newval; -} - -/* Get the value of h-pstate. */ - -UDI -sparc64_h_pstate_get (SIM_CPU *current_cpu) -{ - return CPU (h_pstate); -} - -/* Set a value for h-pstate. */ - -void -sparc64_h_pstate_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_pstate) = newval; -} - -/* Get the value of h-tba. */ - -UDI -sparc64_h_tba_get (SIM_CPU *current_cpu) -{ - return CPU (h_tba); -} - -/* Set a value for h-tba. */ - -void -sparc64_h_tba_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_tba) = newval; -} - -/* Get the value of h-tt. */ - -UDI -sparc64_h_tt_get (SIM_CPU *current_cpu) -{ - return CPU (h_tt); -} - -/* Set a value for h-tt. */ - -void -sparc64_h_tt_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_tt) = newval; -} - -/* Get the value of h-tpc. */ - -UDI -sparc64_h_tpc_get (SIM_CPU *current_cpu) -{ - return CPU (h_tpc); -} - -/* Set a value for h-tpc. */ - -void -sparc64_h_tpc_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_tpc) = newval; -} - -/* Get the value of h-tnpc. */ - -UDI -sparc64_h_tnpc_get (SIM_CPU *current_cpu) -{ - return CPU (h_tnpc); -} - -/* Set a value for h-tnpc. */ - -void -sparc64_h_tnpc_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_tnpc) = newval; -} - -/* Get the value of h-tstate. */ - -UDI -sparc64_h_tstate_get (SIM_CPU *current_cpu) -{ - return CPU (h_tstate); -} - -/* Set a value for h-tstate. */ - -void -sparc64_h_tstate_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_tstate) = newval; -} - -/* Get the value of h-tl. */ - -UQI -sparc64_h_tl_get (SIM_CPU *current_cpu) -{ - return CPU (h_tl); -} - -/* Set a value for h-tl. */ - -void -sparc64_h_tl_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_tl) = newval; -} - -/* Get the value of h-asi. */ - -UQI -sparc64_h_asi_get (SIM_CPU *current_cpu) -{ - return CPU (h_asi); -} - -/* Set a value for h-asi. */ - -void -sparc64_h_asi_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_asi) = newval; -} - -/* Get the value of h-tick. */ - -UDI -sparc64_h_tick_get (SIM_CPU *current_cpu) -{ - return CPU (h_tick); -} - -/* Set a value for h-tick. */ - -void -sparc64_h_tick_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_tick) = newval; -} - -/* Get the value of h-cansave. */ - -UDI -sparc64_h_cansave_get (SIM_CPU *current_cpu) -{ - return CPU (h_cansave); -} - -/* Set a value for h-cansave. */ - -void -sparc64_h_cansave_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_cansave) = newval; -} - -/* Get the value of h-canrestore. */ - -UDI -sparc64_h_canrestore_get (SIM_CPU *current_cpu) -{ - return CPU (h_canrestore); -} - -/* Set a value for h-canrestore. */ - -void -sparc64_h_canrestore_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_canrestore) = newval; -} - -/* Get the value of h-otherwin. */ - -UDI -sparc64_h_otherwin_get (SIM_CPU *current_cpu) -{ - return CPU (h_otherwin); -} - -/* Set a value for h-otherwin. */ - -void -sparc64_h_otherwin_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_otherwin) = newval; -} - -/* Get the value of h-cleanwin. */ - -UDI -sparc64_h_cleanwin_get (SIM_CPU *current_cpu) -{ - return CPU (h_cleanwin); -} - -/* Set a value for h-cleanwin. */ - -void -sparc64_h_cleanwin_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_cleanwin) = newval; -} - -/* Get the value of h-wstate. */ - -UDI -sparc64_h_wstate_get (SIM_CPU *current_cpu) -{ - return CPU (h_wstate); -} - -/* Set a value for h-wstate. */ - -void -sparc64_h_wstate_set (SIM_CPU *current_cpu, UDI newval) -{ - CPU (h_wstate) = newval; -} - -/* Get the value of h-fcc0. */ - -UQI -sparc64_h_fcc0_get (SIM_CPU *current_cpu) -{ - return CPU (h_fcc0); -} - -/* Set a value for h-fcc0. */ - -void -sparc64_h_fcc0_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fcc0) = newval; -} - -/* Get the value of h-fcc1. */ - -UQI -sparc64_h_fcc1_get (SIM_CPU *current_cpu) -{ - return CPU (h_fcc1); -} - -/* Set a value for h-fcc1. */ - -void -sparc64_h_fcc1_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fcc1) = newval; -} - -/* Get the value of h-fcc2. */ - -UQI -sparc64_h_fcc2_get (SIM_CPU *current_cpu) -{ - return CPU (h_fcc2); -} - -/* Set a value for h-fcc2. */ - -void -sparc64_h_fcc2_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fcc2) = newval; -} - -/* Get the value of h-fcc3. */ - -UQI -sparc64_h_fcc3_get (SIM_CPU *current_cpu) -{ - return CPU (h_fcc3); -} - -/* Set a value for h-fcc3. */ - -void -sparc64_h_fcc3_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fcc3) = newval; -} - -/* Get the value of h-fsr-rd. */ - -UQI -sparc64_h_fsr_rd_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_rd); -} - -/* Set a value for h-fsr-rd. */ - -void -sparc64_h_fsr_rd_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fsr_rd) = newval; -} - -/* Get the value of h-fsr-tem. */ - -UQI -sparc64_h_fsr_tem_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_tem); -} - -/* Set a value for h-fsr-tem. */ - -void -sparc64_h_fsr_tem_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fsr_tem) = newval; -} - -/* Get the value of h-fsr-ns. */ - -BI -sparc64_h_fsr_ns_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_ns); -} - -/* Set a value for h-fsr-ns. */ - -void -sparc64_h_fsr_ns_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_fsr_ns) = newval; -} - -/* Get the value of h-fsr-ver. */ - -UQI -sparc64_h_fsr_ver_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_ver); -} - -/* Set a value for h-fsr-ver. */ - -void -sparc64_h_fsr_ver_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fsr_ver) = newval; -} - -/* Get the value of h-fsr-ftt. */ - -UQI -sparc64_h_fsr_ftt_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_ftt); -} - -/* Set a value for h-fsr-ftt. */ - -void -sparc64_h_fsr_ftt_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fsr_ftt) = newval; -} - -/* Get the value of h-fsr-qne. */ - -BI -sparc64_h_fsr_qne_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_qne); -} - -/* Set a value for h-fsr-qne. */ - -void -sparc64_h_fsr_qne_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_fsr_qne) = newval; -} - -/* Get the value of h-fsr-aexc. */ - -UQI -sparc64_h_fsr_aexc_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_aexc); -} - -/* Set a value for h-fsr-aexc. */ - -void -sparc64_h_fsr_aexc_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fsr_aexc) = newval; -} - -/* Get the value of h-fsr-cexc. */ - -UQI -sparc64_h_fsr_cexc_get (SIM_CPU *current_cpu) -{ - return CPU (h_fsr_cexc); -} - -/* Set a value for h-fsr-cexc. */ - -void -sparc64_h_fsr_cexc_set (SIM_CPU *current_cpu, UQI newval) -{ - CPU (h_fsr_cexc) = newval; -} - -/* Get the value of h-fpsr-fef. */ - -BI -sparc64_h_fpsr_fef_get (SIM_CPU *current_cpu) -{ - return CPU (h_fpsr_fef); -} - -/* Set a value for h-fpsr-fef. */ - -void -sparc64_h_fpsr_fef_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_fpsr_fef) = newval; -} - -/* Get the value of h-fpsr-du. */ - -BI -sparc64_h_fpsr_du_get (SIM_CPU *current_cpu) -{ - return CPU (h_fpsr_du); -} - -/* Set a value for h-fpsr-du. */ - -void -sparc64_h_fpsr_du_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_fpsr_du) = newval; -} - -/* Get the value of h-fpsr-dl. */ - -BI -sparc64_h_fpsr_dl_get (SIM_CPU *current_cpu) -{ - return CPU (h_fpsr_dl); -} - -/* Set a value for h-fpsr-dl. */ - -void -sparc64_h_fpsr_dl_set (SIM_CPU *current_cpu, BI newval) -{ - CPU (h_fpsr_dl) = newval; -} - -/* Get the value of h-fpsr. */ - -UQI -sparc64_h_fpsr_get (SIM_CPU *current_cpu) -{ - return GET_H_FPSR (); -} - -/* Set a value for h-fpsr. */ - -void -sparc64_h_fpsr_set (SIM_CPU *current_cpu, UQI newval) -{ - SET_H_FPSR (newval); -} - -/* Record trace results for INSN. */ - -void -sparc64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, - int *indices, TRACE_RECORD *tr) -{ -} diff --git a/sim/sparc/cpu64.h b/sim/sparc/cpu64.h deleted file mode 100644 index 1a6e4a9..0000000 --- a/sim/sparc/cpu64.h +++ /dev/null @@ -1,818 +0,0 @@ -/* CPU family header for sparc64. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef CPU_SPARC64_H -#define CPU_SPARC64_H - -/* Maximum number of instructions that are fetched at a time. - This is for LIW type instructions sets (e.g. m32r). */ -#define MAX_LIW_INSNS 1 - -/* Maximum number of instructions that can be executed in parallel. */ -#define MAX_PARALLEL_INSNS 1 - -/* CPU state information. */ -typedef struct { - /* Hardware elements. */ - struct { - /* program counter */ - USI h_pc; -#define GET_H_PC() CPU (h_pc) -#define SET_H_PC(x) (CPU (h_pc) = (x)) - /* next pc */ - SI h_npc; -#define GET_H_NPC() CPU (h_npc) -#define SET_H_NPC(x) (CPU (h_npc) = (x)) -/* GET_H_GR macro user-written */ -/* SET_H_GR macro user-written */ - /* icc carry bit */ - BI h_icc_c; -#define GET_H_ICC_C() CPU (h_icc_c) -#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x)) - /* icc negative bit */ - BI h_icc_n; -#define GET_H_ICC_N() CPU (h_icc_n) -#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x)) - /* icc overflow bit */ - BI h_icc_v; -#define GET_H_ICC_V() CPU (h_icc_v) -#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x)) - /* icc zero bit */ - BI h_icc_z; -#define GET_H_ICC_Z() CPU (h_icc_z) -#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x)) - /* xcc carry bit */ - BI h_xcc_c; -#define GET_H_XCC_C() CPU (h_xcc_c) -#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x)) - /* xcc negative bit */ - BI h_xcc_n; -#define GET_H_XCC_N() CPU (h_xcc_n) -#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x)) - /* xcc overflow bit */ - BI h_xcc_v; -#define GET_H_XCC_V() CPU (h_xcc_v) -#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x)) - /* xcc zero bit */ - BI h_xcc_z; -#define GET_H_XCC_Z() CPU (h_xcc_z) -#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x)) -/* GET_H_Y macro user-written */ -/* SET_H_Y macro user-written */ - /* ancilliary state registers */ - SI h_asr[32]; -#define GET_H_ASR(a1) CPU (h_asr)[a1] -#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x)) - /* annul next insn? - assists execution */ - BI h_annul_p; -#define GET_H_ANNUL_P() CPU (h_annul_p) -#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x)) - /* floating point regs */ - SF h_fr[32]; -#define GET_H_FR(a1) CPU (h_fr)[a1] -#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) - /* version */ - UDI h_ver; -#define GET_H_VER() CPU (h_ver) -#define SET_H_VER(x) (CPU (h_ver) = (x)) - /* processor state */ - UDI h_pstate; -#define GET_H_PSTATE() CPU (h_pstate) -#define SET_H_PSTATE(x) (CPU (h_pstate) = (x)) - /* trap base address */ - UDI h_tba; -#define GET_H_TBA() CPU (h_tba) -#define SET_H_TBA(x) (CPU (h_tba) = (x)) - /* trap type */ - UDI h_tt; -#define GET_H_TT() CPU (h_tt) -#define SET_H_TT(x) (CPU (h_tt) = (x)) - /* trap pc */ - UDI h_tpc; -#define GET_H_TPC() CPU (h_tpc) -#define SET_H_TPC(x) (CPU (h_tpc) = (x)) - /* trap npc */ - UDI h_tnpc; -#define GET_H_TNPC() CPU (h_tnpc) -#define SET_H_TNPC(x) (CPU (h_tnpc) = (x)) - /* trap state */ - UDI h_tstate; -#define GET_H_TSTATE() CPU (h_tstate) -#define SET_H_TSTATE(x) (CPU (h_tstate) = (x)) - /* trap level */ - UQI h_tl; -#define GET_H_TL() CPU (h_tl) -#define SET_H_TL(x) (CPU (h_tl) = (x)) - /* address space identifier */ - UQI h_asi; -#define GET_H_ASI() CPU (h_asi) -#define SET_H_ASI(x) (CPU (h_asi) = (x)) - /* tick counter */ - UDI h_tick; -#define GET_H_TICK() CPU (h_tick) -#define SET_H_TICK(x) (CPU (h_tick) = (x)) - /* savable window registers */ - UDI h_cansave; -#define GET_H_CANSAVE() CPU (h_cansave) -#define SET_H_CANSAVE(x) (CPU (h_cansave) = (x)) - /* restorable window registers */ - UDI h_canrestore; -#define GET_H_CANRESTORE() CPU (h_canrestore) -#define SET_H_CANRESTORE(x) (CPU (h_canrestore) = (x)) - /* other window registers */ - UDI h_otherwin; -#define GET_H_OTHERWIN() CPU (h_otherwin) -#define SET_H_OTHERWIN(x) (CPU (h_otherwin) = (x)) - /* clean window registers */ - UDI h_cleanwin; -#define GET_H_CLEANWIN() CPU (h_cleanwin) -#define SET_H_CLEANWIN(x) (CPU (h_cleanwin) = (x)) - /* window state */ - UDI h_wstate; -#define GET_H_WSTATE() CPU (h_wstate) -#define SET_H_WSTATE(x) (CPU (h_wstate) = (x)) - /* */ - UQI h_fcc0; -#define GET_H_FCC0() CPU (h_fcc0) -#define SET_H_FCC0(x) (CPU (h_fcc0) = (x)) - /* */ - UQI h_fcc1; -#define GET_H_FCC1() CPU (h_fcc1) -#define SET_H_FCC1(x) (CPU (h_fcc1) = (x)) - /* */ - UQI h_fcc2; -#define GET_H_FCC2() CPU (h_fcc2) -#define SET_H_FCC2(x) (CPU (h_fcc2) = (x)) - /* */ - UQI h_fcc3; -#define GET_H_FCC3() CPU (h_fcc3) -#define SET_H_FCC3(x) (CPU (h_fcc3) = (x)) - /* fsr rounding direction */ - UQI h_fsr_rd; -#define GET_H_FSR_RD() CPU (h_fsr_rd) -#define SET_H_FSR_RD(x) (CPU (h_fsr_rd) = (x)) - /* fsr trap enable mask */ - UQI h_fsr_tem; -#define GET_H_FSR_TEM() CPU (h_fsr_tem) -#define SET_H_FSR_TEM(x) (CPU (h_fsr_tem) = (x)) - /* fsr nonstandard fp */ - BI h_fsr_ns; -#define GET_H_FSR_NS() CPU (h_fsr_ns) -#define SET_H_FSR_NS(x) (CPU (h_fsr_ns) = (x)) - /* fsr version */ - UQI h_fsr_ver; -#define GET_H_FSR_VER() CPU (h_fsr_ver) -#define SET_H_FSR_VER(x) (CPU (h_fsr_ver) = (x)) - /* fsr fp trap type */ - UQI h_fsr_ftt; -#define GET_H_FSR_FTT() CPU (h_fsr_ftt) -#define SET_H_FSR_FTT(x) (CPU (h_fsr_ftt) = (x)) - /* fsr queue not empty */ - BI h_fsr_qne; -#define GET_H_FSR_QNE() CPU (h_fsr_qne) -#define SET_H_FSR_QNE(x) (CPU (h_fsr_qne) = (x)) - /* fsr accrued exception */ - UQI h_fsr_aexc; -#define GET_H_FSR_AEXC() CPU (h_fsr_aexc) -#define SET_H_FSR_AEXC(x) (CPU (h_fsr_aexc) = (x)) - /* fsr current exception */ - UQI h_fsr_cexc; -#define GET_H_FSR_CEXC() CPU (h_fsr_cexc) -#define SET_H_FSR_CEXC(x) (CPU (h_fsr_cexc) = (x)) - /* fpsr enable fp */ - BI h_fpsr_fef; -#define GET_H_FPSR_FEF() CPU (h_fpsr_fef) -#define SET_H_FPSR_FEF(x) (CPU (h_fpsr_fef) = (x)) - /* fpsr dirty upper */ - BI h_fpsr_du; -#define GET_H_FPSR_DU() CPU (h_fpsr_du) -#define SET_H_FPSR_DU(x) (CPU (h_fpsr_du) = (x)) - /* fpsr dirty lower */ - BI h_fpsr_dl; -#define GET_H_FPSR_DL() CPU (h_fpsr_dl) -#define SET_H_FPSR_DL(x) (CPU (h_fpsr_dl) = (x)) -/* GET_H_FPSR macro user-written */ -/* SET_H_FPSR macro user-written */ - } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) -} SPARC64_CPU_DATA; - -/* Cover fns for register access. */ -USI sparc64_h_pc_get (SIM_CPU *); -void sparc64_h_pc_set (SIM_CPU *, USI); -SI sparc64_h_npc_get (SIM_CPU *); -void sparc64_h_npc_set (SIM_CPU *, SI); -SI sparc64_h_gr_get (SIM_CPU *, UINT); -void sparc64_h_gr_set (SIM_CPU *, UINT, SI); -BI sparc64_h_icc_c_get (SIM_CPU *); -void sparc64_h_icc_c_set (SIM_CPU *, BI); -BI sparc64_h_icc_n_get (SIM_CPU *); -void sparc64_h_icc_n_set (SIM_CPU *, BI); -BI sparc64_h_icc_v_get (SIM_CPU *); -void sparc64_h_icc_v_set (SIM_CPU *, BI); -BI sparc64_h_icc_z_get (SIM_CPU *); -void sparc64_h_icc_z_set (SIM_CPU *, BI); -BI sparc64_h_xcc_c_get (SIM_CPU *); -void sparc64_h_xcc_c_set (SIM_CPU *, BI); -BI sparc64_h_xcc_n_get (SIM_CPU *); -void sparc64_h_xcc_n_set (SIM_CPU *, BI); -BI sparc64_h_xcc_v_get (SIM_CPU *); -void sparc64_h_xcc_v_set (SIM_CPU *, BI); -BI sparc64_h_xcc_z_get (SIM_CPU *); -void sparc64_h_xcc_z_set (SIM_CPU *, BI); -SI sparc64_h_y_get (SIM_CPU *); -void sparc64_h_y_set (SIM_CPU *, SI); -SI sparc64_h_asr_get (SIM_CPU *, UINT); -void sparc64_h_asr_set (SIM_CPU *, UINT, SI); -BI sparc64_h_annul_p_get (SIM_CPU *); -void sparc64_h_annul_p_set (SIM_CPU *, BI); -SF sparc64_h_fr_get (SIM_CPU *, UINT); -void sparc64_h_fr_set (SIM_CPU *, UINT, SF); -UDI sparc64_h_ver_get (SIM_CPU *); -void sparc64_h_ver_set (SIM_CPU *, UDI); -UDI sparc64_h_pstate_get (SIM_CPU *); -void sparc64_h_pstate_set (SIM_CPU *, UDI); -UDI sparc64_h_tba_get (SIM_CPU *); -void sparc64_h_tba_set (SIM_CPU *, UDI); -UDI sparc64_h_tt_get (SIM_CPU *); -void sparc64_h_tt_set (SIM_CPU *, UDI); -UDI sparc64_h_tpc_get (SIM_CPU *); -void sparc64_h_tpc_set (SIM_CPU *, UDI); -UDI sparc64_h_tnpc_get (SIM_CPU *); -void sparc64_h_tnpc_set (SIM_CPU *, UDI); -UDI sparc64_h_tstate_get (SIM_CPU *); -void sparc64_h_tstate_set (SIM_CPU *, UDI); -UQI sparc64_h_tl_get (SIM_CPU *); -void sparc64_h_tl_set (SIM_CPU *, UQI); -UQI sparc64_h_asi_get (SIM_CPU *); -void sparc64_h_asi_set (SIM_CPU *, UQI); -UDI sparc64_h_tick_get (SIM_CPU *); -void sparc64_h_tick_set (SIM_CPU *, UDI); -UDI sparc64_h_cansave_get (SIM_CPU *); -void sparc64_h_cansave_set (SIM_CPU *, UDI); -UDI sparc64_h_canrestore_get (SIM_CPU *); -void sparc64_h_canrestore_set (SIM_CPU *, UDI); -UDI sparc64_h_otherwin_get (SIM_CPU *); -void sparc64_h_otherwin_set (SIM_CPU *, UDI); -UDI sparc64_h_cleanwin_get (SIM_CPU *); -void sparc64_h_cleanwin_set (SIM_CPU *, UDI); -UDI sparc64_h_wstate_get (SIM_CPU *); -void sparc64_h_wstate_set (SIM_CPU *, UDI); -UQI sparc64_h_fcc0_get (SIM_CPU *); -void sparc64_h_fcc0_set (SIM_CPU *, UQI); -UQI sparc64_h_fcc1_get (SIM_CPU *); -void sparc64_h_fcc1_set (SIM_CPU *, UQI); -UQI sparc64_h_fcc2_get (SIM_CPU *); -void sparc64_h_fcc2_set (SIM_CPU *, UQI); -UQI sparc64_h_fcc3_get (SIM_CPU *); -void sparc64_h_fcc3_set (SIM_CPU *, UQI); -UQI sparc64_h_fsr_rd_get (SIM_CPU *); -void sparc64_h_fsr_rd_set (SIM_CPU *, UQI); -UQI sparc64_h_fsr_tem_get (SIM_CPU *); -void sparc64_h_fsr_tem_set (SIM_CPU *, UQI); -BI sparc64_h_fsr_ns_get (SIM_CPU *); -void sparc64_h_fsr_ns_set (SIM_CPU *, BI); -UQI sparc64_h_fsr_ver_get (SIM_CPU *); -void sparc64_h_fsr_ver_set (SIM_CPU *, UQI); -UQI sparc64_h_fsr_ftt_get (SIM_CPU *); -void sparc64_h_fsr_ftt_set (SIM_CPU *, UQI); -BI sparc64_h_fsr_qne_get (SIM_CPU *); -void sparc64_h_fsr_qne_set (SIM_CPU *, BI); -UQI sparc64_h_fsr_aexc_get (SIM_CPU *); -void sparc64_h_fsr_aexc_set (SIM_CPU *, UQI); -UQI sparc64_h_fsr_cexc_get (SIM_CPU *); -void sparc64_h_fsr_cexc_set (SIM_CPU *, UQI); -BI sparc64_h_fpsr_fef_get (SIM_CPU *); -void sparc64_h_fpsr_fef_set (SIM_CPU *, BI); -BI sparc64_h_fpsr_du_get (SIM_CPU *); -void sparc64_h_fpsr_du_set (SIM_CPU *, BI); -BI sparc64_h_fpsr_dl_get (SIM_CPU *); -void sparc64_h_fpsr_dl_set (SIM_CPU *, BI); -UQI sparc64_h_fpsr_get (SIM_CPU *); -void sparc64_h_fpsr_set (SIM_CPU *, UQI); - -/* These must be hand-written. */ -extern CPUREG_FETCH_FN sparc64_fetch_register; -extern CPUREG_STORE_FN sparc64_store_register; - -typedef struct { - int empty; -} MODEL_SPARC64_DEF_DATA; - -/* The ARGBUF struct. */ -struct argbuf { - /* These are the baseclass definitions. */ - IADDR addr; - const IDESC *idesc; - char trace_p; - char profile_p; - /* cpu specific data follows */ - CGEN_INSN_INT insn; - int written; -}; - -/* A cached insn. - - ??? SCACHE used to contain more than just argbuf. We could delete the - type entirely and always just use ARGBUF, but for future concerns and as - a level of abstraction it is left in. */ - -struct scache { - struct argbuf argbuf; -}; - -/* Macros to simplify extraction, reading and semantic code. - These define and assign the local vars that contain the insn's fields. */ - -#define EXTRACT_IFMT_EMPTY_VARS \ - /* Instruction fields. */ \ - unsigned int length; -#define EXTRACT_IFMT_EMPTY_CODE \ - length = 0; \ - -#define EXTRACT_IFMT_BEQZ_VARS \ - /* Instruction fields. */ \ - INT f_disp16; \ - UINT f_disp16_hi; \ - UINT f_disp16_lo; \ - UINT f_rs1; \ - UINT f_p; \ - UINT f_op2; \ - UINT f_fmt2_rcond; \ - INT f_bpr_res28_1; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_BEQZ_CODE \ - length = 4; \ - f_disp16_hi = EXTRACT_UINT (insn, 32, 10, 2); \ - f_disp16_lo = EXTRACT_UINT (insn, 32, 18, 14); \ -do {\ - f_disp16 = ((((f_disp16_hi) << (14))) | (f_disp16_low));\ -} while (0);\ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_p = EXTRACT_UINT (insn, 32, 19, 1); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_fmt2_rcond = EXTRACT_UINT (insn, 32, 27, 3); \ - f_bpr_res28_1 = EXTRACT_INT (insn, 32, 28, 1); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_BPCC_BA_VARS \ - /* Instruction fields. */ \ - INT f_disp19; \ - UINT f_p; \ - UINT f_fmt2_cc0; \ - UINT f_fmt2_cc1; \ - UINT f_op2; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_BPCC_BA_CODE \ - length = 4; \ - f_disp19 = EXTRACT_INT (insn, 32, 13, 19); \ - f_p = EXTRACT_UINT (insn, 32, 19, 1); \ - f_fmt2_cc0 = EXTRACT_UINT (insn, 32, 20, 1); \ - f_fmt2_cc1 = EXTRACT_UINT (insn, 32, 21, 1); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_DONE_VARS \ - /* Instruction fields. */ \ - INT f_res_18_19; \ - UINT f_op3; \ - UINT f_fcn; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_DONE_CODE \ - length = 4; \ - f_res_18_19 = EXTRACT_INT (insn, 32, 18, 19); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fcn = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FLUSH_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FLUSH_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FLUSH_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FLUSH_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FLUSHW_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FLUSHW_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_IMPDEP1_VARS \ - /* Instruction fields. */ \ - INT f_impdep19; \ - UINT f_op3; \ - INT f_impdep5; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_IMPDEP1_CODE \ - length = 4; \ - f_impdep19 = EXTRACT_INT (insn, 32, 18, 19); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_impdep5 = EXTRACT_INT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_MEMBAR_VARS \ - /* Instruction fields. */ \ - UINT f_membarmask; \ - INT f_membar_res12_6; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_MEMBAR_CODE \ - length = 4; \ - f_membarmask = EXTRACT_UINT (insn, 32, 6, 7); \ - f_membar_res12_6 = EXTRACT_INT (insn, 32, 12, 6); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_MOVA_ICC_ICC_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_fmt4_res10_6; \ - UINT f_fmt4_cc1_0; \ - UINT f_i; \ - UINT f_fmt4_cc2; \ - UINT f_op3; \ - UINT f_fmt2_cond; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_MOVA_ICC_ICC_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_fmt4_res10_6 = EXTRACT_INT (insn, 32, 10, 6); \ - f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS \ - /* Instruction fields. */ \ - INT f_simm11; \ - UINT f_fmt4_cc1_0; \ - UINT f_i; \ - UINT f_fmt4_cc2; \ - UINT f_op3; \ - UINT f_fmt2_cond; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE \ - length = 4; \ - f_simm11 = EXTRACT_INT (insn, 32, 10, 11); \ - f_fmt4_cc1_0 = EXTRACT_UINT (insn, 32, 12, 2); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_fmt4_cc2 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDSB_REG_REG_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDSB_REG_REG_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDSB_REG_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDSB_REG_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - UINT f_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDD_REG_REG_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDD_REG_REG_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDD_REG_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDD_REG_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - UINT f_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - UINT f_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_asi = EXTRACT_UINT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_SETHI_VARS \ - /* Instruction fields. */ \ - INT f_hi22; \ - UINT f_op2; \ - UINT f_rd; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_SETHI_CODE \ - length = 4; \ - f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_rd = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_UNIMP_VARS \ - /* Instruction fields. */ \ - INT f_imm22; \ - UINT f_op2; \ - UINT f_rd_res; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_UNIMP_CODE \ - length = 4; \ - f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_CALL_VARS \ - /* Instruction fields. */ \ - SI f_disp30; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_CALL_CODE \ - length = 4; \ - f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_BA_VARS \ - /* Instruction fields. */ \ - SI f_disp22; \ - UINT f_op2; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_BA_CODE \ - length = 4; \ - f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \ - f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_TA_VARS \ - /* Instruction fields. */ \ - UINT f_rs2; \ - INT f_res_asi; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_TA_CODE \ - length = 4; \ - f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \ - f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -#define EXTRACT_IFMT_TA_IMM_VARS \ - /* Instruction fields. */ \ - INT f_simm13; \ - UINT f_i; \ - UINT f_rs1; \ - UINT f_op3; \ - UINT f_fmt2_cond; \ - UINT f_a; \ - UINT f_op; \ - unsigned int length; -#define EXTRACT_IFMT_TA_IMM_CODE \ - length = 4; \ - f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \ - f_i = EXTRACT_UINT (insn, 32, 13, 1); \ - f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \ - f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \ - f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \ - f_a = EXTRACT_UINT (insn, 32, 29, 1); \ - f_op = EXTRACT_UINT (insn, 32, 31, 2); \ - -/* Collection of various things for the trace handler to use. */ - -typedef struct trace_record { - IADDR pc; - /* FIXME:wip */ -} TRACE_RECORD; - -#endif /* CPU_SPARC64_H */ diff --git a/sim/sparc/cpuall.h b/sim/sparc/cpuall.h deleted file mode 100644 index f6ae0c5..0000000 --- a/sim/sparc/cpuall.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Simulator CPU header for sparc. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef SPARC_CPUALL_H -#define SPARC_CPUALL_H - -/* Include files for each cpu family. */ - -#ifdef WANT_CPU_SPARC32 -#include "eng32.h" -#include "cgen-engine.h" -#include "cpu32.h" -#include "decode32.h" -#endif - -extern const MACH sparc_v8_mach; -extern const MACH sparclite_mach; - -#ifndef WANT_CPU -/* The ARGBUF struct. */ -struct argbuf { - /* These are the baseclass definitions. */ - IADDR addr; - const IDESC *idesc; - char trace_p; - char profile_p; - /* cpu specific data follows */ -}; -#endif - -#ifndef WANT_CPU -/* A cached insn. - - ??? SCACHE used to contain more than just argbuf. We could delete the - type entirely and always just use ARGBUF, but for future concerns and as - a level of abstraction it is left in. */ - -struct scache { - struct argbuf argbuf; -}; -#endif - -#endif /* SPARC_CPUALL_H */ diff --git a/sim/sparc/decode32.c b/sim/sparc/decode32.c deleted file mode 100644 index 9d85b99..0000000 --- a/sim/sparc/decode32.c +++ /dev/null @@ -1,1278 +0,0 @@ -/* Simulator instruction decoder for sparc32. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc32 -#define WANT_CPU_SPARC32 - -#include "sim-main.h" -#include "sim-assert.h" - -/* FIXME: Need to review choices for the following. */ - -#if WITH_SEM_SWITCH_FULL -#define FULL(fn) -#else -#define FULL(fn) CONCAT3 (sparc32,_sem_,fn) , -#endif - -#if WITH_FAST -#if WITH_SEM_SWITCH_FAST -#define FAST(fn) -#else -#define FAST(fn) CONCAT3 (sparc32,_semf_,fn) , /* f for fast */ -#endif -#else -#define FAST(fn) -#endif - -/* The instruction descriptor array. - This is computed at runtime. Space for it is not malloc'd to save a - teensy bit of cpu in the decoder. Moving it to malloc space is trivial - but won't be done until necessary (we don't currently support the runtime - addition of instructions nor an SMP machine with different cpus). */ -static IDESC sparc32_insn_data[SPARC32_INSN_MAX]; - -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (SPARC32_,insn) -#define TYPE(insn) CONCAT2 (SPARC_,insn) - -/* Commas between elements are contained in the macros. - Some of these are conditionally compiled out. */ - -static const struct insn_sem sparc32_insn_sem[] = -{ - { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, - { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, - { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, - { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, - { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, - { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, - { TYPE (INSN_RD_ASR), IDX (INSN_RD_ASR), FULL (rd_asr) FAST (rd_asr) }, - { TYPE (INSN_WR_ASR), IDX (INSN_WR_ASR), FULL (wr_asr) FAST (wr_asr) }, - { TYPE (INSN_WR_ASR_IMM), IDX (INSN_WR_ASR_IMM), FULL (wr_asr_imm) FAST (wr_asr_imm) }, - { TYPE (INSN_RD_PSR), IDX (INSN_RD_PSR), FULL (rd_psr) FAST (rd_psr) }, - { TYPE (INSN_WR_PSR), IDX (INSN_WR_PSR), FULL (wr_psr) FAST (wr_psr) }, - { TYPE (INSN_WR_PSR_IMM), IDX (INSN_WR_PSR_IMM), FULL (wr_psr_imm) FAST (wr_psr_imm) }, - { TYPE (INSN_RD_WIM), IDX (INSN_RD_WIM), FULL (rd_wim) FAST (rd_wim) }, - { TYPE (INSN_WR_WIM), IDX (INSN_WR_WIM), FULL (wr_wim) FAST (wr_wim) }, - { TYPE (INSN_WR_WIM_IMM), IDX (INSN_WR_WIM_IMM), FULL (wr_wim_imm) FAST (wr_wim_imm) }, - { TYPE (INSN_RD_TBR), IDX (INSN_RD_TBR), FULL (rd_tbr) FAST (rd_tbr) }, - { TYPE (INSN_WR_TBR), IDX (INSN_WR_TBR), FULL (wr_tbr) FAST (wr_tbr) }, - { TYPE (INSN_WR_TBR_IMM), IDX (INSN_WR_TBR_IMM), FULL (wr_tbr_imm) FAST (wr_tbr_imm) }, - { TYPE (INSN_LDSTUB_REG_REG), IDX (INSN_LDSTUB_REG_REG), FULL (ldstub_reg_reg) FAST (ldstub_reg_reg) }, - { TYPE (INSN_LDSTUB_REG_IMM), IDX (INSN_LDSTUB_REG_IMM), FULL (ldstub_reg_imm) FAST (ldstub_reg_imm) }, - { TYPE (INSN_LDSTUB_REG_REG_ASI), IDX (INSN_LDSTUB_REG_REG_ASI), FULL (ldstub_reg_reg_asi) FAST (ldstub_reg_reg_asi) }, - { TYPE (INSN_SWAP_REG_REG), IDX (INSN_SWAP_REG_REG), FULL (swap_reg_reg) FAST (swap_reg_reg) }, - { TYPE (INSN_SWAP_REG_IMM), IDX (INSN_SWAP_REG_IMM), FULL (swap_reg_imm) FAST (swap_reg_imm) }, - { TYPE (INSN_SWAP_REG_REG_ASI), IDX (INSN_SWAP_REG_REG_ASI), FULL (swap_reg_reg_asi) FAST (swap_reg_reg_asi) }, - { TYPE (INSN_LDSB_REG_REG), IDX (INSN_LDSB_REG_REG), FULL (ldsb_reg_reg) FAST (ldsb_reg_reg) }, - { TYPE (INSN_LDSB_REG_IMM), IDX (INSN_LDSB_REG_IMM), FULL (ldsb_reg_imm) FAST (ldsb_reg_imm) }, - { TYPE (INSN_LDSB_REG_REG_ASI), IDX (INSN_LDSB_REG_REG_ASI), FULL (ldsb_reg_reg_asi) FAST (ldsb_reg_reg_asi) }, - { TYPE (INSN_LDUB_REG_REG), IDX (INSN_LDUB_REG_REG), FULL (ldub_reg_reg) FAST (ldub_reg_reg) }, - { TYPE (INSN_LDUB_REG_IMM), IDX (INSN_LDUB_REG_IMM), FULL (ldub_reg_imm) FAST (ldub_reg_imm) }, - { TYPE (INSN_LDUB_REG_REG_ASI), IDX (INSN_LDUB_REG_REG_ASI), FULL (ldub_reg_reg_asi) FAST (ldub_reg_reg_asi) }, - { TYPE (INSN_LDSH_REG_REG), IDX (INSN_LDSH_REG_REG), FULL (ldsh_reg_reg) FAST (ldsh_reg_reg) }, - { TYPE (INSN_LDSH_REG_IMM), IDX (INSN_LDSH_REG_IMM), FULL (ldsh_reg_imm) FAST (ldsh_reg_imm) }, - { TYPE (INSN_LDSH_REG_REG_ASI), IDX (INSN_LDSH_REG_REG_ASI), FULL (ldsh_reg_reg_asi) FAST (ldsh_reg_reg_asi) }, - { TYPE (INSN_LDUH_REG_REG), IDX (INSN_LDUH_REG_REG), FULL (lduh_reg_reg) FAST (lduh_reg_reg) }, - { TYPE (INSN_LDUH_REG_IMM), IDX (INSN_LDUH_REG_IMM), FULL (lduh_reg_imm) FAST (lduh_reg_imm) }, - { TYPE (INSN_LDUH_REG_REG_ASI), IDX (INSN_LDUH_REG_REG_ASI), FULL (lduh_reg_reg_asi) FAST (lduh_reg_reg_asi) }, - { TYPE (INSN_LDSW_REG_REG), IDX (INSN_LDSW_REG_REG), FULL (ldsw_reg_reg) FAST (ldsw_reg_reg) }, - { TYPE (INSN_LDSW_REG_IMM), IDX (INSN_LDSW_REG_IMM), FULL (ldsw_reg_imm) FAST (ldsw_reg_imm) }, - { TYPE (INSN_LDSW_REG_REG_ASI), IDX (INSN_LDSW_REG_REG_ASI), FULL (ldsw_reg_reg_asi) FAST (ldsw_reg_reg_asi) }, - { TYPE (INSN_LDUW_REG_REG), IDX (INSN_LDUW_REG_REG), FULL (lduw_reg_reg) FAST (lduw_reg_reg) }, - { TYPE (INSN_LDUW_REG_IMM), IDX (INSN_LDUW_REG_IMM), FULL (lduw_reg_imm) FAST (lduw_reg_imm) }, - { TYPE (INSN_LDUW_REG_REG_ASI), IDX (INSN_LDUW_REG_REG_ASI), FULL (lduw_reg_reg_asi) FAST (lduw_reg_reg_asi) }, - { TYPE (INSN_LDD_REG_REG), IDX (INSN_LDD_REG_REG), FULL (ldd_reg_reg) FAST (ldd_reg_reg) }, - { TYPE (INSN_LDD_REG_IMM), IDX (INSN_LDD_REG_IMM), FULL (ldd_reg_imm) FAST (ldd_reg_imm) }, - { TYPE (INSN_LDD_REG_REG_ASI), IDX (INSN_LDD_REG_REG_ASI), FULL (ldd_reg_reg_asi) FAST (ldd_reg_reg_asi) }, - { TYPE (INSN_STB_REG_REG), IDX (INSN_STB_REG_REG), FULL (stb_reg_reg) FAST (stb_reg_reg) }, - { TYPE (INSN_STB_REG_IMM), IDX (INSN_STB_REG_IMM), FULL (stb_reg_imm) FAST (stb_reg_imm) }, - { TYPE (INSN_STB_REG_REG_ASI), IDX (INSN_STB_REG_REG_ASI), FULL (stb_reg_reg_asi) FAST (stb_reg_reg_asi) }, - { TYPE (INSN_STH_REG_REG), IDX (INSN_STH_REG_REG), FULL (sth_reg_reg) FAST (sth_reg_reg) }, - { TYPE (INSN_STH_REG_IMM), IDX (INSN_STH_REG_IMM), FULL (sth_reg_imm) FAST (sth_reg_imm) }, - { TYPE (INSN_STH_REG_REG_ASI), IDX (INSN_STH_REG_REG_ASI), FULL (sth_reg_reg_asi) FAST (sth_reg_reg_asi) }, - { TYPE (INSN_ST_REG_REG), IDX (INSN_ST_REG_REG), FULL (st_reg_reg) FAST (st_reg_reg) }, - { TYPE (INSN_ST_REG_IMM), IDX (INSN_ST_REG_IMM), FULL (st_reg_imm) FAST (st_reg_imm) }, - { TYPE (INSN_ST_REG_REG_ASI), IDX (INSN_ST_REG_REG_ASI), FULL (st_reg_reg_asi) FAST (st_reg_reg_asi) }, - { TYPE (INSN_STD_REG_REG), IDX (INSN_STD_REG_REG), FULL (std_reg_reg) FAST (std_reg_reg) }, - { TYPE (INSN_STD_REG_IMM), IDX (INSN_STD_REG_IMM), FULL (std_reg_imm) FAST (std_reg_imm) }, - { TYPE (INSN_STD_REG_REG_ASI), IDX (INSN_STD_REG_REG_ASI), FULL (std_reg_reg_asi) FAST (std_reg_reg_asi) }, - { TYPE (INSN_FP_LD_REG_REG), IDX (INSN_FP_LD_REG_REG), FULL (fp_ld_reg_reg) FAST (fp_ld_reg_reg) }, - { TYPE (INSN_FP_LD_REG_IMM), IDX (INSN_FP_LD_REG_IMM), FULL (fp_ld_reg_imm) FAST (fp_ld_reg_imm) }, - { TYPE (INSN_FP_LD_REG_REG_ASI), IDX (INSN_FP_LD_REG_REG_ASI), FULL (fp_ld_reg_reg_asi) FAST (fp_ld_reg_reg_asi) }, - { TYPE (INSN_SETHI), IDX (INSN_SETHI), FULL (sethi) FAST (sethi) }, - { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) }, - { TYPE (INSN_ADD_IMM), IDX (INSN_ADD_IMM), FULL (add_imm) FAST (add_imm) }, - { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) }, - { TYPE (INSN_SUB_IMM), IDX (INSN_SUB_IMM), FULL (sub_imm) FAST (sub_imm) }, - { TYPE (INSN_ADDCC), IDX (INSN_ADDCC), FULL (addcc) FAST (addcc) }, - { TYPE (INSN_ADDCC_IMM), IDX (INSN_ADDCC_IMM), FULL (addcc_imm) FAST (addcc_imm) }, - { TYPE (INSN_SUBCC), IDX (INSN_SUBCC), FULL (subcc) FAST (subcc) }, - { TYPE (INSN_SUBCC_IMM), IDX (INSN_SUBCC_IMM), FULL (subcc_imm) FAST (subcc_imm) }, - { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) }, - { TYPE (INSN_ADDX_IMM), IDX (INSN_ADDX_IMM), FULL (addx_imm) FAST (addx_imm) }, - { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) }, - { TYPE (INSN_SUBX_IMM), IDX (INSN_SUBX_IMM), FULL (subx_imm) FAST (subx_imm) }, - { TYPE (INSN_ADDXCC), IDX (INSN_ADDXCC), FULL (addxcc) FAST (addxcc) }, - { TYPE (INSN_ADDXCC_IMM), IDX (INSN_ADDXCC_IMM), FULL (addxcc_imm) FAST (addxcc_imm) }, - { TYPE (INSN_SUBXCC), IDX (INSN_SUBXCC), FULL (subxcc) FAST (subxcc) }, - { TYPE (INSN_SUBXCC_IMM), IDX (INSN_SUBXCC_IMM), FULL (subxcc_imm) FAST (subxcc_imm) }, - { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, - { TYPE (INSN_AND_IMM), IDX (INSN_AND_IMM), FULL (and_imm) FAST (and_imm) }, - { TYPE (INSN_ANDCC), IDX (INSN_ANDCC), FULL (andcc) FAST (andcc) }, - { TYPE (INSN_ANDCC_IMM), IDX (INSN_ANDCC_IMM), FULL (andcc_imm) FAST (andcc_imm) }, - { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, - { TYPE (INSN_OR_IMM), IDX (INSN_OR_IMM), FULL (or_imm) FAST (or_imm) }, - { TYPE (INSN_ORCC), IDX (INSN_ORCC), FULL (orcc) FAST (orcc) }, - { TYPE (INSN_ORCC_IMM), IDX (INSN_ORCC_IMM), FULL (orcc_imm) FAST (orcc_imm) }, - { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, - { TYPE (INSN_XOR_IMM), IDX (INSN_XOR_IMM), FULL (xor_imm) FAST (xor_imm) }, - { TYPE (INSN_XORCC), IDX (INSN_XORCC), FULL (xorcc) FAST (xorcc) }, - { TYPE (INSN_XORCC_IMM), IDX (INSN_XORCC_IMM), FULL (xorcc_imm) FAST (xorcc_imm) }, - { TYPE (INSN_ANDN), IDX (INSN_ANDN), FULL (andn) FAST (andn) }, - { TYPE (INSN_ANDN_IMM), IDX (INSN_ANDN_IMM), FULL (andn_imm) FAST (andn_imm) }, - { TYPE (INSN_ANDNCC), IDX (INSN_ANDNCC), FULL (andncc) FAST (andncc) }, - { TYPE (INSN_ANDNCC_IMM), IDX (INSN_ANDNCC_IMM), FULL (andncc_imm) FAST (andncc_imm) }, - { TYPE (INSN_ORN), IDX (INSN_ORN), FULL (orn) FAST (orn) }, - { TYPE (INSN_ORN_IMM), IDX (INSN_ORN_IMM), FULL (orn_imm) FAST (orn_imm) }, - { TYPE (INSN_ORNCC), IDX (INSN_ORNCC), FULL (orncc) FAST (orncc) }, - { TYPE (INSN_ORNCC_IMM), IDX (INSN_ORNCC_IMM), FULL (orncc_imm) FAST (orncc_imm) }, - { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) }, - { TYPE (INSN_XNOR_IMM), IDX (INSN_XNOR_IMM), FULL (xnor_imm) FAST (xnor_imm) }, - { TYPE (INSN_XNORCC), IDX (INSN_XNORCC), FULL (xnorcc) FAST (xnorcc) }, - { TYPE (INSN_XNORCC_IMM), IDX (INSN_XNORCC_IMM), FULL (xnorcc_imm) FAST (xnorcc_imm) }, - { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) }, - { TYPE (INSN_SLL_IMM), IDX (INSN_SLL_IMM), FULL (sll_imm) FAST (sll_imm) }, - { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) }, - { TYPE (INSN_SRL_IMM), IDX (INSN_SRL_IMM), FULL (srl_imm) FAST (srl_imm) }, - { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) }, - { TYPE (INSN_SRA_IMM), IDX (INSN_SRA_IMM), FULL (sra_imm) FAST (sra_imm) }, - { TYPE (INSN_SMUL), IDX (INSN_SMUL), FULL (smul) FAST (smul) }, - { TYPE (INSN_SMUL_IMM), IDX (INSN_SMUL_IMM), FULL (smul_imm) FAST (smul_imm) }, - { TYPE (INSN_SMUL_CC), IDX (INSN_SMUL_CC), FULL (smul_cc) FAST (smul_cc) }, - { TYPE (INSN_SMUL_CC_IMM), IDX (INSN_SMUL_CC_IMM), FULL (smul_cc_imm) FAST (smul_cc_imm) }, - { TYPE (INSN_UMUL), IDX (INSN_UMUL), FULL (umul) FAST (umul) }, - { TYPE (INSN_UMUL_IMM), IDX (INSN_UMUL_IMM), FULL (umul_imm) FAST (umul_imm) }, - { TYPE (INSN_UMUL_CC), IDX (INSN_UMUL_CC), FULL (umul_cc) FAST (umul_cc) }, - { TYPE (INSN_UMUL_CC_IMM), IDX (INSN_UMUL_CC_IMM), FULL (umul_cc_imm) FAST (umul_cc_imm) }, - { TYPE (INSN_SDIV), IDX (INSN_SDIV), FULL (sdiv) FAST (sdiv) }, - { TYPE (INSN_SDIV_IMM), IDX (INSN_SDIV_IMM), FULL (sdiv_imm) FAST (sdiv_imm) }, - { TYPE (INSN_SDIV_CC), IDX (INSN_SDIV_CC), FULL (sdiv_cc) FAST (sdiv_cc) }, - { TYPE (INSN_SDIV_CC_IMM), IDX (INSN_SDIV_CC_IMM), FULL (sdiv_cc_imm) FAST (sdiv_cc_imm) }, - { TYPE (INSN_UDIV), IDX (INSN_UDIV), FULL (udiv) FAST (udiv) }, - { TYPE (INSN_UDIV_IMM), IDX (INSN_UDIV_IMM), FULL (udiv_imm) FAST (udiv_imm) }, - { TYPE (INSN_UDIV_CC), IDX (INSN_UDIV_CC), FULL (udiv_cc) FAST (udiv_cc) }, - { TYPE (INSN_UDIV_CC_IMM), IDX (INSN_UDIV_CC_IMM), FULL (udiv_cc_imm) FAST (udiv_cc_imm) }, - { TYPE (INSN_MULSCC), IDX (INSN_MULSCC), FULL (mulscc) FAST (mulscc) }, - { TYPE (INSN_SAVE), IDX (INSN_SAVE), FULL (save) FAST (save) }, - { TYPE (INSN_SAVE_IMM), IDX (INSN_SAVE_IMM), FULL (save_imm) FAST (save_imm) }, - { TYPE (INSN_RESTORE), IDX (INSN_RESTORE), FULL (restore) FAST (restore) }, - { TYPE (INSN_RESTORE_IMM), IDX (INSN_RESTORE_IMM), FULL (restore_imm) FAST (restore_imm) }, - { TYPE (INSN_RETT), IDX (INSN_RETT), FULL (rett) FAST (rett) }, - { TYPE (INSN_RETT_IMM), IDX (INSN_RETT_IMM), FULL (rett_imm) FAST (rett_imm) }, - { TYPE (INSN_UNIMP), IDX (INSN_UNIMP), FULL (unimp) FAST (unimp) }, - { TYPE (INSN_CALL), IDX (INSN_CALL), FULL (call) FAST (call) }, - { TYPE (INSN_JMPL), IDX (INSN_JMPL), FULL (jmpl) FAST (jmpl) }, - { TYPE (INSN_JMPL_IMM), IDX (INSN_JMPL_IMM), FULL (jmpl_imm) FAST (jmpl_imm) }, - { TYPE (INSN_BA), IDX (INSN_BA), FULL (ba) FAST (ba) }, - { TYPE (INSN_TA), IDX (INSN_TA), FULL (ta) FAST (ta) }, - { TYPE (INSN_TA_IMM), IDX (INSN_TA_IMM), FULL (ta_imm) FAST (ta_imm) }, - { TYPE (INSN_BN), IDX (INSN_BN), FULL (bn) FAST (bn) }, - { TYPE (INSN_TN), IDX (INSN_TN), FULL (tn) FAST (tn) }, - { TYPE (INSN_TN_IMM), IDX (INSN_TN_IMM), FULL (tn_imm) FAST (tn_imm) }, - { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, - { TYPE (INSN_TNE), IDX (INSN_TNE), FULL (tne) FAST (tne) }, - { TYPE (INSN_TNE_IMM), IDX (INSN_TNE_IMM), FULL (tne_imm) FAST (tne_imm) }, - { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) }, - { TYPE (INSN_TE), IDX (INSN_TE), FULL (te) FAST (te) }, - { TYPE (INSN_TE_IMM), IDX (INSN_TE_IMM), FULL (te_imm) FAST (te_imm) }, - { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) }, - { TYPE (INSN_TG), IDX (INSN_TG), FULL (tg) FAST (tg) }, - { TYPE (INSN_TG_IMM), IDX (INSN_TG_IMM), FULL (tg_imm) FAST (tg_imm) }, - { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, - { TYPE (INSN_TLE), IDX (INSN_TLE), FULL (tle) FAST (tle) }, - { TYPE (INSN_TLE_IMM), IDX (INSN_TLE_IMM), FULL (tle_imm) FAST (tle_imm) }, - { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, - { TYPE (INSN_TGE), IDX (INSN_TGE), FULL (tge) FAST (tge) }, - { TYPE (INSN_TGE_IMM), IDX (INSN_TGE_IMM), FULL (tge_imm) FAST (tge_imm) }, - { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) }, - { TYPE (INSN_TL), IDX (INSN_TL), FULL (tl) FAST (tl) }, - { TYPE (INSN_TL_IMM), IDX (INSN_TL_IMM), FULL (tl_imm) FAST (tl_imm) }, - { TYPE (INSN_BGU), IDX (INSN_BGU), FULL (bgu) FAST (bgu) }, - { TYPE (INSN_TGU), IDX (INSN_TGU), FULL (tgu) FAST (tgu) }, - { TYPE (INSN_TGU_IMM), IDX (INSN_TGU_IMM), FULL (tgu_imm) FAST (tgu_imm) }, - { TYPE (INSN_BLEU), IDX (INSN_BLEU), FULL (bleu) FAST (bleu) }, - { TYPE (INSN_TLEU), IDX (INSN_TLEU), FULL (tleu) FAST (tleu) }, - { TYPE (INSN_TLEU_IMM), IDX (INSN_TLEU_IMM), FULL (tleu_imm) FAST (tleu_imm) }, - { TYPE (INSN_BCC), IDX (INSN_BCC), FULL (bcc) FAST (bcc) }, - { TYPE (INSN_TCC), IDX (INSN_TCC), FULL (tcc) FAST (tcc) }, - { TYPE (INSN_TCC_IMM), IDX (INSN_TCC_IMM), FULL (tcc_imm) FAST (tcc_imm) }, - { TYPE (INSN_BCS), IDX (INSN_BCS), FULL (bcs) FAST (bcs) }, - { TYPE (INSN_TCS), IDX (INSN_TCS), FULL (tcs) FAST (tcs) }, - { TYPE (INSN_TCS_IMM), IDX (INSN_TCS_IMM), FULL (tcs_imm) FAST (tcs_imm) }, - { TYPE (INSN_BPOS), IDX (INSN_BPOS), FULL (bpos) FAST (bpos) }, - { TYPE (INSN_TPOS), IDX (INSN_TPOS), FULL (tpos) FAST (tpos) }, - { TYPE (INSN_TPOS_IMM), IDX (INSN_TPOS_IMM), FULL (tpos_imm) FAST (tpos_imm) }, - { TYPE (INSN_BNEG), IDX (INSN_BNEG), FULL (bneg) FAST (bneg) }, - { TYPE (INSN_TNEG), IDX (INSN_TNEG), FULL (tneg) FAST (tneg) }, - { TYPE (INSN_TNEG_IMM), IDX (INSN_TNEG_IMM), FULL (tneg_imm) FAST (tneg_imm) }, - { TYPE (INSN_BVC), IDX (INSN_BVC), FULL (bvc) FAST (bvc) }, - { TYPE (INSN_TVC), IDX (INSN_TVC), FULL (tvc) FAST (tvc) }, - { TYPE (INSN_TVC_IMM), IDX (INSN_TVC_IMM), FULL (tvc_imm) FAST (tvc_imm) }, - { TYPE (INSN_BVS), IDX (INSN_BVS), FULL (bvs) FAST (bvs) }, - { TYPE (INSN_TVS), IDX (INSN_TVS), FULL (tvs) FAST (tvs) }, - { TYPE (INSN_TVS_IMM), IDX (INSN_TVS_IMM), FULL (tvs_imm) FAST (tvs_imm) }, -}; - -static const struct insn_sem sparc32_insn_sem_invalid = -{ - VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) -}; - -#undef IDX -#undef TYPE - -/* Initialize an IDESC from the compile-time computable parts. */ - -static INLINE void -init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) -{ - const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; - - id->num = t->index; - if ((int) t->type <= 0) - id->idata = & cgen_virtual_insn_table[- (int) t->type]; - else - id->idata = & insn_table[t->type]; - id->attrs = CGEN_INSN_ATTRS (id->idata); - /* Oh my god, a magic number. */ - id->length = CGEN_INSN_BITSIZE (id->idata) / 8; -#if ! WITH_SEM_SWITCH_FULL - id->sem_full = t->sem_full; -#endif -#if WITH_FAST && ! WITH_SEM_SWITCH_FAST - id->sem_fast = t->sem_fast; -#endif -#if WITH_PROFILE_MODEL_P - id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; - { - SIM_DESC sd = CPU_STATE (cpu); - SIM_ASSERT (t->index == id->timing->num); - } -#endif -} - -/* Initialize the instruction descriptor table. */ - -void -sparc32_init_idesc_table (SIM_CPU *cpu) -{ - IDESC *id,*tabend; - const struct insn_sem *t,*tend; - int tabsize = SPARC32_INSN_MAX; - IDESC *table = sparc32_insn_data; - - memset (table, 0, tabsize * sizeof (IDESC)); - - /* First set all entries to the `invalid insn'. */ - t = & sparc32_insn_sem_invalid; - for (id = table, tabend = table + tabsize; id < tabend; ++id) - init_idesc (cpu, id, t); - - /* Now fill in the values for the chosen cpu. */ - for (t = sparc32_insn_sem, tend = t + sizeof (sparc32_insn_sem) / sizeof (*t); - t != tend; ++t) - { - init_idesc (cpu, & table[t->index], t); - } - - /* Link the IDESC table into the cpu. */ - CPU_IDESC (cpu) = table; -} - -#define GOTO_EXTRACT(id) goto extract - -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) -#endif - -/* Given an instruction, return a pointer to its IDESC entry. */ - -const IDESC * -sparc32_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, - ARGBUF *abuf) -{ - /* Result. */ - const IDESC *idecode; - - { -#define I(insn) & sparc32_insn_data[CONCAT2 (SPARC32_,insn)] - CGEN_INSN_INT insn = base_insn; - static const IDESC *idecode_invalid = I (INSN_X_INVALID); - - { -#ifdef __GNUC__ - static const void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_16, && case_0_17, && case_0_18, && case_0_19, - && case_0_20, && case_0_21, && case_0_22, && case_0_23, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_128, && case_0_129, && case_0_130, && case_0_131, - && case_0_132, && case_0_133, && case_0_134, && case_0_135, - && case_0_136, && default_0, && case_0_138, && case_0_139, - && case_0_140, && default_0, && case_0_142, && case_0_143, - && case_0_144, && case_0_145, && case_0_146, && case_0_147, - && case_0_148, && case_0_149, && case_0_150, && case_0_151, - && case_0_152, && default_0, && case_0_154, && case_0_155, - && case_0_156, && default_0, && case_0_158, && case_0_159, - && default_0, && default_0, && default_0, && default_0, - && default_0, && case_0_165, && case_0_166, && case_0_167, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_176, && case_0_177, && case_0_178, && case_0_179, - && default_0, && default_0, && default_0, && default_0, - && case_0_184, && case_0_185, && case_0_186, && default_0, - && case_0_188, && case_0_189, && default_0, && default_0, - && case_0_192, && case_0_193, && case_0_194, && case_0_195, - && case_0_196, && case_0_197, && case_0_198, && case_0_199, - && case_0_200, && case_0_201, && case_0_202, && default_0, - && default_0, && case_0_205, && default_0, && case_0_207, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_224, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - }; -#endif - static const IDESC * insns[256] = { - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MULSCC), 0, - 0, 0, - I (INSN_RD_ASR), I (INSN_RD_PSR), - I (INSN_RD_WIM), I (INSN_RD_TBR), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), 0, - I (INSN_X_INVALID), 0, - I (INSN_LDUW_REG_REG_ASI), I (INSN_LDUB_REG_REG_ASI), - I (INSN_LDUH_REG_REG_ASI), I (INSN_LDD_REG_REG_ASI), - I (INSN_ST_REG_REG_ASI), I (INSN_STB_REG_REG_ASI), - I (INSN_STH_REG_REG_ASI), I (INSN_STD_REG_REG_ASI), - I (INSN_LDSW_REG_REG_ASI), I (INSN_LDSB_REG_REG_ASI), - I (INSN_LDSH_REG_REG_ASI), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_LDSTUB_REG_REG_ASI), - I (INSN_X_INVALID), I (INSN_SWAP_REG_REG_ASI), - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_FP_LD_REG_REG_ASI), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 24) & (3 << 6)) | ((insn >> 19) & (63 << 0))); - DECODE_SWITCH (0, val) - { - CASE (0, 16) : /* fall through */ - CASE (0, 17) : /* fall through */ - CASE (0, 18) : /* fall through */ - CASE (0, 19) : /* fall through */ - CASE (0, 20) : /* fall through */ - CASE (0, 21) : /* fall through */ - CASE (0, 22) : /* fall through */ - CASE (0, 23) : - { - static const IDESC * insns[16] = { - I (INSN_BN), I (INSN_BE), - I (INSN_BLE), I (INSN_BL), - I (INSN_BLEU), I (INSN_BCS), - I (INSN_BNEG), I (INSN_BVS), - I (INSN_BA), I (INSN_BNE), - I (INSN_BG), I (INSN_BGE), - I (INSN_BGU), I (INSN_BCC), - I (INSN_BPOS), I (INSN_BVC), - }; - unsigned int val = (((insn >> 25) & (15 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 128) : - { - static const IDESC * insns[2] = { - I (INSN_ADD), I (INSN_ADD_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 129) : - { - static const IDESC * insns[2] = { - I (INSN_AND), I (INSN_AND_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 130) : - { - static const IDESC * insns[2] = { - I (INSN_OR), I (INSN_OR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 131) : - { - static const IDESC * insns[2] = { - I (INSN_XOR), I (INSN_XOR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 132) : - { - static const IDESC * insns[2] = { - I (INSN_SUB), I (INSN_SUB_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 133) : - { - static const IDESC * insns[2] = { - I (INSN_ANDN), I (INSN_ANDN_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 134) : - { - static const IDESC * insns[2] = { - I (INSN_ORN), I (INSN_ORN_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 135) : - { - static const IDESC * insns[2] = { - I (INSN_XNOR), I (INSN_XNOR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 136) : - { - static const IDESC * insns[2] = { - I (INSN_ADDX), I (INSN_ADDX_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 138) : - { - static const IDESC * insns[2] = { - I (INSN_UMUL), I (INSN_UMUL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 139) : - { - static const IDESC * insns[2] = { - I (INSN_SMUL), I (INSN_SMUL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 140) : - { - static const IDESC * insns[2] = { - I (INSN_SUBX), I (INSN_SUBX_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 142) : - { - static const IDESC * insns[2] = { - I (INSN_UDIV), I (INSN_UDIV_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 143) : - { - static const IDESC * insns[2] = { - I (INSN_SDIV), I (INSN_SDIV_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 144) : - { - static const IDESC * insns[2] = { - I (INSN_ADDCC), I (INSN_ADDCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 145) : - { - static const IDESC * insns[2] = { - I (INSN_ANDCC), I (INSN_ANDCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 146) : - { - static const IDESC * insns[2] = { - I (INSN_ORCC), I (INSN_ORCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 147) : - { - static const IDESC * insns[2] = { - I (INSN_XORCC), I (INSN_XORCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 148) : - { - static const IDESC * insns[2] = { - I (INSN_SUBCC), I (INSN_SUBCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 149) : - { - static const IDESC * insns[2] = { - I (INSN_ANDNCC), I (INSN_ANDNCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 150) : - { - static const IDESC * insns[2] = { - I (INSN_ORNCC), I (INSN_ORNCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 151) : - { - static const IDESC * insns[2] = { - I (INSN_XNORCC), I (INSN_XNORCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 152) : - { - static const IDESC * insns[2] = { - I (INSN_ADDXCC), I (INSN_ADDXCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 154) : - { - static const IDESC * insns[2] = { - I (INSN_UMUL_CC), I (INSN_UMUL_CC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 155) : - { - static const IDESC * insns[2] = { - I (INSN_SMUL_CC), I (INSN_SMUL_CC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 156) : - { - static const IDESC * insns[2] = { - I (INSN_SUBXCC), I (INSN_SUBXCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 158) : - { - static const IDESC * insns[2] = { - I (INSN_UDIV_CC), I (INSN_UDIV_CC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 159) : - { - static const IDESC * insns[2] = { - I (INSN_SDIV_CC), I (INSN_SDIV_CC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 165) : - { - static const IDESC * insns[2] = { - I (INSN_SLL), I (INSN_SLL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 166) : - { - static const IDESC * insns[2] = { - I (INSN_SRL), I (INSN_SRL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 167) : - { - static const IDESC * insns[2] = { - I (INSN_SRA), I (INSN_SRA_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 176) : - { - static const IDESC * insns[2] = { - I (INSN_WR_ASR), I (INSN_WR_ASR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 177) : - { -#ifdef __GNUC__ - static const void *labels_0_177[16] = { - && case_0_177_0, && default_0_177, && default_0_177, && default_0_177, - && default_0_177, && default_0_177, && default_0_177, && default_0_177, - && default_0_177, && default_0_177, && default_0_177, && default_0_177, - && default_0_177, && default_0_177, && default_0_177, && default_0_177, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_177, val) - { - CASE (0_177, 0) : - { - static const IDESC * insns[4] = { - I (INSN_WR_PSR), I (INSN_WR_PSR_IMM), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_177) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_177) - } - CASE (0, 178) : - { -#ifdef __GNUC__ - static const void *labels_0_178[16] = { - && case_0_178_0, && default_0_178, && default_0_178, && default_0_178, - && default_0_178, && default_0_178, && default_0_178, && default_0_178, - && default_0_178, && default_0_178, && default_0_178, && default_0_178, - && default_0_178, && default_0_178, && default_0_178, && default_0_178, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_178, val) - { - CASE (0_178, 0) : - { - static const IDESC * insns[4] = { - I (INSN_WR_WIM), I (INSN_WR_WIM_IMM), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_178) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_178) - } - CASE (0, 179) : - { -#ifdef __GNUC__ - static const void *labels_0_179[16] = { - && case_0_179_0, && default_0_179, && default_0_179, && default_0_179, - && default_0_179, && default_0_179, && default_0_179, && default_0_179, - && default_0_179, && default_0_179, && default_0_179, && default_0_179, - && default_0_179, && default_0_179, && default_0_179, && default_0_179, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_179, val) - { - CASE (0_179, 0) : - { - static const IDESC * insns[4] = { - I (INSN_WR_TBR), I (INSN_WR_TBR_IMM), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_179) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_179) - } - CASE (0, 184) : - { - static const IDESC * insns[2] = { - I (INSN_JMPL), I (INSN_JMPL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 185) : - { -#ifdef __GNUC__ - static const void *labels_0_185[16] = { - && case_0_185_0, && default_0_185, && default_0_185, && default_0_185, - && default_0_185, && default_0_185, && default_0_185, && default_0_185, - && default_0_185, && default_0_185, && default_0_185, && default_0_185, - && default_0_185, && default_0_185, && default_0_185, && default_0_185, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_185, val) - { - CASE (0_185, 0) : - { - static const IDESC * insns[4] = { - I (INSN_RETT), I (INSN_RETT_IMM), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_185) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_185) - } - CASE (0, 186) : - { -#ifdef __GNUC__ - static const void *labels_0_186[16] = { - && case_0_186_0, && case_0_186_1, && case_0_186_2, && case_0_186_3, - && case_0_186_4, && case_0_186_5, && case_0_186_6, && case_0_186_7, - && default_0_186, && default_0_186, && default_0_186, && default_0_186, - && default_0_186, && default_0_186, && default_0_186, && default_0_186, - }; -#endif - static const IDESC * insns[16] = { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_186, val) - { - CASE (0_186, 0) : - { - static const IDESC * insns[4] = { - I (INSN_TN), I (INSN_TN_IMM), - I (INSN_TE), I (INSN_TE_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 1) : - { - static const IDESC * insns[4] = { - I (INSN_TLE), I (INSN_TLE_IMM), - I (INSN_TL), I (INSN_TL_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 2) : - { - static const IDESC * insns[4] = { - I (INSN_TLEU), I (INSN_TLEU_IMM), - I (INSN_TCS), I (INSN_TCS_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 3) : - { - static const IDESC * insns[4] = { - I (INSN_TNEG), I (INSN_TNEG_IMM), - I (INSN_TVS), I (INSN_TVS_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 4) : - { - static const IDESC * insns[4] = { - I (INSN_TA), I (INSN_TA_IMM), - I (INSN_TNE), I (INSN_TNE_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 5) : - { - static const IDESC * insns[4] = { - I (INSN_TG), I (INSN_TG_IMM), - I (INSN_TGE), I (INSN_TGE_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 6) : - { - static const IDESC * insns[4] = { - I (INSN_TGU), I (INSN_TGU_IMM), - I (INSN_TCC), I (INSN_TCC_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 7) : - { - static const IDESC * insns[4] = { - I (INSN_TPOS), I (INSN_TPOS_IMM), - I (INSN_TVC), I (INSN_TVC_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_186) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_186) - } - CASE (0, 188) : - { - static const IDESC * insns[2] = { - I (INSN_SAVE), I (INSN_SAVE_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 189) : - { - static const IDESC * insns[2] = { - I (INSN_RESTORE), I (INSN_RESTORE_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 192) : - { - static const IDESC * insns[2] = { - I (INSN_LDUW_REG_REG), I (INSN_LDUW_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 193) : - { - static const IDESC * insns[2] = { - I (INSN_LDUB_REG_REG), I (INSN_LDUB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 194) : - { - static const IDESC * insns[2] = { - I (INSN_LDUH_REG_REG), I (INSN_LDUH_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 195) : - { - static const IDESC * insns[2] = { - I (INSN_LDD_REG_REG), I (INSN_LDD_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 196) : - { - static const IDESC * insns[2] = { - I (INSN_ST_REG_REG), I (INSN_ST_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 197) : - { - static const IDESC * insns[2] = { - I (INSN_STB_REG_REG), I (INSN_STB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 198) : - { - static const IDESC * insns[2] = { - I (INSN_STH_REG_REG), I (INSN_STH_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 199) : - { - static const IDESC * insns[2] = { - I (INSN_STD_REG_REG), I (INSN_STD_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 200) : - { - static const IDESC * insns[2] = { - I (INSN_LDSW_REG_REG), I (INSN_LDSW_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 201) : - { - static const IDESC * insns[2] = { - I (INSN_LDSB_REG_REG), I (INSN_LDSB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 202) : - { - static const IDESC * insns[2] = { - I (INSN_LDSH_REG_REG), I (INSN_LDSH_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 205) : - { - static const IDESC * insns[2] = { - I (INSN_LDSTUB_REG_REG), I (INSN_LDSTUB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 207) : - { - static const IDESC * insns[2] = { - I (INSN_SWAP_REG_REG), I (INSN_SWAP_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 224) : - { - static const IDESC * insns[2] = { - I (INSN_FP_LD_REG_REG), I (INSN_FP_LD_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0) - } -#undef I -#undef E - } - - /* Extraction is defered until the semantic code. */ - - extract: - return idecode; -} diff --git a/sim/sparc/decode32.h b/sim/sparc/decode32.h deleted file mode 100644 index 2d9873e..0000000 --- a/sim/sparc/decode32.h +++ /dev/null @@ -1,285 +0,0 @@ -/* Decode header for sparc32. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef SPARC32_DECODE_H -#define SPARC32_DECODE_H - -extern const IDESC *sparc32_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, - ARGBUF *); -extern void sparc32_init_idesc_table (SIM_CPU *); - -/* Enum declaration for instructions in cpu family sparc32. */ -typedef enum sparc32_insn_type { - SPARC32_INSN_X_INVALID, SPARC32_INSN_X_AFTER, SPARC32_INSN_X_BEFORE, SPARC32_INSN_X_CTI_CHAIN - , SPARC32_INSN_X_CHAIN, SPARC32_INSN_X_BEGIN, SPARC32_INSN_RD_ASR, SPARC32_INSN_WR_ASR - , SPARC32_INSN_WR_ASR_IMM, SPARC32_INSN_RD_PSR, SPARC32_INSN_WR_PSR, SPARC32_INSN_WR_PSR_IMM - , SPARC32_INSN_RD_WIM, SPARC32_INSN_WR_WIM, SPARC32_INSN_WR_WIM_IMM, SPARC32_INSN_RD_TBR - , SPARC32_INSN_WR_TBR, SPARC32_INSN_WR_TBR_IMM, SPARC32_INSN_LDSTUB_REG_REG, SPARC32_INSN_LDSTUB_REG_IMM - , SPARC32_INSN_LDSTUB_REG_REG_ASI, SPARC32_INSN_SWAP_REG_REG, SPARC32_INSN_SWAP_REG_IMM, SPARC32_INSN_SWAP_REG_REG_ASI - , SPARC32_INSN_LDSB_REG_REG, SPARC32_INSN_LDSB_REG_IMM, SPARC32_INSN_LDSB_REG_REG_ASI, SPARC32_INSN_LDUB_REG_REG - , SPARC32_INSN_LDUB_REG_IMM, SPARC32_INSN_LDUB_REG_REG_ASI, SPARC32_INSN_LDSH_REG_REG, SPARC32_INSN_LDSH_REG_IMM - , SPARC32_INSN_LDSH_REG_REG_ASI, SPARC32_INSN_LDUH_REG_REG, SPARC32_INSN_LDUH_REG_IMM, SPARC32_INSN_LDUH_REG_REG_ASI - , SPARC32_INSN_LDSW_REG_REG, SPARC32_INSN_LDSW_REG_IMM, SPARC32_INSN_LDSW_REG_REG_ASI, SPARC32_INSN_LDUW_REG_REG - , SPARC32_INSN_LDUW_REG_IMM, SPARC32_INSN_LDUW_REG_REG_ASI, SPARC32_INSN_LDD_REG_REG, SPARC32_INSN_LDD_REG_IMM - , SPARC32_INSN_LDD_REG_REG_ASI, SPARC32_INSN_STB_REG_REG, SPARC32_INSN_STB_REG_IMM, SPARC32_INSN_STB_REG_REG_ASI - , SPARC32_INSN_STH_REG_REG, SPARC32_INSN_STH_REG_IMM, SPARC32_INSN_STH_REG_REG_ASI, SPARC32_INSN_ST_REG_REG - , SPARC32_INSN_ST_REG_IMM, SPARC32_INSN_ST_REG_REG_ASI, SPARC32_INSN_STD_REG_REG, SPARC32_INSN_STD_REG_IMM - , SPARC32_INSN_STD_REG_REG_ASI, SPARC32_INSN_FP_LD_REG_REG, SPARC32_INSN_FP_LD_REG_IMM, SPARC32_INSN_FP_LD_REG_REG_ASI - , SPARC32_INSN_SETHI, SPARC32_INSN_ADD, SPARC32_INSN_ADD_IMM, SPARC32_INSN_SUB - , SPARC32_INSN_SUB_IMM, SPARC32_INSN_ADDCC, SPARC32_INSN_ADDCC_IMM, SPARC32_INSN_SUBCC - , SPARC32_INSN_SUBCC_IMM, SPARC32_INSN_ADDX, SPARC32_INSN_ADDX_IMM, SPARC32_INSN_SUBX - , SPARC32_INSN_SUBX_IMM, SPARC32_INSN_ADDXCC, SPARC32_INSN_ADDXCC_IMM, SPARC32_INSN_SUBXCC - , SPARC32_INSN_SUBXCC_IMM, SPARC32_INSN_AND, SPARC32_INSN_AND_IMM, SPARC32_INSN_ANDCC - , SPARC32_INSN_ANDCC_IMM, SPARC32_INSN_OR, SPARC32_INSN_OR_IMM, SPARC32_INSN_ORCC - , SPARC32_INSN_ORCC_IMM, SPARC32_INSN_XOR, SPARC32_INSN_XOR_IMM, SPARC32_INSN_XORCC - , SPARC32_INSN_XORCC_IMM, SPARC32_INSN_ANDN, SPARC32_INSN_ANDN_IMM, SPARC32_INSN_ANDNCC - , SPARC32_INSN_ANDNCC_IMM, SPARC32_INSN_ORN, SPARC32_INSN_ORN_IMM, SPARC32_INSN_ORNCC - , SPARC32_INSN_ORNCC_IMM, SPARC32_INSN_XNOR, SPARC32_INSN_XNOR_IMM, SPARC32_INSN_XNORCC - , SPARC32_INSN_XNORCC_IMM, SPARC32_INSN_SLL, SPARC32_INSN_SLL_IMM, SPARC32_INSN_SRL - , SPARC32_INSN_SRL_IMM, SPARC32_INSN_SRA, SPARC32_INSN_SRA_IMM, SPARC32_INSN_SMUL - , SPARC32_INSN_SMUL_IMM, SPARC32_INSN_SMUL_CC, SPARC32_INSN_SMUL_CC_IMM, SPARC32_INSN_UMUL - , SPARC32_INSN_UMUL_IMM, SPARC32_INSN_UMUL_CC, SPARC32_INSN_UMUL_CC_IMM, SPARC32_INSN_SDIV - , SPARC32_INSN_SDIV_IMM, SPARC32_INSN_SDIV_CC, SPARC32_INSN_SDIV_CC_IMM, SPARC32_INSN_UDIV - , SPARC32_INSN_UDIV_IMM, SPARC32_INSN_UDIV_CC, SPARC32_INSN_UDIV_CC_IMM, SPARC32_INSN_MULSCC - , SPARC32_INSN_SAVE, SPARC32_INSN_SAVE_IMM, SPARC32_INSN_RESTORE, SPARC32_INSN_RESTORE_IMM - , SPARC32_INSN_RETT, SPARC32_INSN_RETT_IMM, SPARC32_INSN_UNIMP, SPARC32_INSN_CALL - , SPARC32_INSN_JMPL, SPARC32_INSN_JMPL_IMM, SPARC32_INSN_BA, SPARC32_INSN_TA - , SPARC32_INSN_TA_IMM, SPARC32_INSN_BN, SPARC32_INSN_TN, SPARC32_INSN_TN_IMM - , SPARC32_INSN_BNE, SPARC32_INSN_TNE, SPARC32_INSN_TNE_IMM, SPARC32_INSN_BE - , SPARC32_INSN_TE, SPARC32_INSN_TE_IMM, SPARC32_INSN_BG, SPARC32_INSN_TG - , SPARC32_INSN_TG_IMM, SPARC32_INSN_BLE, SPARC32_INSN_TLE, SPARC32_INSN_TLE_IMM - , SPARC32_INSN_BGE, SPARC32_INSN_TGE, SPARC32_INSN_TGE_IMM, SPARC32_INSN_BL - , SPARC32_INSN_TL, SPARC32_INSN_TL_IMM, SPARC32_INSN_BGU, SPARC32_INSN_TGU - , SPARC32_INSN_TGU_IMM, SPARC32_INSN_BLEU, SPARC32_INSN_TLEU, SPARC32_INSN_TLEU_IMM - , SPARC32_INSN_BCC, SPARC32_INSN_TCC, SPARC32_INSN_TCC_IMM, SPARC32_INSN_BCS - , SPARC32_INSN_TCS, SPARC32_INSN_TCS_IMM, SPARC32_INSN_BPOS, SPARC32_INSN_TPOS - , SPARC32_INSN_TPOS_IMM, SPARC32_INSN_BNEG, SPARC32_INSN_TNEG, SPARC32_INSN_TNEG_IMM - , SPARC32_INSN_BVC, SPARC32_INSN_TVC, SPARC32_INSN_TVC_IMM, SPARC32_INSN_BVS - , SPARC32_INSN_TVS, SPARC32_INSN_TVS_IMM, SPARC32_INSN_MAX -} SPARC32_INSN_TYPE; - -#if ! WITH_SEM_SWITCH_FULL -#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,fn); -#else -#define SEMFULL(fn) -#endif - -#if ! WITH_SEM_SWITCH_FAST -#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc32,_semf_,fn); -#else -#define SEMFAST(fn) -#endif - -#define SEM(fn) SEMFULL (fn) SEMFAST (fn) - -/* The function version of the before/after handlers is always needed, - so we always want the SEMFULL declaration of them. */ -extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,x_before); -extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,x_after); - -SEM (x_invalid) -SEM (x_after) -SEM (x_before) -SEM (x_cti_chain) -SEM (x_chain) -SEM (x_begin) -SEM (rd_asr) -SEM (wr_asr) -SEM (wr_asr_imm) -SEM (rd_psr) -SEM (wr_psr) -SEM (wr_psr_imm) -SEM (rd_wim) -SEM (wr_wim) -SEM (wr_wim_imm) -SEM (rd_tbr) -SEM (wr_tbr) -SEM (wr_tbr_imm) -SEM (ldstub_reg_reg) -SEM (ldstub_reg_imm) -SEM (ldstub_reg_reg_asi) -SEM (swap_reg_reg) -SEM (swap_reg_imm) -SEM (swap_reg_reg_asi) -SEM (ldsb_reg_reg) -SEM (ldsb_reg_imm) -SEM (ldsb_reg_reg_asi) -SEM (ldub_reg_reg) -SEM (ldub_reg_imm) -SEM (ldub_reg_reg_asi) -SEM (ldsh_reg_reg) -SEM (ldsh_reg_imm) -SEM (ldsh_reg_reg_asi) -SEM (lduh_reg_reg) -SEM (lduh_reg_imm) -SEM (lduh_reg_reg_asi) -SEM (ldsw_reg_reg) -SEM (ldsw_reg_imm) -SEM (ldsw_reg_reg_asi) -SEM (lduw_reg_reg) -SEM (lduw_reg_imm) -SEM (lduw_reg_reg_asi) -SEM (ldd_reg_reg) -SEM (ldd_reg_imm) -SEM (ldd_reg_reg_asi) -SEM (stb_reg_reg) -SEM (stb_reg_imm) -SEM (stb_reg_reg_asi) -SEM (sth_reg_reg) -SEM (sth_reg_imm) -SEM (sth_reg_reg_asi) -SEM (st_reg_reg) -SEM (st_reg_imm) -SEM (st_reg_reg_asi) -SEM (std_reg_reg) -SEM (std_reg_imm) -SEM (std_reg_reg_asi) -SEM (fp_ld_reg_reg) -SEM (fp_ld_reg_imm) -SEM (fp_ld_reg_reg_asi) -SEM (sethi) -SEM (add) -SEM (add_imm) -SEM (sub) -SEM (sub_imm) -SEM (addcc) -SEM (addcc_imm) -SEM (subcc) -SEM (subcc_imm) -SEM (addx) -SEM (addx_imm) -SEM (subx) -SEM (subx_imm) -SEM (addxcc) -SEM (addxcc_imm) -SEM (subxcc) -SEM (subxcc_imm) -SEM (and) -SEM (and_imm) -SEM (andcc) -SEM (andcc_imm) -SEM (or) -SEM (or_imm) -SEM (orcc) -SEM (orcc_imm) -SEM (xor) -SEM (xor_imm) -SEM (xorcc) -SEM (xorcc_imm) -SEM (andn) -SEM (andn_imm) -SEM (andncc) -SEM (andncc_imm) -SEM (orn) -SEM (orn_imm) -SEM (orncc) -SEM (orncc_imm) -SEM (xnor) -SEM (xnor_imm) -SEM (xnorcc) -SEM (xnorcc_imm) -SEM (sll) -SEM (sll_imm) -SEM (srl) -SEM (srl_imm) -SEM (sra) -SEM (sra_imm) -SEM (smul) -SEM (smul_imm) -SEM (smul_cc) -SEM (smul_cc_imm) -SEM (umul) -SEM (umul_imm) -SEM (umul_cc) -SEM (umul_cc_imm) -SEM (sdiv) -SEM (sdiv_imm) -SEM (sdiv_cc) -SEM (sdiv_cc_imm) -SEM (udiv) -SEM (udiv_imm) -SEM (udiv_cc) -SEM (udiv_cc_imm) -SEM (mulscc) -SEM (save) -SEM (save_imm) -SEM (restore) -SEM (restore_imm) -SEM (rett) -SEM (rett_imm) -SEM (unimp) -SEM (call) -SEM (jmpl) -SEM (jmpl_imm) -SEM (ba) -SEM (ta) -SEM (ta_imm) -SEM (bn) -SEM (tn) -SEM (tn_imm) -SEM (bne) -SEM (tne) -SEM (tne_imm) -SEM (be) -SEM (te) -SEM (te_imm) -SEM (bg) -SEM (tg) -SEM (tg_imm) -SEM (ble) -SEM (tle) -SEM (tle_imm) -SEM (bge) -SEM (tge) -SEM (tge_imm) -SEM (bl) -SEM (tl) -SEM (tl_imm) -SEM (bgu) -SEM (tgu) -SEM (tgu_imm) -SEM (bleu) -SEM (tleu) -SEM (tleu_imm) -SEM (bcc) -SEM (tcc) -SEM (tcc_imm) -SEM (bcs) -SEM (tcs) -SEM (tcs_imm) -SEM (bpos) -SEM (tpos) -SEM (tpos_imm) -SEM (bneg) -SEM (tneg) -SEM (tneg_imm) -SEM (bvc) -SEM (tvc) -SEM (tvc_imm) -SEM (bvs) -SEM (tvs) -SEM (tvs_imm) - -#undef SEMFULL -#undef SEMFAST -#undef SEM - -/* Function unit handlers (user written). */ - -extern int sparc32_model_sparc32_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); - -/* Profiling before/after handlers (user written) */ - -extern void sparc32_model_insn_before (SIM_CPU *, int /*first_p*/); -extern void sparc32_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); - -#endif /* SPARC32_DECODE_H */ diff --git a/sim/sparc/decode64.c b/sim/sparc/decode64.c deleted file mode 100644 index ed5eb06..0000000 --- a/sim/sparc/decode64.c +++ /dev/null @@ -1,1602 +0,0 @@ -/* Simulator instruction decoder for sparc64. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc64 -#define WANT_CPU_SPARC64 - -#include "sim-main.h" -#include "sim-assert.h" - -/* FIXME: Need to review choices for the following. */ - -#if WITH_SEM_SWITCH_FULL -#define FULL(fn) -#else -#define FULL(fn) CONCAT3 (sparc64,_sem_,fn) , -#endif - -#if WITH_FAST -#if WITH_SEM_SWITCH_FAST -#define FAST(fn) -#else -#define FAST(fn) CONCAT3 (sparc64,_semf_,fn) , /* f for fast */ -#endif -#else -#define FAST(fn) -#endif - -/* The instruction descriptor array. - This is computed at runtime. Space for it is not malloc'd to save a - teensy bit of cpu in the decoder. Moving it to malloc space is trivial - but won't be done until necessary (we don't currently support the runtime - addition of instructions nor an SMP machine with different cpus). */ -static IDESC sparc64_insn_data[SPARC64_INSN_MAX]; - -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (SPARC64_,insn) -#define TYPE(insn) CONCAT2 (SPARC_,insn) - -/* Commas between elements are contained in the macros. - Some of these are conditionally compiled out. */ - -static const struct insn_sem sparc64_insn_sem[] = -{ - { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, - { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, - { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, - { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, - { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, - { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, - { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) }, - { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) }, - { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) }, - { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) }, - { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) }, - { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) }, - { TYPE (INSN_BPCC_BA), IDX (INSN_BPCC_BA), FULL (bpcc_ba) FAST (bpcc_ba) }, - { TYPE (INSN_BPCC_BN), IDX (INSN_BPCC_BN), FULL (bpcc_bn) FAST (bpcc_bn) }, - { TYPE (INSN_BPCC_BNE), IDX (INSN_BPCC_BNE), FULL (bpcc_bne) FAST (bpcc_bne) }, - { TYPE (INSN_BPCC_BE), IDX (INSN_BPCC_BE), FULL (bpcc_be) FAST (bpcc_be) }, - { TYPE (INSN_BPCC_BG), IDX (INSN_BPCC_BG), FULL (bpcc_bg) FAST (bpcc_bg) }, - { TYPE (INSN_BPCC_BLE), IDX (INSN_BPCC_BLE), FULL (bpcc_ble) FAST (bpcc_ble) }, - { TYPE (INSN_BPCC_BGE), IDX (INSN_BPCC_BGE), FULL (bpcc_bge) FAST (bpcc_bge) }, - { TYPE (INSN_BPCC_BL), IDX (INSN_BPCC_BL), FULL (bpcc_bl) FAST (bpcc_bl) }, - { TYPE (INSN_BPCC_BGU), IDX (INSN_BPCC_BGU), FULL (bpcc_bgu) FAST (bpcc_bgu) }, - { TYPE (INSN_BPCC_BLEU), IDX (INSN_BPCC_BLEU), FULL (bpcc_bleu) FAST (bpcc_bleu) }, - { TYPE (INSN_BPCC_BCC), IDX (INSN_BPCC_BCC), FULL (bpcc_bcc) FAST (bpcc_bcc) }, - { TYPE (INSN_BPCC_BCS), IDX (INSN_BPCC_BCS), FULL (bpcc_bcs) FAST (bpcc_bcs) }, - { TYPE (INSN_BPCC_BPOS), IDX (INSN_BPCC_BPOS), FULL (bpcc_bpos) FAST (bpcc_bpos) }, - { TYPE (INSN_BPCC_BNEG), IDX (INSN_BPCC_BNEG), FULL (bpcc_bneg) FAST (bpcc_bneg) }, - { TYPE (INSN_BPCC_BVC), IDX (INSN_BPCC_BVC), FULL (bpcc_bvc) FAST (bpcc_bvc) }, - { TYPE (INSN_BPCC_BVS), IDX (INSN_BPCC_BVS), FULL (bpcc_bvs) FAST (bpcc_bvs) }, - { TYPE (INSN_DONE), IDX (INSN_DONE), FULL (done) FAST (done) }, - { TYPE (INSN_RETRY), IDX (INSN_RETRY), FULL (retry) FAST (retry) }, - { TYPE (INSN_FLUSH), IDX (INSN_FLUSH), FULL (flush) FAST (flush) }, - { TYPE (INSN_FLUSH_IMM), IDX (INSN_FLUSH_IMM), FULL (flush_imm) FAST (flush_imm) }, - { TYPE (INSN_FLUSHW), IDX (INSN_FLUSHW), FULL (flushw) FAST (flushw) }, - { TYPE (INSN_IMPDEP1), IDX (INSN_IMPDEP1), FULL (impdep1) FAST (impdep1) }, - { TYPE (INSN_IMPDEP2), IDX (INSN_IMPDEP2), FULL (impdep2) FAST (impdep2) }, - { TYPE (INSN_MEMBAR), IDX (INSN_MEMBAR), FULL (membar) FAST (membar) }, - { TYPE (INSN_MOVA_ICC_ICC), IDX (INSN_MOVA_ICC_ICC), FULL (mova_icc_icc) FAST (mova_icc_icc) }, - { TYPE (INSN_MOVA_IMM_ICC_ICC), IDX (INSN_MOVA_IMM_ICC_ICC), FULL (mova_imm_icc_icc) FAST (mova_imm_icc_icc) }, - { TYPE (INSN_MOVA_XCC_XCC), IDX (INSN_MOVA_XCC_XCC), FULL (mova_xcc_xcc) FAST (mova_xcc_xcc) }, - { TYPE (INSN_MOVA_IMM_XCC_XCC), IDX (INSN_MOVA_IMM_XCC_XCC), FULL (mova_imm_xcc_xcc) FAST (mova_imm_xcc_xcc) }, - { TYPE (INSN_MOVN_ICC_ICC), IDX (INSN_MOVN_ICC_ICC), FULL (movn_icc_icc) FAST (movn_icc_icc) }, - { TYPE (INSN_MOVN_IMM_ICC_ICC), IDX (INSN_MOVN_IMM_ICC_ICC), FULL (movn_imm_icc_icc) FAST (movn_imm_icc_icc) }, - { TYPE (INSN_MOVN_XCC_XCC), IDX (INSN_MOVN_XCC_XCC), FULL (movn_xcc_xcc) FAST (movn_xcc_xcc) }, - { TYPE (INSN_MOVN_IMM_XCC_XCC), IDX (INSN_MOVN_IMM_XCC_XCC), FULL (movn_imm_xcc_xcc) FAST (movn_imm_xcc_xcc) }, - { TYPE (INSN_MOVNE_ICC_ICC), IDX (INSN_MOVNE_ICC_ICC), FULL (movne_icc_icc) FAST (movne_icc_icc) }, - { TYPE (INSN_MOVNE_IMM_ICC_ICC), IDX (INSN_MOVNE_IMM_ICC_ICC), FULL (movne_imm_icc_icc) FAST (movne_imm_icc_icc) }, - { TYPE (INSN_MOVNE_XCC_XCC), IDX (INSN_MOVNE_XCC_XCC), FULL (movne_xcc_xcc) FAST (movne_xcc_xcc) }, - { TYPE (INSN_MOVNE_IMM_XCC_XCC), IDX (INSN_MOVNE_IMM_XCC_XCC), FULL (movne_imm_xcc_xcc) FAST (movne_imm_xcc_xcc) }, - { TYPE (INSN_MOVE_ICC_ICC), IDX (INSN_MOVE_ICC_ICC), FULL (move_icc_icc) FAST (move_icc_icc) }, - { TYPE (INSN_MOVE_IMM_ICC_ICC), IDX (INSN_MOVE_IMM_ICC_ICC), FULL (move_imm_icc_icc) FAST (move_imm_icc_icc) }, - { TYPE (INSN_MOVE_XCC_XCC), IDX (INSN_MOVE_XCC_XCC), FULL (move_xcc_xcc) FAST (move_xcc_xcc) }, - { TYPE (INSN_MOVE_IMM_XCC_XCC), IDX (INSN_MOVE_IMM_XCC_XCC), FULL (move_imm_xcc_xcc) FAST (move_imm_xcc_xcc) }, - { TYPE (INSN_MOVG_ICC_ICC), IDX (INSN_MOVG_ICC_ICC), FULL (movg_icc_icc) FAST (movg_icc_icc) }, - { TYPE (INSN_MOVG_IMM_ICC_ICC), IDX (INSN_MOVG_IMM_ICC_ICC), FULL (movg_imm_icc_icc) FAST (movg_imm_icc_icc) }, - { TYPE (INSN_MOVG_XCC_XCC), IDX (INSN_MOVG_XCC_XCC), FULL (movg_xcc_xcc) FAST (movg_xcc_xcc) }, - { TYPE (INSN_MOVG_IMM_XCC_XCC), IDX (INSN_MOVG_IMM_XCC_XCC), FULL (movg_imm_xcc_xcc) FAST (movg_imm_xcc_xcc) }, - { TYPE (INSN_MOVLE_ICC_ICC), IDX (INSN_MOVLE_ICC_ICC), FULL (movle_icc_icc) FAST (movle_icc_icc) }, - { TYPE (INSN_MOVLE_IMM_ICC_ICC), IDX (INSN_MOVLE_IMM_ICC_ICC), FULL (movle_imm_icc_icc) FAST (movle_imm_icc_icc) }, - { TYPE (INSN_MOVLE_XCC_XCC), IDX (INSN_MOVLE_XCC_XCC), FULL (movle_xcc_xcc) FAST (movle_xcc_xcc) }, - { TYPE (INSN_MOVLE_IMM_XCC_XCC), IDX (INSN_MOVLE_IMM_XCC_XCC), FULL (movle_imm_xcc_xcc) FAST (movle_imm_xcc_xcc) }, - { TYPE (INSN_MOVGE_ICC_ICC), IDX (INSN_MOVGE_ICC_ICC), FULL (movge_icc_icc) FAST (movge_icc_icc) }, - { TYPE (INSN_MOVGE_IMM_ICC_ICC), IDX (INSN_MOVGE_IMM_ICC_ICC), FULL (movge_imm_icc_icc) FAST (movge_imm_icc_icc) }, - { TYPE (INSN_MOVGE_XCC_XCC), IDX (INSN_MOVGE_XCC_XCC), FULL (movge_xcc_xcc) FAST (movge_xcc_xcc) }, - { TYPE (INSN_MOVGE_IMM_XCC_XCC), IDX (INSN_MOVGE_IMM_XCC_XCC), FULL (movge_imm_xcc_xcc) FAST (movge_imm_xcc_xcc) }, - { TYPE (INSN_MOVL_ICC_ICC), IDX (INSN_MOVL_ICC_ICC), FULL (movl_icc_icc) FAST (movl_icc_icc) }, - { TYPE (INSN_MOVL_IMM_ICC_ICC), IDX (INSN_MOVL_IMM_ICC_ICC), FULL (movl_imm_icc_icc) FAST (movl_imm_icc_icc) }, - { TYPE (INSN_MOVL_XCC_XCC), IDX (INSN_MOVL_XCC_XCC), FULL (movl_xcc_xcc) FAST (movl_xcc_xcc) }, - { TYPE (INSN_MOVL_IMM_XCC_XCC), IDX (INSN_MOVL_IMM_XCC_XCC), FULL (movl_imm_xcc_xcc) FAST (movl_imm_xcc_xcc) }, - { TYPE (INSN_MOVGU_ICC_ICC), IDX (INSN_MOVGU_ICC_ICC), FULL (movgu_icc_icc) FAST (movgu_icc_icc) }, - { TYPE (INSN_MOVGU_IMM_ICC_ICC), IDX (INSN_MOVGU_IMM_ICC_ICC), FULL (movgu_imm_icc_icc) FAST (movgu_imm_icc_icc) }, - { TYPE (INSN_MOVGU_XCC_XCC), IDX (INSN_MOVGU_XCC_XCC), FULL (movgu_xcc_xcc) FAST (movgu_xcc_xcc) }, - { TYPE (INSN_MOVGU_IMM_XCC_XCC), IDX (INSN_MOVGU_IMM_XCC_XCC), FULL (movgu_imm_xcc_xcc) FAST (movgu_imm_xcc_xcc) }, - { TYPE (INSN_MOVLEU_ICC_ICC), IDX (INSN_MOVLEU_ICC_ICC), FULL (movleu_icc_icc) FAST (movleu_icc_icc) }, - { TYPE (INSN_MOVLEU_IMM_ICC_ICC), IDX (INSN_MOVLEU_IMM_ICC_ICC), FULL (movleu_imm_icc_icc) FAST (movleu_imm_icc_icc) }, - { TYPE (INSN_MOVLEU_XCC_XCC), IDX (INSN_MOVLEU_XCC_XCC), FULL (movleu_xcc_xcc) FAST (movleu_xcc_xcc) }, - { TYPE (INSN_MOVLEU_IMM_XCC_XCC), IDX (INSN_MOVLEU_IMM_XCC_XCC), FULL (movleu_imm_xcc_xcc) FAST (movleu_imm_xcc_xcc) }, - { TYPE (INSN_MOVCC_ICC_ICC), IDX (INSN_MOVCC_ICC_ICC), FULL (movcc_icc_icc) FAST (movcc_icc_icc) }, - { TYPE (INSN_MOVCC_IMM_ICC_ICC), IDX (INSN_MOVCC_IMM_ICC_ICC), FULL (movcc_imm_icc_icc) FAST (movcc_imm_icc_icc) }, - { TYPE (INSN_MOVCC_XCC_XCC), IDX (INSN_MOVCC_XCC_XCC), FULL (movcc_xcc_xcc) FAST (movcc_xcc_xcc) }, - { TYPE (INSN_MOVCC_IMM_XCC_XCC), IDX (INSN_MOVCC_IMM_XCC_XCC), FULL (movcc_imm_xcc_xcc) FAST (movcc_imm_xcc_xcc) }, - { TYPE (INSN_MOVCS_ICC_ICC), IDX (INSN_MOVCS_ICC_ICC), FULL (movcs_icc_icc) FAST (movcs_icc_icc) }, - { TYPE (INSN_MOVCS_IMM_ICC_ICC), IDX (INSN_MOVCS_IMM_ICC_ICC), FULL (movcs_imm_icc_icc) FAST (movcs_imm_icc_icc) }, - { TYPE (INSN_MOVCS_XCC_XCC), IDX (INSN_MOVCS_XCC_XCC), FULL (movcs_xcc_xcc) FAST (movcs_xcc_xcc) }, - { TYPE (INSN_MOVCS_IMM_XCC_XCC), IDX (INSN_MOVCS_IMM_XCC_XCC), FULL (movcs_imm_xcc_xcc) FAST (movcs_imm_xcc_xcc) }, - { TYPE (INSN_MOVPOS_ICC_ICC), IDX (INSN_MOVPOS_ICC_ICC), FULL (movpos_icc_icc) FAST (movpos_icc_icc) }, - { TYPE (INSN_MOVPOS_IMM_ICC_ICC), IDX (INSN_MOVPOS_IMM_ICC_ICC), FULL (movpos_imm_icc_icc) FAST (movpos_imm_icc_icc) }, - { TYPE (INSN_MOVPOS_XCC_XCC), IDX (INSN_MOVPOS_XCC_XCC), FULL (movpos_xcc_xcc) FAST (movpos_xcc_xcc) }, - { TYPE (INSN_MOVPOS_IMM_XCC_XCC), IDX (INSN_MOVPOS_IMM_XCC_XCC), FULL (movpos_imm_xcc_xcc) FAST (movpos_imm_xcc_xcc) }, - { TYPE (INSN_MOVNEG_ICC_ICC), IDX (INSN_MOVNEG_ICC_ICC), FULL (movneg_icc_icc) FAST (movneg_icc_icc) }, - { TYPE (INSN_MOVNEG_IMM_ICC_ICC), IDX (INSN_MOVNEG_IMM_ICC_ICC), FULL (movneg_imm_icc_icc) FAST (movneg_imm_icc_icc) }, - { TYPE (INSN_MOVNEG_XCC_XCC), IDX (INSN_MOVNEG_XCC_XCC), FULL (movneg_xcc_xcc) FAST (movneg_xcc_xcc) }, - { TYPE (INSN_MOVNEG_IMM_XCC_XCC), IDX (INSN_MOVNEG_IMM_XCC_XCC), FULL (movneg_imm_xcc_xcc) FAST (movneg_imm_xcc_xcc) }, - { TYPE (INSN_MOVVC_ICC_ICC), IDX (INSN_MOVVC_ICC_ICC), FULL (movvc_icc_icc) FAST (movvc_icc_icc) }, - { TYPE (INSN_MOVVC_IMM_ICC_ICC), IDX (INSN_MOVVC_IMM_ICC_ICC), FULL (movvc_imm_icc_icc) FAST (movvc_imm_icc_icc) }, - { TYPE (INSN_MOVVC_XCC_XCC), IDX (INSN_MOVVC_XCC_XCC), FULL (movvc_xcc_xcc) FAST (movvc_xcc_xcc) }, - { TYPE (INSN_MOVVC_IMM_XCC_XCC), IDX (INSN_MOVVC_IMM_XCC_XCC), FULL (movvc_imm_xcc_xcc) FAST (movvc_imm_xcc_xcc) }, - { TYPE (INSN_MOVVS_ICC_ICC), IDX (INSN_MOVVS_ICC_ICC), FULL (movvs_icc_icc) FAST (movvs_icc_icc) }, - { TYPE (INSN_MOVVS_IMM_ICC_ICC), IDX (INSN_MOVVS_IMM_ICC_ICC), FULL (movvs_imm_icc_icc) FAST (movvs_imm_icc_icc) }, - { TYPE (INSN_MOVVS_XCC_XCC), IDX (INSN_MOVVS_XCC_XCC), FULL (movvs_xcc_xcc) FAST (movvs_xcc_xcc) }, - { TYPE (INSN_MOVVS_IMM_XCC_XCC), IDX (INSN_MOVVS_IMM_XCC_XCC), FULL (movvs_imm_xcc_xcc) FAST (movvs_imm_xcc_xcc) }, - { TYPE (INSN_LDSB_REG_REG), IDX (INSN_LDSB_REG_REG), FULL (ldsb_reg_reg) FAST (ldsb_reg_reg) }, - { TYPE (INSN_LDSB_REG_IMM), IDX (INSN_LDSB_REG_IMM), FULL (ldsb_reg_imm) FAST (ldsb_reg_imm) }, - { TYPE (INSN_LDSB_REG_REG_ASI), IDX (INSN_LDSB_REG_REG_ASI), FULL (ldsb_reg_reg_asi) FAST (ldsb_reg_reg_asi) }, - { TYPE (INSN_LDUB_REG_REG), IDX (INSN_LDUB_REG_REG), FULL (ldub_reg_reg) FAST (ldub_reg_reg) }, - { TYPE (INSN_LDUB_REG_IMM), IDX (INSN_LDUB_REG_IMM), FULL (ldub_reg_imm) FAST (ldub_reg_imm) }, - { TYPE (INSN_LDUB_REG_REG_ASI), IDX (INSN_LDUB_REG_REG_ASI), FULL (ldub_reg_reg_asi) FAST (ldub_reg_reg_asi) }, - { TYPE (INSN_LDSH_REG_REG), IDX (INSN_LDSH_REG_REG), FULL (ldsh_reg_reg) FAST (ldsh_reg_reg) }, - { TYPE (INSN_LDSH_REG_IMM), IDX (INSN_LDSH_REG_IMM), FULL (ldsh_reg_imm) FAST (ldsh_reg_imm) }, - { TYPE (INSN_LDSH_REG_REG_ASI), IDX (INSN_LDSH_REG_REG_ASI), FULL (ldsh_reg_reg_asi) FAST (ldsh_reg_reg_asi) }, - { TYPE (INSN_LDUH_REG_REG), IDX (INSN_LDUH_REG_REG), FULL (lduh_reg_reg) FAST (lduh_reg_reg) }, - { TYPE (INSN_LDUH_REG_IMM), IDX (INSN_LDUH_REG_IMM), FULL (lduh_reg_imm) FAST (lduh_reg_imm) }, - { TYPE (INSN_LDUH_REG_REG_ASI), IDX (INSN_LDUH_REG_REG_ASI), FULL (lduh_reg_reg_asi) FAST (lduh_reg_reg_asi) }, - { TYPE (INSN_LDSW_REG_REG), IDX (INSN_LDSW_REG_REG), FULL (ldsw_reg_reg) FAST (ldsw_reg_reg) }, - { TYPE (INSN_LDSW_REG_IMM), IDX (INSN_LDSW_REG_IMM), FULL (ldsw_reg_imm) FAST (ldsw_reg_imm) }, - { TYPE (INSN_LDSW_REG_REG_ASI), IDX (INSN_LDSW_REG_REG_ASI), FULL (ldsw_reg_reg_asi) FAST (ldsw_reg_reg_asi) }, - { TYPE (INSN_LDUW_REG_REG), IDX (INSN_LDUW_REG_REG), FULL (lduw_reg_reg) FAST (lduw_reg_reg) }, - { TYPE (INSN_LDUW_REG_IMM), IDX (INSN_LDUW_REG_IMM), FULL (lduw_reg_imm) FAST (lduw_reg_imm) }, - { TYPE (INSN_LDUW_REG_REG_ASI), IDX (INSN_LDUW_REG_REG_ASI), FULL (lduw_reg_reg_asi) FAST (lduw_reg_reg_asi) }, - { TYPE (INSN_LDX_REG_REG), IDX (INSN_LDX_REG_REG), FULL (ldx_reg_reg) FAST (ldx_reg_reg) }, - { TYPE (INSN_LDX_REG_IMM), IDX (INSN_LDX_REG_IMM), FULL (ldx_reg_imm) FAST (ldx_reg_imm) }, - { TYPE (INSN_LDX_REG_REG_ASI), IDX (INSN_LDX_REG_REG_ASI), FULL (ldx_reg_reg_asi) FAST (ldx_reg_reg_asi) }, - { TYPE (INSN_LDD_REG_REG), IDX (INSN_LDD_REG_REG), FULL (ldd_reg_reg) FAST (ldd_reg_reg) }, - { TYPE (INSN_LDD_REG_IMM), IDX (INSN_LDD_REG_IMM), FULL (ldd_reg_imm) FAST (ldd_reg_imm) }, - { TYPE (INSN_LDD_REG_REG_ASI), IDX (INSN_LDD_REG_REG_ASI), FULL (ldd_reg_reg_asi) FAST (ldd_reg_reg_asi) }, - { TYPE (INSN_STB_REG_REG), IDX (INSN_STB_REG_REG), FULL (stb_reg_reg) FAST (stb_reg_reg) }, - { TYPE (INSN_STB_REG_IMM), IDX (INSN_STB_REG_IMM), FULL (stb_reg_imm) FAST (stb_reg_imm) }, - { TYPE (INSN_STB_REG_REG_ASI), IDX (INSN_STB_REG_REG_ASI), FULL (stb_reg_reg_asi) FAST (stb_reg_reg_asi) }, - { TYPE (INSN_STH_REG_REG), IDX (INSN_STH_REG_REG), FULL (sth_reg_reg) FAST (sth_reg_reg) }, - { TYPE (INSN_STH_REG_IMM), IDX (INSN_STH_REG_IMM), FULL (sth_reg_imm) FAST (sth_reg_imm) }, - { TYPE (INSN_STH_REG_REG_ASI), IDX (INSN_STH_REG_REG_ASI), FULL (sth_reg_reg_asi) FAST (sth_reg_reg_asi) }, - { TYPE (INSN_ST_REG_REG), IDX (INSN_ST_REG_REG), FULL (st_reg_reg) FAST (st_reg_reg) }, - { TYPE (INSN_ST_REG_IMM), IDX (INSN_ST_REG_IMM), FULL (st_reg_imm) FAST (st_reg_imm) }, - { TYPE (INSN_ST_REG_REG_ASI), IDX (INSN_ST_REG_REG_ASI), FULL (st_reg_reg_asi) FAST (st_reg_reg_asi) }, - { TYPE (INSN_STX_REG_REG), IDX (INSN_STX_REG_REG), FULL (stx_reg_reg) FAST (stx_reg_reg) }, - { TYPE (INSN_STX_REG_IMM), IDX (INSN_STX_REG_IMM), FULL (stx_reg_imm) FAST (stx_reg_imm) }, - { TYPE (INSN_STX_REG_REG_ASI), IDX (INSN_STX_REG_REG_ASI), FULL (stx_reg_reg_asi) FAST (stx_reg_reg_asi) }, - { TYPE (INSN_STD_REG_REG), IDX (INSN_STD_REG_REG), FULL (std_reg_reg) FAST (std_reg_reg) }, - { TYPE (INSN_STD_REG_IMM), IDX (INSN_STD_REG_IMM), FULL (std_reg_imm) FAST (std_reg_imm) }, - { TYPE (INSN_STD_REG_REG_ASI), IDX (INSN_STD_REG_REG_ASI), FULL (std_reg_reg_asi) FAST (std_reg_reg_asi) }, - { TYPE (INSN_FP_LD_REG_REG), IDX (INSN_FP_LD_REG_REG), FULL (fp_ld_reg_reg) FAST (fp_ld_reg_reg) }, - { TYPE (INSN_FP_LD_REG_IMM), IDX (INSN_FP_LD_REG_IMM), FULL (fp_ld_reg_imm) FAST (fp_ld_reg_imm) }, - { TYPE (INSN_FP_LD_REG_REG_ASI), IDX (INSN_FP_LD_REG_REG_ASI), FULL (fp_ld_reg_reg_asi) FAST (fp_ld_reg_reg_asi) }, - { TYPE (INSN_SETHI), IDX (INSN_SETHI), FULL (sethi) FAST (sethi) }, - { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) }, - { TYPE (INSN_ADD_IMM), IDX (INSN_ADD_IMM), FULL (add_imm) FAST (add_imm) }, - { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) }, - { TYPE (INSN_SUB_IMM), IDX (INSN_SUB_IMM), FULL (sub_imm) FAST (sub_imm) }, - { TYPE (INSN_ADDCC), IDX (INSN_ADDCC), FULL (addcc) FAST (addcc) }, - { TYPE (INSN_ADDCC_IMM), IDX (INSN_ADDCC_IMM), FULL (addcc_imm) FAST (addcc_imm) }, - { TYPE (INSN_SUBCC), IDX (INSN_SUBCC), FULL (subcc) FAST (subcc) }, - { TYPE (INSN_SUBCC_IMM), IDX (INSN_SUBCC_IMM), FULL (subcc_imm) FAST (subcc_imm) }, - { TYPE (INSN_ADDC), IDX (INSN_ADDC), FULL (addc) FAST (addc) }, - { TYPE (INSN_ADDC_IMM), IDX (INSN_ADDC_IMM), FULL (addc_imm) FAST (addc_imm) }, - { TYPE (INSN_SUBC), IDX (INSN_SUBC), FULL (subc) FAST (subc) }, - { TYPE (INSN_SUBC_IMM), IDX (INSN_SUBC_IMM), FULL (subc_imm) FAST (subc_imm) }, - { TYPE (INSN_ADDCCC), IDX (INSN_ADDCCC), FULL (addccc) FAST (addccc) }, - { TYPE (INSN_ADDCCC_IMM), IDX (INSN_ADDCCC_IMM), FULL (addccc_imm) FAST (addccc_imm) }, - { TYPE (INSN_SUBCCC), IDX (INSN_SUBCCC), FULL (subccc) FAST (subccc) }, - { TYPE (INSN_SUBCCC_IMM), IDX (INSN_SUBCCC_IMM), FULL (subccc_imm) FAST (subccc_imm) }, - { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, - { TYPE (INSN_AND_IMM), IDX (INSN_AND_IMM), FULL (and_imm) FAST (and_imm) }, - { TYPE (INSN_ANDCC), IDX (INSN_ANDCC), FULL (andcc) FAST (andcc) }, - { TYPE (INSN_ANDCC_IMM), IDX (INSN_ANDCC_IMM), FULL (andcc_imm) FAST (andcc_imm) }, - { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, - { TYPE (INSN_OR_IMM), IDX (INSN_OR_IMM), FULL (or_imm) FAST (or_imm) }, - { TYPE (INSN_ORCC), IDX (INSN_ORCC), FULL (orcc) FAST (orcc) }, - { TYPE (INSN_ORCC_IMM), IDX (INSN_ORCC_IMM), FULL (orcc_imm) FAST (orcc_imm) }, - { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, - { TYPE (INSN_XOR_IMM), IDX (INSN_XOR_IMM), FULL (xor_imm) FAST (xor_imm) }, - { TYPE (INSN_XORCC), IDX (INSN_XORCC), FULL (xorcc) FAST (xorcc) }, - { TYPE (INSN_XORCC_IMM), IDX (INSN_XORCC_IMM), FULL (xorcc_imm) FAST (xorcc_imm) }, - { TYPE (INSN_ANDN), IDX (INSN_ANDN), FULL (andn) FAST (andn) }, - { TYPE (INSN_ANDN_IMM), IDX (INSN_ANDN_IMM), FULL (andn_imm) FAST (andn_imm) }, - { TYPE (INSN_ANDNCC), IDX (INSN_ANDNCC), FULL (andncc) FAST (andncc) }, - { TYPE (INSN_ANDNCC_IMM), IDX (INSN_ANDNCC_IMM), FULL (andncc_imm) FAST (andncc_imm) }, - { TYPE (INSN_ORN), IDX (INSN_ORN), FULL (orn) FAST (orn) }, - { TYPE (INSN_ORN_IMM), IDX (INSN_ORN_IMM), FULL (orn_imm) FAST (orn_imm) }, - { TYPE (INSN_ORNCC), IDX (INSN_ORNCC), FULL (orncc) FAST (orncc) }, - { TYPE (INSN_ORNCC_IMM), IDX (INSN_ORNCC_IMM), FULL (orncc_imm) FAST (orncc_imm) }, - { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) }, - { TYPE (INSN_XNOR_IMM), IDX (INSN_XNOR_IMM), FULL (xnor_imm) FAST (xnor_imm) }, - { TYPE (INSN_XNORCC), IDX (INSN_XNORCC), FULL (xnorcc) FAST (xnorcc) }, - { TYPE (INSN_XNORCC_IMM), IDX (INSN_XNORCC_IMM), FULL (xnorcc_imm) FAST (xnorcc_imm) }, - { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) }, - { TYPE (INSN_SLL_IMM), IDX (INSN_SLL_IMM), FULL (sll_imm) FAST (sll_imm) }, - { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) }, - { TYPE (INSN_SRL_IMM), IDX (INSN_SRL_IMM), FULL (srl_imm) FAST (srl_imm) }, - { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) }, - { TYPE (INSN_SRA_IMM), IDX (INSN_SRA_IMM), FULL (sra_imm) FAST (sra_imm) }, - { TYPE (INSN_SMUL), IDX (INSN_SMUL), FULL (smul) FAST (smul) }, - { TYPE (INSN_SMUL_IMM), IDX (INSN_SMUL_IMM), FULL (smul_imm) FAST (smul_imm) }, - { TYPE (INSN_SMUL_CC), IDX (INSN_SMUL_CC), FULL (smul_cc) FAST (smul_cc) }, - { TYPE (INSN_SMUL_CC_IMM), IDX (INSN_SMUL_CC_IMM), FULL (smul_cc_imm) FAST (smul_cc_imm) }, - { TYPE (INSN_UMUL), IDX (INSN_UMUL), FULL (umul) FAST (umul) }, - { TYPE (INSN_UMUL_IMM), IDX (INSN_UMUL_IMM), FULL (umul_imm) FAST (umul_imm) }, - { TYPE (INSN_UMUL_CC), IDX (INSN_UMUL_CC), FULL (umul_cc) FAST (umul_cc) }, - { TYPE (INSN_UMUL_CC_IMM), IDX (INSN_UMUL_CC_IMM), FULL (umul_cc_imm) FAST (umul_cc_imm) }, - { TYPE (INSN_MULSCC), IDX (INSN_MULSCC), FULL (mulscc) FAST (mulscc) }, - { TYPE (INSN_SAVE), IDX (INSN_SAVE), FULL (save) FAST (save) }, - { TYPE (INSN_SAVE_IMM), IDX (INSN_SAVE_IMM), FULL (save_imm) FAST (save_imm) }, - { TYPE (INSN_RESTORE), IDX (INSN_RESTORE), FULL (restore) FAST (restore) }, - { TYPE (INSN_RESTORE_IMM), IDX (INSN_RESTORE_IMM), FULL (restore_imm) FAST (restore_imm) }, - { TYPE (INSN_RETT), IDX (INSN_RETT), FULL (rett) FAST (rett) }, - { TYPE (INSN_RETT_IMM), IDX (INSN_RETT_IMM), FULL (rett_imm) FAST (rett_imm) }, - { TYPE (INSN_UNIMP), IDX (INSN_UNIMP), FULL (unimp) FAST (unimp) }, - { TYPE (INSN_CALL), IDX (INSN_CALL), FULL (call) FAST (call) }, - { TYPE (INSN_JMPL), IDX (INSN_JMPL), FULL (jmpl) FAST (jmpl) }, - { TYPE (INSN_JMPL_IMM), IDX (INSN_JMPL_IMM), FULL (jmpl_imm) FAST (jmpl_imm) }, - { TYPE (INSN_BA), IDX (INSN_BA), FULL (ba) FAST (ba) }, - { TYPE (INSN_TA), IDX (INSN_TA), FULL (ta) FAST (ta) }, - { TYPE (INSN_TA_IMM), IDX (INSN_TA_IMM), FULL (ta_imm) FAST (ta_imm) }, - { TYPE (INSN_BN), IDX (INSN_BN), FULL (bn) FAST (bn) }, - { TYPE (INSN_TN), IDX (INSN_TN), FULL (tn) FAST (tn) }, - { TYPE (INSN_TN_IMM), IDX (INSN_TN_IMM), FULL (tn_imm) FAST (tn_imm) }, - { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, - { TYPE (INSN_TNE), IDX (INSN_TNE), FULL (tne) FAST (tne) }, - { TYPE (INSN_TNE_IMM), IDX (INSN_TNE_IMM), FULL (tne_imm) FAST (tne_imm) }, - { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) }, - { TYPE (INSN_TE), IDX (INSN_TE), FULL (te) FAST (te) }, - { TYPE (INSN_TE_IMM), IDX (INSN_TE_IMM), FULL (te_imm) FAST (te_imm) }, - { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) }, - { TYPE (INSN_TG), IDX (INSN_TG), FULL (tg) FAST (tg) }, - { TYPE (INSN_TG_IMM), IDX (INSN_TG_IMM), FULL (tg_imm) FAST (tg_imm) }, - { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, - { TYPE (INSN_TLE), IDX (INSN_TLE), FULL (tle) FAST (tle) }, - { TYPE (INSN_TLE_IMM), IDX (INSN_TLE_IMM), FULL (tle_imm) FAST (tle_imm) }, - { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, - { TYPE (INSN_TGE), IDX (INSN_TGE), FULL (tge) FAST (tge) }, - { TYPE (INSN_TGE_IMM), IDX (INSN_TGE_IMM), FULL (tge_imm) FAST (tge_imm) }, - { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) }, - { TYPE (INSN_TL), IDX (INSN_TL), FULL (tl) FAST (tl) }, - { TYPE (INSN_TL_IMM), IDX (INSN_TL_IMM), FULL (tl_imm) FAST (tl_imm) }, - { TYPE (INSN_BGU), IDX (INSN_BGU), FULL (bgu) FAST (bgu) }, - { TYPE (INSN_TGU), IDX (INSN_TGU), FULL (tgu) FAST (tgu) }, - { TYPE (INSN_TGU_IMM), IDX (INSN_TGU_IMM), FULL (tgu_imm) FAST (tgu_imm) }, - { TYPE (INSN_BLEU), IDX (INSN_BLEU), FULL (bleu) FAST (bleu) }, - { TYPE (INSN_TLEU), IDX (INSN_TLEU), FULL (tleu) FAST (tleu) }, - { TYPE (INSN_TLEU_IMM), IDX (INSN_TLEU_IMM), FULL (tleu_imm) FAST (tleu_imm) }, - { TYPE (INSN_BCC), IDX (INSN_BCC), FULL (bcc) FAST (bcc) }, - { TYPE (INSN_TCC), IDX (INSN_TCC), FULL (tcc) FAST (tcc) }, - { TYPE (INSN_TCC_IMM), IDX (INSN_TCC_IMM), FULL (tcc_imm) FAST (tcc_imm) }, - { TYPE (INSN_BCS), IDX (INSN_BCS), FULL (bcs) FAST (bcs) }, - { TYPE (INSN_TCS), IDX (INSN_TCS), FULL (tcs) FAST (tcs) }, - { TYPE (INSN_TCS_IMM), IDX (INSN_TCS_IMM), FULL (tcs_imm) FAST (tcs_imm) }, - { TYPE (INSN_BPOS), IDX (INSN_BPOS), FULL (bpos) FAST (bpos) }, - { TYPE (INSN_TPOS), IDX (INSN_TPOS), FULL (tpos) FAST (tpos) }, - { TYPE (INSN_TPOS_IMM), IDX (INSN_TPOS_IMM), FULL (tpos_imm) FAST (tpos_imm) }, - { TYPE (INSN_BNEG), IDX (INSN_BNEG), FULL (bneg) FAST (bneg) }, - { TYPE (INSN_TNEG), IDX (INSN_TNEG), FULL (tneg) FAST (tneg) }, - { TYPE (INSN_TNEG_IMM), IDX (INSN_TNEG_IMM), FULL (tneg_imm) FAST (tneg_imm) }, - { TYPE (INSN_BVC), IDX (INSN_BVC), FULL (bvc) FAST (bvc) }, - { TYPE (INSN_TVC), IDX (INSN_TVC), FULL (tvc) FAST (tvc) }, - { TYPE (INSN_TVC_IMM), IDX (INSN_TVC_IMM), FULL (tvc_imm) FAST (tvc_imm) }, - { TYPE (INSN_BVS), IDX (INSN_BVS), FULL (bvs) FAST (bvs) }, - { TYPE (INSN_TVS), IDX (INSN_TVS), FULL (tvs) FAST (tvs) }, - { TYPE (INSN_TVS_IMM), IDX (INSN_TVS_IMM), FULL (tvs_imm) FAST (tvs_imm) }, - { TYPE (INSN_LDSTUB_REG_REG), IDX (INSN_LDSTUB_REG_REG), FULL (ldstub_reg_reg) FAST (ldstub_reg_reg) }, - { TYPE (INSN_LDSTUB_REG_IMM), IDX (INSN_LDSTUB_REG_IMM), FULL (ldstub_reg_imm) FAST (ldstub_reg_imm) }, - { TYPE (INSN_LDSTUB_REG_REG_ASI), IDX (INSN_LDSTUB_REG_REG_ASI), FULL (ldstub_reg_reg_asi) FAST (ldstub_reg_reg_asi) }, - { TYPE (INSN_SWAP_REG_REG), IDX (INSN_SWAP_REG_REG), FULL (swap_reg_reg) FAST (swap_reg_reg) }, - { TYPE (INSN_SWAP_REG_IMM), IDX (INSN_SWAP_REG_IMM), FULL (swap_reg_imm) FAST (swap_reg_imm) }, - { TYPE (INSN_SWAP_REG_REG_ASI), IDX (INSN_SWAP_REG_REG_ASI), FULL (swap_reg_reg_asi) FAST (swap_reg_reg_asi) }, -}; - -static const struct insn_sem sparc64_insn_sem_invalid = -{ - VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) -}; - -#undef IDX -#undef TYPE - -/* Initialize an IDESC from the compile-time computable parts. */ - -static INLINE void -init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) -{ - const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; - - id->num = t->index; - if ((int) t->type <= 0) - id->idata = & cgen_virtual_insn_table[- (int) t->type]; - else - id->idata = & insn_table[t->type]; - id->attrs = CGEN_INSN_ATTRS (id->idata); - /* Oh my god, a magic number. */ - id->length = CGEN_INSN_BITSIZE (id->idata) / 8; -#if ! WITH_SEM_SWITCH_FULL - id->sem_full = t->sem_full; -#endif -#if WITH_FAST && ! WITH_SEM_SWITCH_FAST - id->sem_fast = t->sem_fast; -#endif -#if WITH_PROFILE_MODEL_P - id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; - { - SIM_DESC sd = CPU_STATE (cpu); - SIM_ASSERT (t->index == id->timing->num); - } -#endif -} - -/* Initialize the instruction descriptor table. */ - -void -sparc64_init_idesc_table (SIM_CPU *cpu) -{ - IDESC *id,*tabend; - const struct insn_sem *t,*tend; - int tabsize = SPARC64_INSN_MAX; - IDESC *table = sparc64_insn_data; - - memset (table, 0, tabsize * sizeof (IDESC)); - - /* First set all entries to the `invalid insn'. */ - t = & sparc64_insn_sem_invalid; - for (id = table, tabend = table + tabsize; id < tabend; ++id) - init_idesc (cpu, id, t); - - /* Now fill in the values for the chosen cpu. */ - for (t = sparc64_insn_sem, tend = t + sizeof (sparc64_insn_sem) / sizeof (*t); - t != tend; ++t) - { - init_idesc (cpu, & table[t->index], t); - } - - /* Link the IDESC table into the cpu. */ - CPU_IDESC (cpu) = table; -} - -#define GOTO_EXTRACT(id) goto extract - -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) -#endif - -/* Given an instruction, return a pointer to its IDESC entry. */ - -const IDESC * -sparc64_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, - ARGBUF *abuf) -{ - /* Result. */ - const IDESC *idecode; - - { -#define I(insn) & sparc64_insn_data[CONCAT2 (SPARC64_,insn)] - CGEN_INSN_INT insn = base_insn; - static const IDESC *idecode_invalid = I (INSN_X_INVALID); - - { -#ifdef __GNUC__ - static const void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_12, && case_0_13, && default_0, && default_0, - && case_0_16, && case_0_17, && case_0_18, && case_0_19, - && case_0_20, && case_0_21, && case_0_22, && case_0_23, - && case_0_24, && case_0_25, && case_0_26, && case_0_27, - && case_0_28, && case_0_29, && case_0_30, && case_0_31, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_128, && case_0_129, && case_0_130, && case_0_131, - && case_0_132, && case_0_133, && case_0_134, && case_0_135, - && case_0_136, && default_0, && case_0_138, && case_0_139, - && case_0_140, && default_0, && default_0, && default_0, - && case_0_144, && case_0_145, && case_0_146, && case_0_147, - && case_0_148, && case_0_149, && case_0_150, && case_0_151, - && case_0_152, && default_0, && case_0_154, && case_0_155, - && case_0_156, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && case_0_165, && case_0_166, && case_0_167, - && default_0, && default_0, && default_0, && default_0, - && case_0_172, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_184, && case_0_185, && case_0_186, && case_0_187, - && case_0_188, && case_0_189, && case_0_190, && default_0, - && case_0_192, && case_0_193, && case_0_194, && case_0_195, - && case_0_196, && case_0_197, && case_0_198, && case_0_199, - && case_0_200, && case_0_201, && case_0_202, && case_0_203, - && default_0, && case_0_205, && case_0_206, && case_0_207, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && case_0_224, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - }; -#endif - static const IDESC * insns[256] = { - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_UNIMP), I (INSN_UNIMP), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_SETHI), I (INSN_SETHI), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - I (INSN_CALL), I (INSN_CALL), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MULSCC), 0, - 0, 0, - I (INSN_MEMBAR), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_FLUSHW), - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_IMPDEP1), I (INSN_IMPDEP2), - 0, 0, - 0, 0, - 0, 0, - 0, I (INSN_X_INVALID), - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - I (INSN_X_INVALID), 0, - 0, 0, - I (INSN_LDUW_REG_REG_ASI), I (INSN_LDUB_REG_REG_ASI), - I (INSN_LDUH_REG_REG_ASI), I (INSN_LDD_REG_REG_ASI), - I (INSN_ST_REG_REG_ASI), I (INSN_STB_REG_REG_ASI), - I (INSN_STH_REG_REG_ASI), I (INSN_STD_REG_REG_ASI), - I (INSN_LDSW_REG_REG_ASI), I (INSN_LDSB_REG_REG_ASI), - I (INSN_LDSH_REG_REG_ASI), I (INSN_LDX_REG_REG_ASI), - I (INSN_X_INVALID), I (INSN_LDSTUB_REG_REG_ASI), - I (INSN_STX_REG_REG_ASI), I (INSN_SWAP_REG_REG_ASI), - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_FP_LD_REG_REG_ASI), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 24) & (3 << 6)) | ((insn >> 19) & (63 << 0))); - DECODE_SWITCH (0, val) - { - CASE (0, 12) : /* fall through */ - CASE (0, 13) : - { - static const IDESC * insns[16] = { - I (INSN_BPCC_BN), I (INSN_BPCC_BE), - I (INSN_BPCC_BLE), I (INSN_BPCC_BL), - I (INSN_BPCC_BLEU), I (INSN_BPCC_BCS), - I (INSN_BPCC_BNEG), I (INSN_BPCC_BVS), - I (INSN_BPCC_BA), I (INSN_BPCC_BNE), - I (INSN_BPCC_BG), I (INSN_BPCC_BGE), - I (INSN_BPCC_BGU), I (INSN_BPCC_BCC), - I (INSN_BPCC_BPOS), I (INSN_BPCC_BVC), - }; - unsigned int val = (((insn >> 25) & (15 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 16) : /* fall through */ - CASE (0, 17) : /* fall through */ - CASE (0, 18) : /* fall through */ - CASE (0, 19) : /* fall through */ - CASE (0, 20) : /* fall through */ - CASE (0, 21) : /* fall through */ - CASE (0, 22) : /* fall through */ - CASE (0, 23) : - { - static const IDESC * insns[16] = { - I (INSN_BN), I (INSN_BE), - I (INSN_BLE), I (INSN_BL), - I (INSN_BLEU), I (INSN_BCS), - I (INSN_BNEG), I (INSN_BVS), - I (INSN_BA), I (INSN_BNE), - I (INSN_BG), I (INSN_BGE), - I (INSN_BGU), I (INSN_BCC), - I (INSN_BPOS), I (INSN_BVC), - }; - unsigned int val = (((insn >> 25) & (15 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 24) : /* fall through */ - CASE (0, 25) : /* fall through */ - CASE (0, 26) : /* fall through */ - CASE (0, 27) : /* fall through */ - CASE (0, 28) : /* fall through */ - CASE (0, 29) : /* fall through */ - CASE (0, 30) : /* fall through */ - CASE (0, 31) : - { - static const IDESC * insns[8] = { - I (INSN_X_INVALID), I (INSN_BEQZ), - I (INSN_BLEZ), I (INSN_BLTZ), - I (INSN_X_INVALID), I (INSN_BNEZ), - I (INSN_BGTZ), I (INSN_BGEZ), - }; - unsigned int val = (((insn >> 25) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 128) : - { - static const IDESC * insns[2] = { - I (INSN_ADD), I (INSN_ADD_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 129) : - { - static const IDESC * insns[2] = { - I (INSN_AND), I (INSN_AND_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 130) : - { - static const IDESC * insns[2] = { - I (INSN_OR), I (INSN_OR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 131) : - { - static const IDESC * insns[2] = { - I (INSN_XOR), I (INSN_XOR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 132) : - { - static const IDESC * insns[2] = { - I (INSN_SUB), I (INSN_SUB_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 133) : - { - static const IDESC * insns[2] = { - I (INSN_ANDN), I (INSN_ANDN_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 134) : - { - static const IDESC * insns[2] = { - I (INSN_ORN), I (INSN_ORN_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 135) : - { - static const IDESC * insns[2] = { - I (INSN_XNOR), I (INSN_XNOR_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 136) : - { - static const IDESC * insns[2] = { - I (INSN_ADDC), I (INSN_ADDC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 138) : - { - static const IDESC * insns[2] = { - I (INSN_UMUL), I (INSN_UMUL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 139) : - { - static const IDESC * insns[2] = { - I (INSN_SMUL), I (INSN_SMUL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 140) : - { - static const IDESC * insns[2] = { - I (INSN_SUBC), I (INSN_SUBC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 144) : - { - static const IDESC * insns[2] = { - I (INSN_ADDCC), I (INSN_ADDCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 145) : - { - static const IDESC * insns[2] = { - I (INSN_ANDCC), I (INSN_ANDCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 146) : - { - static const IDESC * insns[2] = { - I (INSN_ORCC), I (INSN_ORCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 147) : - { - static const IDESC * insns[2] = { - I (INSN_XORCC), I (INSN_XORCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 148) : - { - static const IDESC * insns[2] = { - I (INSN_SUBCC), I (INSN_SUBCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 149) : - { - static const IDESC * insns[2] = { - I (INSN_ANDNCC), I (INSN_ANDNCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 150) : - { - static const IDESC * insns[2] = { - I (INSN_ORNCC), I (INSN_ORNCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 151) : - { - static const IDESC * insns[2] = { - I (INSN_XNORCC), I (INSN_XNORCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 152) : - { - static const IDESC * insns[2] = { - I (INSN_ADDCCC), I (INSN_ADDCCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 154) : - { - static const IDESC * insns[2] = { - I (INSN_UMUL_CC), I (INSN_UMUL_CC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 155) : - { - static const IDESC * insns[2] = { - I (INSN_SMUL_CC), I (INSN_SMUL_CC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 156) : - { - static const IDESC * insns[2] = { - I (INSN_SUBCCC), I (INSN_SUBCCC_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 165) : - { - static const IDESC * insns[2] = { - I (INSN_SLL), I (INSN_SLL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 166) : - { - static const IDESC * insns[2] = { - I (INSN_SRL), I (INSN_SRL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 167) : - { - static const IDESC * insns[2] = { - I (INSN_SRA), I (INSN_SRA_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 172) : - { -#ifdef __GNUC__ - static const void *labels_0_172[16] = { - && case_0_172_0, && case_0_172_1, && case_0_172_2, && case_0_172_3, - && case_0_172_4, && case_0_172_5, && case_0_172_6, && case_0_172_7, - && case_0_172_8, && case_0_172_9, && case_0_172_10, && case_0_172_11, - && case_0_172_12, && case_0_172_13, && case_0_172_14, && case_0_172_15, - }; -#endif - unsigned int val; - val = (((insn >> 25) & (15 << 0))); - DECODE_SWITCH (0_172, val) - { - CASE (0_172, 0) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVN_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVN_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVN_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVN_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 1) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVE_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVE_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVE_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVE_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 2) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVLE_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVLE_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVLE_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVLE_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 3) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVL_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVL_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVL_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVL_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 4) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVLEU_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVLEU_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVLEU_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVLEU_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 5) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVCS_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVCS_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVCS_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVCS_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 6) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVNEG_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVNEG_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVNEG_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVNEG_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 7) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVVS_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVVS_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVVS_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVVS_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 8) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVA_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVA_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVA_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVA_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 9) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVNE_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVNE_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVNE_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVNE_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 10) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVG_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVG_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVG_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVG_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 11) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVGE_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVGE_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVGE_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVGE_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 12) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVGU_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVGU_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVGU_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVGU_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 13) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVCC_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVCC_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVCC_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVCC_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 14) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVPOS_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVPOS_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVPOS_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVPOS_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_172, 15) : - { - static const IDESC * insns[16] = { - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_MOVVC_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVVC_XCC_XCC), I (INSN_X_INVALID), - I (INSN_MOVVC_IMM_ICC_ICC), I (INSN_X_INVALID), - I (INSN_MOVVC_IMM_XCC_XCC), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 15) & (1 << 3)) | ((insn >> 11) & (7 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_172) : - idecode = idecode_invalid; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_172) - } - CASE (0, 184) : - { - static const IDESC * insns[2] = { - I (INSN_JMPL), I (INSN_JMPL_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 185) : - { -#ifdef __GNUC__ - static const void *labels_0_185[16] = { - && case_0_185_0, && default_0_185, && default_0_185, && default_0_185, - && default_0_185, && default_0_185, && default_0_185, && default_0_185, - && default_0_185, && default_0_185, && default_0_185, && default_0_185, - && default_0_185, && default_0_185, && default_0_185, && default_0_185, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_185, val) - { - CASE (0_185, 0) : - { - static const IDESC * insns[4] = { - I (INSN_RETT), I (INSN_RETT_IMM), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_185) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_185) - } - CASE (0, 186) : - { -#ifdef __GNUC__ - static const void *labels_0_186[16] = { - && case_0_186_0, && case_0_186_1, && case_0_186_2, && case_0_186_3, - && case_0_186_4, && case_0_186_5, && case_0_186_6, && case_0_186_7, - && default_0_186, && default_0_186, && default_0_186, && default_0_186, - && default_0_186, && default_0_186, && default_0_186, && default_0_186, - }; -#endif - static const IDESC * insns[16] = { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_186, val) - { - CASE (0_186, 0) : - { - static const IDESC * insns[4] = { - I (INSN_TN), I (INSN_TN_IMM), - I (INSN_TE), I (INSN_TE_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 1) : - { - static const IDESC * insns[4] = { - I (INSN_TLE), I (INSN_TLE_IMM), - I (INSN_TL), I (INSN_TL_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 2) : - { - static const IDESC * insns[4] = { - I (INSN_TLEU), I (INSN_TLEU_IMM), - I (INSN_TCS), I (INSN_TCS_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 3) : - { - static const IDESC * insns[4] = { - I (INSN_TNEG), I (INSN_TNEG_IMM), - I (INSN_TVS), I (INSN_TVS_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 4) : - { - static const IDESC * insns[4] = { - I (INSN_TA), I (INSN_TA_IMM), - I (INSN_TNE), I (INSN_TNE_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 5) : - { - static const IDESC * insns[4] = { - I (INSN_TG), I (INSN_TG_IMM), - I (INSN_TGE), I (INSN_TGE_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 6) : - { - static const IDESC * insns[4] = { - I (INSN_TGU), I (INSN_TGU_IMM), - I (INSN_TCC), I (INSN_TCC_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0_186, 7) : - { - static const IDESC * insns[4] = { - I (INSN_TPOS), I (INSN_TPOS_IMM), - I (INSN_TVC), I (INSN_TVC_IMM), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_186) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_186) - } - CASE (0, 187) : - { -#ifdef __GNUC__ - static const void *labels_0_187[16] = { - && case_0_187_0, && default_0_187, && default_0_187, && default_0_187, - && default_0_187, && default_0_187, && default_0_187, && default_0_187, - && default_0_187, && default_0_187, && default_0_187, && default_0_187, - && default_0_187, && default_0_187, && default_0_187, && default_0_187, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_187, val) - { - CASE (0_187, 0) : - { - static const IDESC * insns[4] = { - I (INSN_FLUSH), I (INSN_FLUSH_IMM), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_187) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_187) - } - CASE (0, 188) : - { - static const IDESC * insns[2] = { - I (INSN_SAVE), I (INSN_SAVE_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 189) : - { - static const IDESC * insns[2] = { - I (INSN_RESTORE), I (INSN_RESTORE_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 190) : - { -#ifdef __GNUC__ - static const void *labels_0_190[16] = { - && case_0_190_0, && default_0_190, && default_0_190, && default_0_190, - && default_0_190, && default_0_190, && default_0_190, && default_0_190, - && default_0_190, && default_0_190, && default_0_190, && default_0_190, - && default_0_190, && default_0_190, && default_0_190, && default_0_190, - }; -#endif - static const IDESC * insns[16] = { - 0, I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - I (INSN_X_INVALID), I (INSN_X_INVALID), - }; - unsigned int val; - val = (((insn >> 26) & (15 << 0))); - DECODE_SWITCH (0_190, val) - { - CASE (0_190, 0) : - { - static const IDESC * insns[2] = { - I (INSN_DONE), I (INSN_RETRY), - }; - unsigned int val = (((insn >> 25) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0_190) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0_190) - } - CASE (0, 192) : - { - static const IDESC * insns[2] = { - I (INSN_LDUW_REG_REG), I (INSN_LDUW_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 193) : - { - static const IDESC * insns[2] = { - I (INSN_LDUB_REG_REG), I (INSN_LDUB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 194) : - { - static const IDESC * insns[2] = { - I (INSN_LDUH_REG_REG), I (INSN_LDUH_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 195) : - { - static const IDESC * insns[2] = { - I (INSN_LDD_REG_REG), I (INSN_LDD_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 196) : - { - static const IDESC * insns[2] = { - I (INSN_ST_REG_REG), I (INSN_ST_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 197) : - { - static const IDESC * insns[2] = { - I (INSN_STB_REG_REG), I (INSN_STB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 198) : - { - static const IDESC * insns[2] = { - I (INSN_STH_REG_REG), I (INSN_STH_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 199) : - { - static const IDESC * insns[2] = { - I (INSN_STD_REG_REG), I (INSN_STD_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 200) : - { - static const IDESC * insns[2] = { - I (INSN_LDSW_REG_REG), I (INSN_LDSW_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 201) : - { - static const IDESC * insns[2] = { - I (INSN_LDSB_REG_REG), I (INSN_LDSB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 202) : - { - static const IDESC * insns[2] = { - I (INSN_LDSH_REG_REG), I (INSN_LDSH_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 203) : - { - static const IDESC * insns[2] = { - I (INSN_LDX_REG_REG), I (INSN_LDX_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 205) : - { - static const IDESC * insns[2] = { - I (INSN_LDSTUB_REG_REG), I (INSN_LDSTUB_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 206) : - { - static const IDESC * insns[2] = { - I (INSN_STX_REG_REG), I (INSN_STX_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 207) : - { - static const IDESC * insns[2] = { - I (INSN_SWAP_REG_REG), I (INSN_SWAP_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - CASE (0, 224) : - { - static const IDESC * insns[2] = { - I (INSN_FP_LD_REG_REG), I (INSN_FP_LD_REG_IMM), - }; - unsigned int val = (((insn >> 13) & (1 << 0))); - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - DEFAULT (0) : - idecode = insns[val]; - GOTO_EXTRACT (idecode); - } - ENDSWITCH (0) - } -#undef I -#undef E - } - - /* Extraction is defered until the semantic code. */ - - extract: - return idecode; -} diff --git a/sim/sparc/decode64.h b/sim/sparc/decode64.h deleted file mode 100644 index 373d5e3..0000000 --- a/sim/sparc/decode64.h +++ /dev/null @@ -1,385 +0,0 @@ -/* Decode header for sparc64. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef SPARC64_DECODE_H -#define SPARC64_DECODE_H - -extern const IDESC *sparc64_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, - ARGBUF *); -extern void sparc64_init_idesc_table (SIM_CPU *); - -/* Enum declaration for instructions in cpu family sparc64. */ -typedef enum sparc64_insn_type { - SPARC64_INSN_X_INVALID, SPARC64_INSN_X_AFTER, SPARC64_INSN_X_BEFORE, SPARC64_INSN_X_CTI_CHAIN - , SPARC64_INSN_X_CHAIN, SPARC64_INSN_X_BEGIN, SPARC64_INSN_BEQZ, SPARC64_INSN_BGEZ - , SPARC64_INSN_BGTZ, SPARC64_INSN_BLEZ, SPARC64_INSN_BLTZ, SPARC64_INSN_BNEZ - , SPARC64_INSN_BPCC_BA, SPARC64_INSN_BPCC_BN, SPARC64_INSN_BPCC_BNE, SPARC64_INSN_BPCC_BE - , SPARC64_INSN_BPCC_BG, SPARC64_INSN_BPCC_BLE, SPARC64_INSN_BPCC_BGE, SPARC64_INSN_BPCC_BL - , SPARC64_INSN_BPCC_BGU, SPARC64_INSN_BPCC_BLEU, SPARC64_INSN_BPCC_BCC, SPARC64_INSN_BPCC_BCS - , SPARC64_INSN_BPCC_BPOS, SPARC64_INSN_BPCC_BNEG, SPARC64_INSN_BPCC_BVC, SPARC64_INSN_BPCC_BVS - , SPARC64_INSN_DONE, SPARC64_INSN_RETRY, SPARC64_INSN_FLUSH, SPARC64_INSN_FLUSH_IMM - , SPARC64_INSN_FLUSHW, SPARC64_INSN_IMPDEP1, SPARC64_INSN_IMPDEP2, SPARC64_INSN_MEMBAR - , SPARC64_INSN_MOVA_ICC_ICC, SPARC64_INSN_MOVA_IMM_ICC_ICC, SPARC64_INSN_MOVA_XCC_XCC, SPARC64_INSN_MOVA_IMM_XCC_XCC - , SPARC64_INSN_MOVN_ICC_ICC, SPARC64_INSN_MOVN_IMM_ICC_ICC, SPARC64_INSN_MOVN_XCC_XCC, SPARC64_INSN_MOVN_IMM_XCC_XCC - , SPARC64_INSN_MOVNE_ICC_ICC, SPARC64_INSN_MOVNE_IMM_ICC_ICC, SPARC64_INSN_MOVNE_XCC_XCC, SPARC64_INSN_MOVNE_IMM_XCC_XCC - , SPARC64_INSN_MOVE_ICC_ICC, SPARC64_INSN_MOVE_IMM_ICC_ICC, SPARC64_INSN_MOVE_XCC_XCC, SPARC64_INSN_MOVE_IMM_XCC_XCC - , SPARC64_INSN_MOVG_ICC_ICC, SPARC64_INSN_MOVG_IMM_ICC_ICC, SPARC64_INSN_MOVG_XCC_XCC, SPARC64_INSN_MOVG_IMM_XCC_XCC - , SPARC64_INSN_MOVLE_ICC_ICC, SPARC64_INSN_MOVLE_IMM_ICC_ICC, SPARC64_INSN_MOVLE_XCC_XCC, SPARC64_INSN_MOVLE_IMM_XCC_XCC - , SPARC64_INSN_MOVGE_ICC_ICC, SPARC64_INSN_MOVGE_IMM_ICC_ICC, SPARC64_INSN_MOVGE_XCC_XCC, SPARC64_INSN_MOVGE_IMM_XCC_XCC - , SPARC64_INSN_MOVL_ICC_ICC, SPARC64_INSN_MOVL_IMM_ICC_ICC, SPARC64_INSN_MOVL_XCC_XCC, SPARC64_INSN_MOVL_IMM_XCC_XCC - , SPARC64_INSN_MOVGU_ICC_ICC, SPARC64_INSN_MOVGU_IMM_ICC_ICC, SPARC64_INSN_MOVGU_XCC_XCC, SPARC64_INSN_MOVGU_IMM_XCC_XCC - , SPARC64_INSN_MOVLEU_ICC_ICC, SPARC64_INSN_MOVLEU_IMM_ICC_ICC, SPARC64_INSN_MOVLEU_XCC_XCC, SPARC64_INSN_MOVLEU_IMM_XCC_XCC - , SPARC64_INSN_MOVCC_ICC_ICC, SPARC64_INSN_MOVCC_IMM_ICC_ICC, SPARC64_INSN_MOVCC_XCC_XCC, SPARC64_INSN_MOVCC_IMM_XCC_XCC - , SPARC64_INSN_MOVCS_ICC_ICC, SPARC64_INSN_MOVCS_IMM_ICC_ICC, SPARC64_INSN_MOVCS_XCC_XCC, SPARC64_INSN_MOVCS_IMM_XCC_XCC - , SPARC64_INSN_MOVPOS_ICC_ICC, SPARC64_INSN_MOVPOS_IMM_ICC_ICC, SPARC64_INSN_MOVPOS_XCC_XCC, SPARC64_INSN_MOVPOS_IMM_XCC_XCC - , SPARC64_INSN_MOVNEG_ICC_ICC, SPARC64_INSN_MOVNEG_IMM_ICC_ICC, SPARC64_INSN_MOVNEG_XCC_XCC, SPARC64_INSN_MOVNEG_IMM_XCC_XCC - , SPARC64_INSN_MOVVC_ICC_ICC, SPARC64_INSN_MOVVC_IMM_ICC_ICC, SPARC64_INSN_MOVVC_XCC_XCC, SPARC64_INSN_MOVVC_IMM_XCC_XCC - , SPARC64_INSN_MOVVS_ICC_ICC, SPARC64_INSN_MOVVS_IMM_ICC_ICC, SPARC64_INSN_MOVVS_XCC_XCC, SPARC64_INSN_MOVVS_IMM_XCC_XCC - , SPARC64_INSN_LDSB_REG_REG, SPARC64_INSN_LDSB_REG_IMM, SPARC64_INSN_LDSB_REG_REG_ASI, SPARC64_INSN_LDUB_REG_REG - , SPARC64_INSN_LDUB_REG_IMM, SPARC64_INSN_LDUB_REG_REG_ASI, SPARC64_INSN_LDSH_REG_REG, SPARC64_INSN_LDSH_REG_IMM - , SPARC64_INSN_LDSH_REG_REG_ASI, SPARC64_INSN_LDUH_REG_REG, SPARC64_INSN_LDUH_REG_IMM, SPARC64_INSN_LDUH_REG_REG_ASI - , SPARC64_INSN_LDSW_REG_REG, SPARC64_INSN_LDSW_REG_IMM, SPARC64_INSN_LDSW_REG_REG_ASI, SPARC64_INSN_LDUW_REG_REG - , SPARC64_INSN_LDUW_REG_IMM, SPARC64_INSN_LDUW_REG_REG_ASI, SPARC64_INSN_LDX_REG_REG, SPARC64_INSN_LDX_REG_IMM - , SPARC64_INSN_LDX_REG_REG_ASI, SPARC64_INSN_LDD_REG_REG, SPARC64_INSN_LDD_REG_IMM, SPARC64_INSN_LDD_REG_REG_ASI - , SPARC64_INSN_STB_REG_REG, SPARC64_INSN_STB_REG_IMM, SPARC64_INSN_STB_REG_REG_ASI, SPARC64_INSN_STH_REG_REG - , SPARC64_INSN_STH_REG_IMM, SPARC64_INSN_STH_REG_REG_ASI, SPARC64_INSN_ST_REG_REG, SPARC64_INSN_ST_REG_IMM - , SPARC64_INSN_ST_REG_REG_ASI, SPARC64_INSN_STX_REG_REG, SPARC64_INSN_STX_REG_IMM, SPARC64_INSN_STX_REG_REG_ASI - , SPARC64_INSN_STD_REG_REG, SPARC64_INSN_STD_REG_IMM, SPARC64_INSN_STD_REG_REG_ASI, SPARC64_INSN_FP_LD_REG_REG - , SPARC64_INSN_FP_LD_REG_IMM, SPARC64_INSN_FP_LD_REG_REG_ASI, SPARC64_INSN_SETHI, SPARC64_INSN_ADD - , SPARC64_INSN_ADD_IMM, SPARC64_INSN_SUB, SPARC64_INSN_SUB_IMM, SPARC64_INSN_ADDCC - , SPARC64_INSN_ADDCC_IMM, SPARC64_INSN_SUBCC, SPARC64_INSN_SUBCC_IMM, SPARC64_INSN_ADDC - , SPARC64_INSN_ADDC_IMM, SPARC64_INSN_SUBC, SPARC64_INSN_SUBC_IMM, SPARC64_INSN_ADDCCC - , SPARC64_INSN_ADDCCC_IMM, SPARC64_INSN_SUBCCC, SPARC64_INSN_SUBCCC_IMM, SPARC64_INSN_AND - , SPARC64_INSN_AND_IMM, SPARC64_INSN_ANDCC, SPARC64_INSN_ANDCC_IMM, SPARC64_INSN_OR - , SPARC64_INSN_OR_IMM, SPARC64_INSN_ORCC, SPARC64_INSN_ORCC_IMM, SPARC64_INSN_XOR - , SPARC64_INSN_XOR_IMM, SPARC64_INSN_XORCC, SPARC64_INSN_XORCC_IMM, SPARC64_INSN_ANDN - , SPARC64_INSN_ANDN_IMM, SPARC64_INSN_ANDNCC, SPARC64_INSN_ANDNCC_IMM, SPARC64_INSN_ORN - , SPARC64_INSN_ORN_IMM, SPARC64_INSN_ORNCC, SPARC64_INSN_ORNCC_IMM, SPARC64_INSN_XNOR - , SPARC64_INSN_XNOR_IMM, SPARC64_INSN_XNORCC, SPARC64_INSN_XNORCC_IMM, SPARC64_INSN_SLL - , SPARC64_INSN_SLL_IMM, SPARC64_INSN_SRL, SPARC64_INSN_SRL_IMM, SPARC64_INSN_SRA - , SPARC64_INSN_SRA_IMM, SPARC64_INSN_SMUL, SPARC64_INSN_SMUL_IMM, SPARC64_INSN_SMUL_CC - , SPARC64_INSN_SMUL_CC_IMM, SPARC64_INSN_UMUL, SPARC64_INSN_UMUL_IMM, SPARC64_INSN_UMUL_CC - , SPARC64_INSN_UMUL_CC_IMM, SPARC64_INSN_MULSCC, SPARC64_INSN_SAVE, SPARC64_INSN_SAVE_IMM - , SPARC64_INSN_RESTORE, SPARC64_INSN_RESTORE_IMM, SPARC64_INSN_RETT, SPARC64_INSN_RETT_IMM - , SPARC64_INSN_UNIMP, SPARC64_INSN_CALL, SPARC64_INSN_JMPL, SPARC64_INSN_JMPL_IMM - , SPARC64_INSN_BA, SPARC64_INSN_TA, SPARC64_INSN_TA_IMM, SPARC64_INSN_BN - , SPARC64_INSN_TN, SPARC64_INSN_TN_IMM, SPARC64_INSN_BNE, SPARC64_INSN_TNE - , SPARC64_INSN_TNE_IMM, SPARC64_INSN_BE, SPARC64_INSN_TE, SPARC64_INSN_TE_IMM - , SPARC64_INSN_BG, SPARC64_INSN_TG, SPARC64_INSN_TG_IMM, SPARC64_INSN_BLE - , SPARC64_INSN_TLE, SPARC64_INSN_TLE_IMM, SPARC64_INSN_BGE, SPARC64_INSN_TGE - , SPARC64_INSN_TGE_IMM, SPARC64_INSN_BL, SPARC64_INSN_TL, SPARC64_INSN_TL_IMM - , SPARC64_INSN_BGU, SPARC64_INSN_TGU, SPARC64_INSN_TGU_IMM, SPARC64_INSN_BLEU - , SPARC64_INSN_TLEU, SPARC64_INSN_TLEU_IMM, SPARC64_INSN_BCC, SPARC64_INSN_TCC - , SPARC64_INSN_TCC_IMM, SPARC64_INSN_BCS, SPARC64_INSN_TCS, SPARC64_INSN_TCS_IMM - , SPARC64_INSN_BPOS, SPARC64_INSN_TPOS, SPARC64_INSN_TPOS_IMM, SPARC64_INSN_BNEG - , SPARC64_INSN_TNEG, SPARC64_INSN_TNEG_IMM, SPARC64_INSN_BVC, SPARC64_INSN_TVC - , SPARC64_INSN_TVC_IMM, SPARC64_INSN_BVS, SPARC64_INSN_TVS, SPARC64_INSN_TVS_IMM - , SPARC64_INSN_LDSTUB_REG_REG, SPARC64_INSN_LDSTUB_REG_IMM, SPARC64_INSN_LDSTUB_REG_REG_ASI, SPARC64_INSN_SWAP_REG_REG - , SPARC64_INSN_SWAP_REG_IMM, SPARC64_INSN_SWAP_REG_REG_ASI, SPARC64_INSN_MAX -} SPARC64_INSN_TYPE; - -#if ! WITH_SEM_SWITCH_FULL -#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,fn); -#else -#define SEMFULL(fn) -#endif - -#if ! WITH_SEM_SWITCH_FAST -#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc64,_semf_,fn); -#else -#define SEMFAST(fn) -#endif - -#define SEM(fn) SEMFULL (fn) SEMFAST (fn) - -/* The function version of the before/after handlers is always needed, - so we always want the SEMFULL declaration of them. */ -extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_before); -extern SEMANTIC_FN CONCAT3 (sparc64,_sem_,x_after); - -SEM (x_invalid) -SEM (x_after) -SEM (x_before) -SEM (x_cti_chain) -SEM (x_chain) -SEM (x_begin) -SEM (beqz) -SEM (bgez) -SEM (bgtz) -SEM (blez) -SEM (bltz) -SEM (bnez) -SEM (bpcc_ba) -SEM (bpcc_bn) -SEM (bpcc_bne) -SEM (bpcc_be) -SEM (bpcc_bg) -SEM (bpcc_ble) -SEM (bpcc_bge) -SEM (bpcc_bl) -SEM (bpcc_bgu) -SEM (bpcc_bleu) -SEM (bpcc_bcc) -SEM (bpcc_bcs) -SEM (bpcc_bpos) -SEM (bpcc_bneg) -SEM (bpcc_bvc) -SEM (bpcc_bvs) -SEM (done) -SEM (retry) -SEM (flush) -SEM (flush_imm) -SEM (flushw) -SEM (impdep1) -SEM (impdep2) -SEM (membar) -SEM (mova_icc_icc) -SEM (mova_imm_icc_icc) -SEM (mova_xcc_xcc) -SEM (mova_imm_xcc_xcc) -SEM (movn_icc_icc) -SEM (movn_imm_icc_icc) -SEM (movn_xcc_xcc) -SEM (movn_imm_xcc_xcc) -SEM (movne_icc_icc) -SEM (movne_imm_icc_icc) -SEM (movne_xcc_xcc) -SEM (movne_imm_xcc_xcc) -SEM (move_icc_icc) -SEM (move_imm_icc_icc) -SEM (move_xcc_xcc) -SEM (move_imm_xcc_xcc) -SEM (movg_icc_icc) -SEM (movg_imm_icc_icc) -SEM (movg_xcc_xcc) -SEM (movg_imm_xcc_xcc) -SEM (movle_icc_icc) -SEM (movle_imm_icc_icc) -SEM (movle_xcc_xcc) -SEM (movle_imm_xcc_xcc) -SEM (movge_icc_icc) -SEM (movge_imm_icc_icc) -SEM (movge_xcc_xcc) -SEM (movge_imm_xcc_xcc) -SEM (movl_icc_icc) -SEM (movl_imm_icc_icc) -SEM (movl_xcc_xcc) -SEM (movl_imm_xcc_xcc) -SEM (movgu_icc_icc) -SEM (movgu_imm_icc_icc) -SEM (movgu_xcc_xcc) -SEM (movgu_imm_xcc_xcc) -SEM (movleu_icc_icc) -SEM (movleu_imm_icc_icc) -SEM (movleu_xcc_xcc) -SEM (movleu_imm_xcc_xcc) -SEM (movcc_icc_icc) -SEM (movcc_imm_icc_icc) -SEM (movcc_xcc_xcc) -SEM (movcc_imm_xcc_xcc) -SEM (movcs_icc_icc) -SEM (movcs_imm_icc_icc) -SEM (movcs_xcc_xcc) -SEM (movcs_imm_xcc_xcc) -SEM (movpos_icc_icc) -SEM (movpos_imm_icc_icc) -SEM (movpos_xcc_xcc) -SEM (movpos_imm_xcc_xcc) -SEM (movneg_icc_icc) -SEM (movneg_imm_icc_icc) -SEM (movneg_xcc_xcc) -SEM (movneg_imm_xcc_xcc) -SEM (movvc_icc_icc) -SEM (movvc_imm_icc_icc) -SEM (movvc_xcc_xcc) -SEM (movvc_imm_xcc_xcc) -SEM (movvs_icc_icc) -SEM (movvs_imm_icc_icc) -SEM (movvs_xcc_xcc) -SEM (movvs_imm_xcc_xcc) -SEM (ldsb_reg_reg) -SEM (ldsb_reg_imm) -SEM (ldsb_reg_reg_asi) -SEM (ldub_reg_reg) -SEM (ldub_reg_imm) -SEM (ldub_reg_reg_asi) -SEM (ldsh_reg_reg) -SEM (ldsh_reg_imm) -SEM (ldsh_reg_reg_asi) -SEM (lduh_reg_reg) -SEM (lduh_reg_imm) -SEM (lduh_reg_reg_asi) -SEM (ldsw_reg_reg) -SEM (ldsw_reg_imm) -SEM (ldsw_reg_reg_asi) -SEM (lduw_reg_reg) -SEM (lduw_reg_imm) -SEM (lduw_reg_reg_asi) -SEM (ldx_reg_reg) -SEM (ldx_reg_imm) -SEM (ldx_reg_reg_asi) -SEM (ldd_reg_reg) -SEM (ldd_reg_imm) -SEM (ldd_reg_reg_asi) -SEM (stb_reg_reg) -SEM (stb_reg_imm) -SEM (stb_reg_reg_asi) -SEM (sth_reg_reg) -SEM (sth_reg_imm) -SEM (sth_reg_reg_asi) -SEM (st_reg_reg) -SEM (st_reg_imm) -SEM (st_reg_reg_asi) -SEM (stx_reg_reg) -SEM (stx_reg_imm) -SEM (stx_reg_reg_asi) -SEM (std_reg_reg) -SEM (std_reg_imm) -SEM (std_reg_reg_asi) -SEM (fp_ld_reg_reg) -SEM (fp_ld_reg_imm) -SEM (fp_ld_reg_reg_asi) -SEM (sethi) -SEM (add) -SEM (add_imm) -SEM (sub) -SEM (sub_imm) -SEM (addcc) -SEM (addcc_imm) -SEM (subcc) -SEM (subcc_imm) -SEM (addc) -SEM (addc_imm) -SEM (subc) -SEM (subc_imm) -SEM (addccc) -SEM (addccc_imm) -SEM (subccc) -SEM (subccc_imm) -SEM (and) -SEM (and_imm) -SEM (andcc) -SEM (andcc_imm) -SEM (or) -SEM (or_imm) -SEM (orcc) -SEM (orcc_imm) -SEM (xor) -SEM (xor_imm) -SEM (xorcc) -SEM (xorcc_imm) -SEM (andn) -SEM (andn_imm) -SEM (andncc) -SEM (andncc_imm) -SEM (orn) -SEM (orn_imm) -SEM (orncc) -SEM (orncc_imm) -SEM (xnor) -SEM (xnor_imm) -SEM (xnorcc) -SEM (xnorcc_imm) -SEM (sll) -SEM (sll_imm) -SEM (srl) -SEM (srl_imm) -SEM (sra) -SEM (sra_imm) -SEM (smul) -SEM (smul_imm) -SEM (smul_cc) -SEM (smul_cc_imm) -SEM (umul) -SEM (umul_imm) -SEM (umul_cc) -SEM (umul_cc_imm) -SEM (mulscc) -SEM (save) -SEM (save_imm) -SEM (restore) -SEM (restore_imm) -SEM (rett) -SEM (rett_imm) -SEM (unimp) -SEM (call) -SEM (jmpl) -SEM (jmpl_imm) -SEM (ba) -SEM (ta) -SEM (ta_imm) -SEM (bn) -SEM (tn) -SEM (tn_imm) -SEM (bne) -SEM (tne) -SEM (tne_imm) -SEM (be) -SEM (te) -SEM (te_imm) -SEM (bg) -SEM (tg) -SEM (tg_imm) -SEM (ble) -SEM (tle) -SEM (tle_imm) -SEM (bge) -SEM (tge) -SEM (tge_imm) -SEM (bl) -SEM (tl) -SEM (tl_imm) -SEM (bgu) -SEM (tgu) -SEM (tgu_imm) -SEM (bleu) -SEM (tleu) -SEM (tleu_imm) -SEM (bcc) -SEM (tcc) -SEM (tcc_imm) -SEM (bcs) -SEM (tcs) -SEM (tcs_imm) -SEM (bpos) -SEM (tpos) -SEM (tpos_imm) -SEM (bneg) -SEM (tneg) -SEM (tneg_imm) -SEM (bvc) -SEM (tvc) -SEM (tvc_imm) -SEM (bvs) -SEM (tvs) -SEM (tvs_imm) -SEM (ldstub_reg_reg) -SEM (ldstub_reg_imm) -SEM (ldstub_reg_reg_asi) -SEM (swap_reg_reg) -SEM (swap_reg_imm) -SEM (swap_reg_reg_asi) - -#undef SEMFULL -#undef SEMFAST -#undef SEM - -/* Function unit handlers (user written). */ - -extern int sparc64_model_sparc64_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); - -/* Profiling before/after handlers (user written) */ - -extern void sparc64_model_insn_before (SIM_CPU *, int /*first_p*/); -extern void sparc64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); - -#endif /* SPARC64_DECODE_H */ diff --git a/sim/sparc/dev32.c b/sim/sparc/dev32.c deleted file mode 100644 index 52a47ae..0000000 --- a/sim/sparc/dev32.c +++ /dev/null @@ -1,98 +0,0 @@ -/* sparc device support - Copyright (C) 1999 Cygnus Solutions. */ - -#include "sim-main.h" -#include "dev32.h" - -#ifdef HAVE_DV_SOCKSER -#include "dv-sockser.h" -#endif - -/* ??? At present this is to match erc32 so outbyte works. */ - -device sparc_devices; - -int -device_io_read_buffer (device *me, void *source, int space, - address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) -{ - SIM_DESC sd = CPU_STATE (cpu); - - if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) - return nr_bytes; - -#ifdef HAVE_DV_SOCKSER - if (addr == UART_INCHAR_ADDR) - { - int c = dv_sockser_read (sd); - if (c == -1) - return 0; - *(char *) source = c; - return 1; - } - if (addr == UART_STATUS_ADDR) - { - int status = dv_sockser_status (sd); - unsigned char *p = source; - p[0] = 0; - p[1] = (((status & DV_SOCKSER_INPUT_EMPTY) -#ifdef UART_INPUT_READY0 - ? UART_INPUT_READY : 0) -#else - ? 0 : UART_INPUT_READY) -#endif - + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0)); - return 2; - } -#endif - - /* erc32 compatibility */ - if (addr == RXSTAT) - { - int Ucontrol = 0; - unsigned char *p = source; - Ucontrol |= 1; - Ucontrol |= 0x00060006; - SETTSI (p, Ucontrol); - } - - return nr_bytes; -} - -int -device_io_write_buffer (device *me, const void *source, int space, - address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) -{ - SIM_DESC sd = CPU_STATE (cpu); - -#if 0 && WITH_SCACHE - if (addr == MCCR_ADDR) - { - if ((*(const char *) source & MCCR_CP) != 0) - scache_flush (sd); - return nr_bytes; - } -#endif - - if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) - return nr_bytes; - -#ifdef HAVE_DV_SOCKSER - if (addr == UART_OUTCHAR_ADDR) - { - int rc = dv_sockser_write (sd, *(char *) source); - return rc == 1; - } -#endif - - if (addr == RXADATA) - { - sim_io_printf (sd, "%c", GETTSI (source)); - } - - return nr_bytes; -} - -void device_error () {} diff --git a/sim/sparc/dev32.h b/sim/sparc/dev32.h deleted file mode 100644 index 44c79ac..0000000 --- a/sim/sparc/dev32.h +++ /dev/null @@ -1,21 +0,0 @@ -/* sparc device support - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef DEVICES_H -#define DEVICES_H - -/* From libgloss/sparc/erc32-io.c. */ - -#define ERC32_DEVICE_ADDR 0x1f80000 -#define ERC32_DEVICE_LEN (0x2000000 - 0x1f80000) - -#define RXADATA 0x01F800E0 -#define RXBDATA 0x01F800E4 -#define RXSTAT 0x01F800E8 - -extern device sparc_devices; - -/* FIXME: Temporary, until device support ready. */ -struct _device { int foo; }; - -#endif /* DEVICES_H */ diff --git a/sim/sparc/dev64.c b/sim/sparc/dev64.c deleted file mode 100644 index 73236a4..0000000 --- a/sim/sparc/dev64.c +++ /dev/null @@ -1,9 +0,0 @@ -/* sparc64 device support - Copyright (C) 1999 Cygnus Solutions. */ - -#include "sim-main.h" -#include "dev64.h" - -#ifdef HAVE_DV_SOCKSER -#include "dv-sockser.h" -#endif diff --git a/sim/sparc/dev64.h b/sim/sparc/dev64.h deleted file mode 100644 index 689e0e7..0000000 --- a/sim/sparc/dev64.h +++ /dev/null @@ -1,21 +0,0 @@ -/* sparc64 device support - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef DEV64_H -#define DEV64_H - -/* From libgloss/sparc/erc32-io.c. */ - -#define ERC32_DEVICE_ADDR 0x1f80000 -#define ERC32_DEVICE_LEN (0x2000000 - 0x1f80000) - -#define RXADATA 0x01F800E0 -#define RXBDATA 0x01F800E4 -#define RXSTAT 0x01F800E8 - -extern device sparc_devices; - -/* FIXME: Temporary, until device support ready. */ -struct _device { int foo; }; - -#endif /* DEV64_H */ diff --git a/sim/sparc/mloop32.in b/sim/sparc/mloop32.in deleted file mode 100644 index effc19a..0000000 --- a/sim/sparc/mloop32.in +++ /dev/null @@ -1,133 +0,0 @@ -# Simulator main loop for sparc. -*- C -*- -# Copyright (C) 1999 Cygnus Solutions. - -# Syntax: -# /bin/sh mainloop.in command -# -# Command is one of: -# -# init -# support -# extract-{simple,scache,pbb} -# {full,fast}-exec-{simple,scache,pbb} -# -# A target need only provide a "full" version of one of simple,scache,pbb. -# If the target wants it can also provide a fast version of same, or if -# the slow (full featured) version is `simple', then the fast version can be -# one of scache/pbb. -# A target can't provide more than this. - -# ??? After a few more ports are done, revisit. -# Will eventually need to machine generate a lot of this. - -case "x$1" in - -xsupport) - -cat <<EOF - -static INLINE void -execute (SIM_CPU *current_cpu, SCACHE *sc) -{ - ARGBUF *abuf = &sc->argbuf; - IADDR pc = GET_H_PC (); - USI insn = GETIMEMUSI (current_cpu, pc); - int fast_p = STATE_RUN_FAST_P (CPU_STATE (current_cpu)); - - if (fast_p) - { - const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); - - @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); - (*id->sem_full) (current_cpu, sc, insn); - } - else - { - const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); - const CGEN_INSN *opcode = id->opcode; - int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); - int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); - - @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); - @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p); - - /* FIXME: call x-before */ - if (ARGBUF_PROFILE_P (abuf)) - PROFILE_COUNT_INSN (current_cpu, pc, id->num); - /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ - if (PROFILE_MODEL_P (current_cpu) - && ARGBUF_PROFILE_P (abuf)) - @cpu@_model_insn_before (current_cpu, 1 /*first_p*/); - TRACE_INSN_INIT (current_cpu, abuf, 1); - TRACE_INSN (current_cpu, opcode, abuf, pc); - - (*id->sem_full) (current_cpu, sc, insn); - - /* FIXME: call x-after */ - if (PROFILE_MODEL_P (current_cpu) - && ARGBUF_PROFILE_P (abuf)) - { - int cycles; - - cycles = (*id->timing->model_fn) (current_cpu, sc); - @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles); - } - TRACE_INSN_FINI (current_cpu, abuf, 1); - } -} - -static INLINE void -do_annul (SIM_CPU *current_cpu) -{ - IADDR npc = GET_H_NPC (); - - /* ??? log profiling data */ - /* ??? anything else */ - - SET_H_PC (npc); - SET_H_NPC (npc + 4); -} - -EOF - -;; - -xinit) - -# Nothing needed. - -;; - -xfull-exec-simple) - -# Inputs: current_cpu, sc, FAST_P -# Outputs: none, instruction is fetched and executed -# Recorded PC is updated after every insn. -# ??? Use of `sc' is a bit of a hack as we don't use the scache. -# We do however use ARGBUF so for consistency with the other engine flavours -# sc is used. - -cat <<EOF - -{ - if (GET_H_ANNUL_P ()) - { - do_annul (current_cpu); - SET_H_ANNUL_P (0); - } - else - { - execute (current_cpu, sc); - } -} - -EOF - -;; - -*) - echo "Invalid argument to mainloop.in: $1" >&2 - exit 1 - ;; - -esac diff --git a/sim/sparc/mloop64.in b/sim/sparc/mloop64.in deleted file mode 100644 index 1fd570e..0000000 --- a/sim/sparc/mloop64.in +++ /dev/null @@ -1,133 +0,0 @@ -# Simulator main loop for sparc64. -*- C -*- -# Copyright (C) 1999 Cygnus Solutions. - -# Syntax: -# /bin/sh mainloop.in command -# -# Command is one of: -# -# init -# support -# extract-{simple,scache,pbb} -# {full,fast}-exec-{simple,scache,pbb} -# -# A target need only provide a "full" version of one of simple,scache,pbb. -# If the target wants it can also provide a fast version of same, or if -# the slow (full featured) version is `simple', then the fast version can be -# one of scache/pbb. -# A target can't provide more than this. - -# ??? After a few more ports are done, revisit. -# Will eventually need to machine generate a lot of this. - -case "x$1" in - -xsupport) - -cat <<EOF - -static INLINE void -execute (SIM_CPU *current_cpu, SCACHE *sc) -{ - ARGBUF *abuf = &sc->argbuf; - IADDR pc = GET_H_PC (); - USI insn = GETIMEMUSI (current_cpu, pc); - int fast_p = STATE_RUN_FAST_P (CPU_STATE (current_cpu)); - - if (fast_p) - { - const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); - - @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); - (*id->sem_full) (current_cpu, sc, insn); - } - else - { - const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf); - const CGEN_INSN *idata = id->idata; - int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); - int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); - - @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); - @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p); - - /* FIXME: call x-before */ - if (ARGBUF_PROFILE_P (abuf)) - PROFILE_COUNT_INSN (current_cpu, pc, id->num); - /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ - if (PROFILE_MODEL_P (current_cpu) - && ARGBUF_PROFILE_P (abuf)) - @cpu@_model_insn_before (current_cpu, 1 /*first_p*/); - TRACE_INSN_INIT (current_cpu, abuf, 1); - TRACE_INSN (current_cpu, idata, abuf, pc); - - (*id->sem_full) (current_cpu, sc, insn); - - /* FIXME: call x-after */ - if (PROFILE_MODEL_P (current_cpu) - && ARGBUF_PROFILE_P (abuf)) - { - int cycles; - - cycles = (*id->timing->model_fn) (current_cpu, sc); - @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles); - } - TRACE_INSN_FINI (current_cpu, abuf, 1); - } -} - -static INLINE void -do_annul (SIM_CPU *current_cpu) -{ - IADDR npc = GET_H_NPC (); - - /* ??? log profiling data */ - /* ??? anything else */ - - SET_H_PC (npc); - SET_H_NPC (npc + 4); -} - -EOF - -;; - -xinit) - -# Nothing needed. - -;; - -xfull-exec-simple) - -# Inputs: current_cpu, sc, FAST_P -# Outputs: none, instruction is fetched and executed -# Recorded PC is updated after every insn. -# ??? Use of `sc' is a bit of a hack as we don't use the scache. -# We do however use ARGBUF so for consistency with the other engine flavours -# sc is used. - -cat <<EOF - -{ - if (GET_H_ANNUL_P ()) - { - do_annul (current_cpu); - SET_H_ANNUL_P (0); - } - else - { - execute (current_cpu, sc); - } -} - -EOF - -;; - -*) - echo "Invalid argument to mainloop.in: $1" >&2 - exit 1 - ;; - -esac diff --git a/sim/sparc/model32.c b/sim/sparc/model32.c deleted file mode 100644 index ba2e8d5..0000000 --- a/sim/sparc/model32.c +++ /dev/null @@ -1,3516 +0,0 @@ -/* Simulator model support for sparc32. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc32 -#define WANT_CPU_SPARC32 - -#include "sim-main.h" - -/* The profiling data is recorded here, but is accessed via the profiling - mechanism. After all, this is information for profiling. */ - -#if WITH_PROFILE_MODEL_P - -/* Model handlers for each insn. */ - -static int -model_sparc32_def_rd_asr (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_RD_ASR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_ASR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_asr (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_ASR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_ASR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_asr_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_ASR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_ASR_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_rd_psr (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_psr (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_psr_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_rd_wim (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_wim (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_wim_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_rd_tbr (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_tbr (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_wr_tbr_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldstub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldstub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldstub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_swap_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_swap_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_swap_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_lduh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_lduh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_lduh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldsw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_lduw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_lduw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_lduw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldd_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldd_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ldd_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_stb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_stb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_stb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sth_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sth_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sth_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_st_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_st_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_st_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_std_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_std_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_std_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_fp_ld_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_fp_ld_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_fp_ld_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sethi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ - EXTRACT_IFMT_SETHI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_add (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_add_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sub (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sub_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_addcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_addcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_subcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_subcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_addx (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_addx_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_subx (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_subx_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_addxcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_addxcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_subxcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_subxcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_and (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_and_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_andcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_andcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_or (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_or_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_orcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_orcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xor (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xor_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xorcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xorcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_andn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_andn_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_andncc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_andncc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_orn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_orn_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_orncc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_orncc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xnor (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xnor_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xnorcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_xnorcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sll (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sll_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_srl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_srl_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sra (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sra_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_smul (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_smul_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_smul_cc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_smul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_umul (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_umul_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_umul_cc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_umul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sdiv (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sdiv_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sdiv_cc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_sdiv_cc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_udiv (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_udiv_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_udiv_cc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_udiv_cc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_mulscc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_save (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_save_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_restore (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_restore_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_rett (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_rett_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_unimp (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ - EXTRACT_IFMT_UNIMP_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_call (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ - IADDR i_disp30; - EXTRACT_IFMT_CALL_CODE - i_disp30 = f_disp30; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_jmpl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_jmpl_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ba (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ta (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ta_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_BA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tn_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bne (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tne (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tne_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_be (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_te (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_te_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_ble (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tle (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tle_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bge (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tge (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tge_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tl_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bgu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tgu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tgu_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bleu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tleu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tleu_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bcs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tcs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tcs_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bpos (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tpos (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tpos_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bneg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tneg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tneg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bvc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tvc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tvc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_bvs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tvs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc32_def_tvs_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc32_model_sparc32_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -/* We assume UNIT_NONE == 0 because the tables don't always terminate - entries with it. */ - -/* Model timing data for `sparc32-def'. */ - -static const INSN_TIMING sparc32_def_timing[] = { - { SPARC32_INSN_X_INVALID, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_X_AFTER, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_X_BEFORE, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_X_CHAIN, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_X_BEGIN, 0, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RD_ASR, model_sparc32_def_rd_asr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_ASR, model_sparc32_def_wr_asr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_ASR_IMM, model_sparc32_def_wr_asr_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RD_PSR, model_sparc32_def_rd_psr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_PSR, model_sparc32_def_wr_psr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_PSR_IMM, model_sparc32_def_wr_psr_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RD_WIM, model_sparc32_def_rd_wim, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_WIM, model_sparc32_def_wr_wim, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_WIM_IMM, model_sparc32_def_wr_wim_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RD_TBR, model_sparc32_def_rd_tbr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_TBR, model_sparc32_def_wr_tbr, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_WR_TBR_IMM, model_sparc32_def_wr_tbr_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSTUB_REG_REG, model_sparc32_def_ldstub_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSTUB_REG_IMM, model_sparc32_def_ldstub_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSTUB_REG_REG_ASI, model_sparc32_def_ldstub_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SWAP_REG_REG, model_sparc32_def_swap_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SWAP_REG_IMM, model_sparc32_def_swap_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SWAP_REG_REG_ASI, model_sparc32_def_swap_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSB_REG_REG, model_sparc32_def_ldsb_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSB_REG_IMM, model_sparc32_def_ldsb_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSB_REG_REG_ASI, model_sparc32_def_ldsb_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUB_REG_REG, model_sparc32_def_ldub_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUB_REG_IMM, model_sparc32_def_ldub_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUB_REG_REG_ASI, model_sparc32_def_ldub_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSH_REG_REG, model_sparc32_def_ldsh_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSH_REG_IMM, model_sparc32_def_ldsh_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSH_REG_REG_ASI, model_sparc32_def_ldsh_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUH_REG_REG, model_sparc32_def_lduh_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUH_REG_IMM, model_sparc32_def_lduh_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUH_REG_REG_ASI, model_sparc32_def_lduh_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSW_REG_REG, model_sparc32_def_ldsw_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSW_REG_IMM, model_sparc32_def_ldsw_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDSW_REG_REG_ASI, model_sparc32_def_ldsw_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUW_REG_REG, model_sparc32_def_lduw_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUW_REG_IMM, model_sparc32_def_lduw_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDUW_REG_REG_ASI, model_sparc32_def_lduw_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDD_REG_REG, model_sparc32_def_ldd_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDD_REG_IMM, model_sparc32_def_ldd_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_LDD_REG_REG_ASI, model_sparc32_def_ldd_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STB_REG_REG, model_sparc32_def_stb_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STB_REG_IMM, model_sparc32_def_stb_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STB_REG_REG_ASI, model_sparc32_def_stb_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STH_REG_REG, model_sparc32_def_sth_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STH_REG_IMM, model_sparc32_def_sth_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STH_REG_REG_ASI, model_sparc32_def_sth_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ST_REG_REG, model_sparc32_def_st_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ST_REG_IMM, model_sparc32_def_st_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ST_REG_REG_ASI, model_sparc32_def_st_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STD_REG_REG, model_sparc32_def_std_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STD_REG_IMM, model_sparc32_def_std_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_STD_REG_REG_ASI, model_sparc32_def_std_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_FP_LD_REG_REG, model_sparc32_def_fp_ld_reg_reg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_FP_LD_REG_IMM, model_sparc32_def_fp_ld_reg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_FP_LD_REG_REG_ASI, model_sparc32_def_fp_ld_reg_reg_asi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SETHI, model_sparc32_def_sethi, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADD, model_sparc32_def_add, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADD_IMM, model_sparc32_def_add_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUB, model_sparc32_def_sub, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUB_IMM, model_sparc32_def_sub_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADDCC, model_sparc32_def_addcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADDCC_IMM, model_sparc32_def_addcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUBCC, model_sparc32_def_subcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUBCC_IMM, model_sparc32_def_subcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADDX, model_sparc32_def_addx, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADDX_IMM, model_sparc32_def_addx_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUBX, model_sparc32_def_subx, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUBX_IMM, model_sparc32_def_subx_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADDXCC, model_sparc32_def_addxcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ADDXCC_IMM, model_sparc32_def_addxcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUBXCC, model_sparc32_def_subxcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SUBXCC_IMM, model_sparc32_def_subxcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_AND, model_sparc32_def_and, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_AND_IMM, model_sparc32_def_and_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ANDCC, model_sparc32_def_andcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ANDCC_IMM, model_sparc32_def_andcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_OR, model_sparc32_def_or, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_OR_IMM, model_sparc32_def_or_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ORCC, model_sparc32_def_orcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ORCC_IMM, model_sparc32_def_orcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XOR, model_sparc32_def_xor, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XOR_IMM, model_sparc32_def_xor_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XORCC, model_sparc32_def_xorcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XORCC_IMM, model_sparc32_def_xorcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ANDN, model_sparc32_def_andn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ANDN_IMM, model_sparc32_def_andn_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ANDNCC, model_sparc32_def_andncc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ANDNCC_IMM, model_sparc32_def_andncc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ORN, model_sparc32_def_orn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ORN_IMM, model_sparc32_def_orn_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ORNCC, model_sparc32_def_orncc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_ORNCC_IMM, model_sparc32_def_orncc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XNOR, model_sparc32_def_xnor, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XNOR_IMM, model_sparc32_def_xnor_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XNORCC, model_sparc32_def_xnorcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_XNORCC_IMM, model_sparc32_def_xnorcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SLL, model_sparc32_def_sll, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SLL_IMM, model_sparc32_def_sll_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SRL, model_sparc32_def_srl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SRL_IMM, model_sparc32_def_srl_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SRA, model_sparc32_def_sra, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SRA_IMM, model_sparc32_def_sra_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SMUL, model_sparc32_def_smul, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SMUL_IMM, model_sparc32_def_smul_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SMUL_CC, model_sparc32_def_smul_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SMUL_CC_IMM, model_sparc32_def_smul_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UMUL, model_sparc32_def_umul, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UMUL_IMM, model_sparc32_def_umul_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UMUL_CC, model_sparc32_def_umul_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UMUL_CC_IMM, model_sparc32_def_umul_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SDIV, model_sparc32_def_sdiv, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SDIV_IMM, model_sparc32_def_sdiv_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SDIV_CC, model_sparc32_def_sdiv_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SDIV_CC_IMM, model_sparc32_def_sdiv_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UDIV, model_sparc32_def_udiv, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UDIV_IMM, model_sparc32_def_udiv_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UDIV_CC, model_sparc32_def_udiv_cc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UDIV_CC_IMM, model_sparc32_def_udiv_cc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_MULSCC, model_sparc32_def_mulscc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SAVE, model_sparc32_def_save, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_SAVE_IMM, model_sparc32_def_save_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RESTORE, model_sparc32_def_restore, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RESTORE_IMM, model_sparc32_def_restore_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RETT, model_sparc32_def_rett, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_RETT_IMM, model_sparc32_def_rett_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_UNIMP, model_sparc32_def_unimp, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_CALL, model_sparc32_def_call, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_JMPL, model_sparc32_def_jmpl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_JMPL_IMM, model_sparc32_def_jmpl_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BA, model_sparc32_def_ba, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TA, model_sparc32_def_ta, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TA_IMM, model_sparc32_def_ta_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BN, model_sparc32_def_bn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TN, model_sparc32_def_tn, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TN_IMM, model_sparc32_def_tn_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BNE, model_sparc32_def_bne, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TNE, model_sparc32_def_tne, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TNE_IMM, model_sparc32_def_tne_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BE, model_sparc32_def_be, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TE, model_sparc32_def_te, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TE_IMM, model_sparc32_def_te_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BG, model_sparc32_def_bg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TG, model_sparc32_def_tg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TG_IMM, model_sparc32_def_tg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BLE, model_sparc32_def_ble, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TLE, model_sparc32_def_tle, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TLE_IMM, model_sparc32_def_tle_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BGE, model_sparc32_def_bge, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TGE, model_sparc32_def_tge, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TGE_IMM, model_sparc32_def_tge_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BL, model_sparc32_def_bl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TL, model_sparc32_def_tl, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TL_IMM, model_sparc32_def_tl_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BGU, model_sparc32_def_bgu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TGU, model_sparc32_def_tgu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TGU_IMM, model_sparc32_def_tgu_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BLEU, model_sparc32_def_bleu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TLEU, model_sparc32_def_tleu, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TLEU_IMM, model_sparc32_def_tleu_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BCC, model_sparc32_def_bcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TCC, model_sparc32_def_tcc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TCC_IMM, model_sparc32_def_tcc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BCS, model_sparc32_def_bcs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TCS, model_sparc32_def_tcs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TCS_IMM, model_sparc32_def_tcs_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BPOS, model_sparc32_def_bpos, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TPOS, model_sparc32_def_tpos, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TPOS_IMM, model_sparc32_def_tpos_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BNEG, model_sparc32_def_bneg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TNEG, model_sparc32_def_tneg, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TNEG_IMM, model_sparc32_def_tneg_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BVC, model_sparc32_def_bvc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TVC, model_sparc32_def_tvc, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TVC_IMM, model_sparc32_def_tvc_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_BVS, model_sparc32_def_bvs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TVS, model_sparc32_def_tvs, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, - { SPARC32_INSN_TVS_IMM, model_sparc32_def_tvs_imm, { { (int) UNIT_SPARC32_DEF_U_EXEC, 1, 1 } } }, -}; - -#endif /* WITH_PROFILE_MODEL_P */ - -static void -sparc32_def_model_init (SIM_CPU *cpu) -{ - CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SPARC32_DEF_DATA)); -} - -#if WITH_PROFILE_MODEL_P -#define TIMING_DATA(td) td -#else -#define TIMING_DATA(td) 0 -#endif - -static const MODEL sparc_v8_models[] = -{ - { "sparc32-def", & sparc_v8_mach, MODEL_SPARC32_DEF, TIMING_DATA (& sparc32_def_timing[0]), sparc32_def_model_init }, - { 0 } -}; - -static const MODEL sparclite_models[] = -{ - { 0 } -}; - -/* The properties of this cpu's implementation. */ - -static const MACH_IMP_PROPERTIES sparc32_imp_properties = -{ - sizeof (SIM_CPU), -#if WITH_SCACHE - sizeof (SCACHE) -#else - 0 -#endif -}; - - -static void -sparc32_prepare_run (SIM_CPU *cpu) -{ - if (CPU_IDESC (cpu) == NULL) - sparc32_init_idesc_table (cpu); -} - -static const CGEN_INSN * -sparc32_get_idata (SIM_CPU *cpu, int inum) -{ - return CPU_IDESC (cpu) [inum].idata; -} - -static void -sparc_v8_init_cpu (SIM_CPU *cpu) -{ - CPU_REG_FETCH (cpu) = sparc32_fetch_register; - CPU_REG_STORE (cpu) = sparc32_store_register; - CPU_PC_FETCH (cpu) = sparc32_h_pc_get; - CPU_PC_STORE (cpu) = sparc32_h_pc_set; - CPU_GET_IDATA (cpu) = sparc32_get_idata; - CPU_MAX_INSNS (cpu) = SPARC32_INSN_MAX; - CPU_INSN_NAME (cpu) = cgen_insn_name; - CPU_FULL_ENGINE_FN (cpu) = sparc32_engine_run_full; -#if WITH_FAST - CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_fast; -#else - CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_full; -#endif -} - -const MACH sparc_v8_mach = -{ - "sparc-v8", "sparc", - 32, 32, & sparc_v8_models[0], & sparc32_imp_properties, - sparc_v8_init_cpu, - sparc32_prepare_run -}; - -static void -sparclite_init_cpu (SIM_CPU *cpu) -{ - CPU_REG_FETCH (cpu) = sparc32_fetch_register; - CPU_REG_STORE (cpu) = sparc32_store_register; - CPU_PC_FETCH (cpu) = sparc32_h_pc_get; - CPU_PC_STORE (cpu) = sparc32_h_pc_set; - CPU_GET_IDATA (cpu) = sparc32_get_idata; - CPU_MAX_INSNS (cpu) = SPARC32_INSN_MAX; - CPU_INSN_NAME (cpu) = cgen_insn_name; - CPU_FULL_ENGINE_FN (cpu) = sparc32_engine_run_full; -#if WITH_FAST - CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_fast; -#else - CPU_FAST_ENGINE_FN (cpu) = sparc32_engine_run_full; -#endif -} - -const MACH sparclite_mach = -{ - "sparclite", "sparc_sparclite", - 32, 32, & sparclite_models[0], & sparc32_imp_properties, - sparclite_init_cpu, - sparc32_prepare_run -}; - diff --git a/sim/sparc/model64.c b/sim/sparc/model64.c deleted file mode 100644 index bbbbc16..0000000 --- a/sim/sparc/model64.c +++ /dev/null @@ -1,5047 +0,0 @@ -/* Simulator model support for sparc64. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc64 -#define WANT_CPU_SPARC64 - -#include "sim-main.h" - -/* The profiling data is recorded here, but is accessed via the profiling - mechanism. After all, this is information for profiling. */ - -#if WITH_PROFILE_MODEL_P - -/* Model handlers for each insn. */ - -static int -model_sparc64_def_beqz (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bgez (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bgtz (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_blez (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bltz (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bnez (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_ba (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_BPCC_BA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bne (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_be (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_ble (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bge (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bgu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bleu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bcs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bpos (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bneg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bvc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpcc_bvs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_done (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ - EXTRACT_IFMT_DONE_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_retry (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ - EXTRACT_IFMT_DONE_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_flush (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_flush_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_flushw (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FLUSHW_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSHW_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_impdep1 (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ - EXTRACT_IFMT_IMPDEP1_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_impdep2 (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ - EXTRACT_IFMT_IMPDEP1_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_membar (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MEMBAR_VARS /* f-membarmask f-membar-res12-6 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_MEMBAR_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_mova_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_mova_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_mova_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_mova_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movn_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movn_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movn_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movn_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movne_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movne_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movne_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movne_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_move_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_move_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_move_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_move_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movg_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movg_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movg_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movg_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movle_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movle_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movle_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movle_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movge_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movge_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movge_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movge_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movl_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movl_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movl_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movl_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movgu_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movgu_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movgu_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movgu_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movleu_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movleu_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movleu_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movleu_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcc_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcc_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcc_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcc_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcs_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcs_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcs_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movcs_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movpos_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movpos_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movpos_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movpos_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movneg_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movneg_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movneg_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movneg_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvc_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvc_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvc_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvc_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvs_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvs_imm_icc_icc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvs_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_movvs_imm_xcc_xcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_lduh_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_lduh_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_lduh_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldsw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_lduw_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_lduw_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_lduw_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldx_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldx_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldx_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldd_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldd_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldd_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_stb_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_stb_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_stb_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sth_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sth_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sth_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_st_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_st_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_st_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_stx_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_stx_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_stx_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_std_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_std_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_std_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_fp_ld_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_fp_ld_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_fp_ld_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sethi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ - EXTRACT_IFMT_SETHI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_add (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_add_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sub (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sub_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_addcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_addcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_subcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_subcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_addc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_addc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_subc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_subc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_addccc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_addccc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_subccc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_subccc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_and (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_and_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_andcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_andcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_or (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_or_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_orcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_orcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xor (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xor_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xorcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xorcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_andn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_andn_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_andncc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_andncc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_orn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_orn_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_orncc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_orncc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xnor (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xnor_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xnorcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_xnorcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sll (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sll_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_srl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_srl_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sra (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_sra_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_smul (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_smul_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_smul_cc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_smul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_umul (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_umul_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_umul_cc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_umul_cc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_mulscc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_save (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_save_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_restore (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_restore_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_rett (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_rett_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_unimp (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ - EXTRACT_IFMT_UNIMP_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_call (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ - IADDR i_disp30; - EXTRACT_IFMT_CALL_CODE - i_disp30 = f_disp30; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_jmpl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_jmpl_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ba (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ta (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ta_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_BA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tn (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tn_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bne (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tne (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tne_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_be (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_te (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_te_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ble (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tle (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tle_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bge (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tge (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tge_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tl (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tl_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bgu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tgu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tgu_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bleu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tleu (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tleu_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tcc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tcc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bcs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tcs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tcs_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bpos (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tpos (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tpos_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bneg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tneg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tneg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bvc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tvc (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tvc_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_bvs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tvs (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_tvs_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldstub_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldstub_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_ldstub_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_swap_reg_reg (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_swap_reg_imm (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -static int -model_sparc64_def_swap_reg_reg_asi (SIM_CPU *current_cpu, void *sem_arg) -{ - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - IADDR UNUSED pc = GET_H_PC (); - CGEN_INSN_INT insn = abuf->insn; - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += sparc64_model_sparc64_def_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -} - -/* We assume UNIT_NONE == 0 because the tables don't always terminate - entries with it. */ - -/* Model timing data for `sparc64-def'. */ - -static const INSN_TIMING sparc64_def_timing[] = { - { SPARC64_INSN_X_INVALID, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_X_AFTER, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_X_BEFORE, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_X_CHAIN, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_X_BEGIN, 0, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BEQZ, model_sparc64_def_beqz, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BGEZ, model_sparc64_def_bgez, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BGTZ, model_sparc64_def_bgtz, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BLEZ, model_sparc64_def_blez, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BLTZ, model_sparc64_def_bltz, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BNEZ, model_sparc64_def_bnez, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BA, model_sparc64_def_bpcc_ba, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BN, model_sparc64_def_bpcc_bn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BNE, model_sparc64_def_bpcc_bne, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BE, model_sparc64_def_bpcc_be, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BG, model_sparc64_def_bpcc_bg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BLE, model_sparc64_def_bpcc_ble, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BGE, model_sparc64_def_bpcc_bge, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BL, model_sparc64_def_bpcc_bl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BGU, model_sparc64_def_bpcc_bgu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BLEU, model_sparc64_def_bpcc_bleu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BCC, model_sparc64_def_bpcc_bcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BCS, model_sparc64_def_bpcc_bcs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BPOS, model_sparc64_def_bpcc_bpos, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BNEG, model_sparc64_def_bpcc_bneg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BVC, model_sparc64_def_bpcc_bvc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPCC_BVS, model_sparc64_def_bpcc_bvs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_DONE, model_sparc64_def_done, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_RETRY, model_sparc64_def_retry, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_FLUSH, model_sparc64_def_flush, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_FLUSH_IMM, model_sparc64_def_flush_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_FLUSHW, model_sparc64_def_flushw, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_IMPDEP1, model_sparc64_def_impdep1, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_IMPDEP2, model_sparc64_def_impdep2, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MEMBAR, model_sparc64_def_membar, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVA_ICC_ICC, model_sparc64_def_mova_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVA_IMM_ICC_ICC, model_sparc64_def_mova_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVA_XCC_XCC, model_sparc64_def_mova_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVA_IMM_XCC_XCC, model_sparc64_def_mova_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVN_ICC_ICC, model_sparc64_def_movn_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVN_IMM_ICC_ICC, model_sparc64_def_movn_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVN_XCC_XCC, model_sparc64_def_movn_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVN_IMM_XCC_XCC, model_sparc64_def_movn_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNE_ICC_ICC, model_sparc64_def_movne_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNE_IMM_ICC_ICC, model_sparc64_def_movne_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNE_XCC_XCC, model_sparc64_def_movne_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNE_IMM_XCC_XCC, model_sparc64_def_movne_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVE_ICC_ICC, model_sparc64_def_move_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVE_IMM_ICC_ICC, model_sparc64_def_move_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVE_XCC_XCC, model_sparc64_def_move_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVE_IMM_XCC_XCC, model_sparc64_def_move_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVG_ICC_ICC, model_sparc64_def_movg_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVG_IMM_ICC_ICC, model_sparc64_def_movg_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVG_XCC_XCC, model_sparc64_def_movg_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVG_IMM_XCC_XCC, model_sparc64_def_movg_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLE_ICC_ICC, model_sparc64_def_movle_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLE_IMM_ICC_ICC, model_sparc64_def_movle_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLE_XCC_XCC, model_sparc64_def_movle_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLE_IMM_XCC_XCC, model_sparc64_def_movle_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGE_ICC_ICC, model_sparc64_def_movge_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGE_IMM_ICC_ICC, model_sparc64_def_movge_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGE_XCC_XCC, model_sparc64_def_movge_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGE_IMM_XCC_XCC, model_sparc64_def_movge_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVL_ICC_ICC, model_sparc64_def_movl_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVL_IMM_ICC_ICC, model_sparc64_def_movl_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVL_XCC_XCC, model_sparc64_def_movl_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVL_IMM_XCC_XCC, model_sparc64_def_movl_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGU_ICC_ICC, model_sparc64_def_movgu_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGU_IMM_ICC_ICC, model_sparc64_def_movgu_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGU_XCC_XCC, model_sparc64_def_movgu_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVGU_IMM_XCC_XCC, model_sparc64_def_movgu_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLEU_ICC_ICC, model_sparc64_def_movleu_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLEU_IMM_ICC_ICC, model_sparc64_def_movleu_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLEU_XCC_XCC, model_sparc64_def_movleu_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVLEU_IMM_XCC_XCC, model_sparc64_def_movleu_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCC_ICC_ICC, model_sparc64_def_movcc_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCC_IMM_ICC_ICC, model_sparc64_def_movcc_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCC_XCC_XCC, model_sparc64_def_movcc_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCC_IMM_XCC_XCC, model_sparc64_def_movcc_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCS_ICC_ICC, model_sparc64_def_movcs_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCS_IMM_ICC_ICC, model_sparc64_def_movcs_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCS_XCC_XCC, model_sparc64_def_movcs_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVCS_IMM_XCC_XCC, model_sparc64_def_movcs_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVPOS_ICC_ICC, model_sparc64_def_movpos_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVPOS_IMM_ICC_ICC, model_sparc64_def_movpos_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVPOS_XCC_XCC, model_sparc64_def_movpos_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVPOS_IMM_XCC_XCC, model_sparc64_def_movpos_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNEG_ICC_ICC, model_sparc64_def_movneg_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNEG_IMM_ICC_ICC, model_sparc64_def_movneg_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNEG_XCC_XCC, model_sparc64_def_movneg_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVNEG_IMM_XCC_XCC, model_sparc64_def_movneg_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVC_ICC_ICC, model_sparc64_def_movvc_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVC_IMM_ICC_ICC, model_sparc64_def_movvc_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVC_XCC_XCC, model_sparc64_def_movvc_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVC_IMM_XCC_XCC, model_sparc64_def_movvc_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVS_ICC_ICC, model_sparc64_def_movvs_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVS_IMM_ICC_ICC, model_sparc64_def_movvs_imm_icc_icc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVS_XCC_XCC, model_sparc64_def_movvs_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MOVVS_IMM_XCC_XCC, model_sparc64_def_movvs_imm_xcc_xcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSB_REG_REG, model_sparc64_def_ldsb_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSB_REG_IMM, model_sparc64_def_ldsb_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSB_REG_REG_ASI, model_sparc64_def_ldsb_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUB_REG_REG, model_sparc64_def_ldub_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUB_REG_IMM, model_sparc64_def_ldub_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUB_REG_REG_ASI, model_sparc64_def_ldub_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSH_REG_REG, model_sparc64_def_ldsh_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSH_REG_IMM, model_sparc64_def_ldsh_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSH_REG_REG_ASI, model_sparc64_def_ldsh_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUH_REG_REG, model_sparc64_def_lduh_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUH_REG_IMM, model_sparc64_def_lduh_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUH_REG_REG_ASI, model_sparc64_def_lduh_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSW_REG_REG, model_sparc64_def_ldsw_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSW_REG_IMM, model_sparc64_def_ldsw_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSW_REG_REG_ASI, model_sparc64_def_ldsw_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUW_REG_REG, model_sparc64_def_lduw_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUW_REG_IMM, model_sparc64_def_lduw_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDUW_REG_REG_ASI, model_sparc64_def_lduw_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDX_REG_REG, model_sparc64_def_ldx_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDX_REG_IMM, model_sparc64_def_ldx_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDX_REG_REG_ASI, model_sparc64_def_ldx_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDD_REG_REG, model_sparc64_def_ldd_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDD_REG_IMM, model_sparc64_def_ldd_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDD_REG_REG_ASI, model_sparc64_def_ldd_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STB_REG_REG, model_sparc64_def_stb_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STB_REG_IMM, model_sparc64_def_stb_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STB_REG_REG_ASI, model_sparc64_def_stb_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STH_REG_REG, model_sparc64_def_sth_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STH_REG_IMM, model_sparc64_def_sth_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STH_REG_REG_ASI, model_sparc64_def_sth_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ST_REG_REG, model_sparc64_def_st_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ST_REG_IMM, model_sparc64_def_st_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ST_REG_REG_ASI, model_sparc64_def_st_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STX_REG_REG, model_sparc64_def_stx_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STX_REG_IMM, model_sparc64_def_stx_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STX_REG_REG_ASI, model_sparc64_def_stx_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STD_REG_REG, model_sparc64_def_std_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STD_REG_IMM, model_sparc64_def_std_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_STD_REG_REG_ASI, model_sparc64_def_std_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_FP_LD_REG_REG, model_sparc64_def_fp_ld_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_FP_LD_REG_IMM, model_sparc64_def_fp_ld_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_FP_LD_REG_REG_ASI, model_sparc64_def_fp_ld_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SETHI, model_sparc64_def_sethi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADD, model_sparc64_def_add, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADD_IMM, model_sparc64_def_add_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUB, model_sparc64_def_sub, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUB_IMM, model_sparc64_def_sub_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADDCC, model_sparc64_def_addcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADDCC_IMM, model_sparc64_def_addcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUBCC, model_sparc64_def_subcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUBCC_IMM, model_sparc64_def_subcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADDC, model_sparc64_def_addc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADDC_IMM, model_sparc64_def_addc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUBC, model_sparc64_def_subc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUBC_IMM, model_sparc64_def_subc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADDCCC, model_sparc64_def_addccc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ADDCCC_IMM, model_sparc64_def_addccc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUBCCC, model_sparc64_def_subccc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SUBCCC_IMM, model_sparc64_def_subccc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_AND, model_sparc64_def_and, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_AND_IMM, model_sparc64_def_and_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ANDCC, model_sparc64_def_andcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ANDCC_IMM, model_sparc64_def_andcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_OR, model_sparc64_def_or, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_OR_IMM, model_sparc64_def_or_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ORCC, model_sparc64_def_orcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ORCC_IMM, model_sparc64_def_orcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XOR, model_sparc64_def_xor, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XOR_IMM, model_sparc64_def_xor_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XORCC, model_sparc64_def_xorcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XORCC_IMM, model_sparc64_def_xorcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ANDN, model_sparc64_def_andn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ANDN_IMM, model_sparc64_def_andn_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ANDNCC, model_sparc64_def_andncc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ANDNCC_IMM, model_sparc64_def_andncc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ORN, model_sparc64_def_orn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ORN_IMM, model_sparc64_def_orn_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ORNCC, model_sparc64_def_orncc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_ORNCC_IMM, model_sparc64_def_orncc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XNOR, model_sparc64_def_xnor, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XNOR_IMM, model_sparc64_def_xnor_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XNORCC, model_sparc64_def_xnorcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_XNORCC_IMM, model_sparc64_def_xnorcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SLL, model_sparc64_def_sll, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SLL_IMM, model_sparc64_def_sll_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SRL, model_sparc64_def_srl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SRL_IMM, model_sparc64_def_srl_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SRA, model_sparc64_def_sra, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SRA_IMM, model_sparc64_def_sra_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SMUL, model_sparc64_def_smul, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SMUL_IMM, model_sparc64_def_smul_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SMUL_CC, model_sparc64_def_smul_cc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SMUL_CC_IMM, model_sparc64_def_smul_cc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_UMUL, model_sparc64_def_umul, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_UMUL_IMM, model_sparc64_def_umul_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_UMUL_CC, model_sparc64_def_umul_cc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_UMUL_CC_IMM, model_sparc64_def_umul_cc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_MULSCC, model_sparc64_def_mulscc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SAVE, model_sparc64_def_save, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SAVE_IMM, model_sparc64_def_save_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_RESTORE, model_sparc64_def_restore, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_RESTORE_IMM, model_sparc64_def_restore_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_RETT, model_sparc64_def_rett, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_RETT_IMM, model_sparc64_def_rett_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_UNIMP, model_sparc64_def_unimp, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_CALL, model_sparc64_def_call, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_JMPL, model_sparc64_def_jmpl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_JMPL_IMM, model_sparc64_def_jmpl_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BA, model_sparc64_def_ba, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TA, model_sparc64_def_ta, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TA_IMM, model_sparc64_def_ta_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BN, model_sparc64_def_bn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TN, model_sparc64_def_tn, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TN_IMM, model_sparc64_def_tn_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BNE, model_sparc64_def_bne, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TNE, model_sparc64_def_tne, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TNE_IMM, model_sparc64_def_tne_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BE, model_sparc64_def_be, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TE, model_sparc64_def_te, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TE_IMM, model_sparc64_def_te_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BG, model_sparc64_def_bg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TG, model_sparc64_def_tg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TG_IMM, model_sparc64_def_tg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BLE, model_sparc64_def_ble, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TLE, model_sparc64_def_tle, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TLE_IMM, model_sparc64_def_tle_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BGE, model_sparc64_def_bge, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TGE, model_sparc64_def_tge, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TGE_IMM, model_sparc64_def_tge_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BL, model_sparc64_def_bl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TL, model_sparc64_def_tl, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TL_IMM, model_sparc64_def_tl_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BGU, model_sparc64_def_bgu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TGU, model_sparc64_def_tgu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TGU_IMM, model_sparc64_def_tgu_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BLEU, model_sparc64_def_bleu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TLEU, model_sparc64_def_tleu, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TLEU_IMM, model_sparc64_def_tleu_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BCC, model_sparc64_def_bcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TCC, model_sparc64_def_tcc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TCC_IMM, model_sparc64_def_tcc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BCS, model_sparc64_def_bcs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TCS, model_sparc64_def_tcs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TCS_IMM, model_sparc64_def_tcs_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BPOS, model_sparc64_def_bpos, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TPOS, model_sparc64_def_tpos, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TPOS_IMM, model_sparc64_def_tpos_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BNEG, model_sparc64_def_bneg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TNEG, model_sparc64_def_tneg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TNEG_IMM, model_sparc64_def_tneg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BVC, model_sparc64_def_bvc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TVC, model_sparc64_def_tvc, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TVC_IMM, model_sparc64_def_tvc_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_BVS, model_sparc64_def_bvs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TVS, model_sparc64_def_tvs, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_TVS_IMM, model_sparc64_def_tvs_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSTUB_REG_REG, model_sparc64_def_ldstub_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSTUB_REG_IMM, model_sparc64_def_ldstub_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_LDSTUB_REG_REG_ASI, model_sparc64_def_ldstub_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SWAP_REG_REG, model_sparc64_def_swap_reg_reg, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SWAP_REG_IMM, model_sparc64_def_swap_reg_imm, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, - { SPARC64_INSN_SWAP_REG_REG_ASI, model_sparc64_def_swap_reg_reg_asi, { { (int) UNIT_SPARC64_DEF_U_EXEC, 1, 1 } } }, -}; - -#endif /* WITH_PROFILE_MODEL_P */ - -static void -sparc64_def_model_init (SIM_CPU *cpu) -{ - CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SPARC64_DEF_DATA)); -} - -#if WITH_PROFILE_MODEL_P -#define TIMING_DATA(td) td -#else -#define TIMING_DATA(td) 0 -#endif - -static const MODEL sparc_v9_models[] = -{ - { "sparc64-def", & sparc_v9_mach, MODEL_SPARC64_DEF, TIMING_DATA (& sparc64_def_timing[0]), sparc64_def_model_init }, - { 0 } -}; - -/* The properties of this cpu's implementation. */ - -static const MACH_IMP_PROPERTIES sparc64_imp_properties = -{ - sizeof (SIM_CPU), -#if WITH_SCACHE - sizeof (SCACHE) -#else - 0 -#endif -}; - - -static void -sparc64_prepare_run (SIM_CPU *cpu) -{ - if (CPU_IDESC (cpu) == NULL) - sparc64_init_idesc_table (cpu); -} - -static const CGEN_INSN * -sparc64_get_idata (SIM_CPU *cpu, int inum) -{ - return CPU_IDESC (cpu) [inum].idata; -} - -static void -sparc_v9_init_cpu (SIM_CPU *cpu) -{ - CPU_REG_FETCH (cpu) = sparc64_fetch_register; - CPU_REG_STORE (cpu) = sparc64_store_register; - CPU_PC_FETCH (cpu) = sparc64_h_pc_get; - CPU_PC_STORE (cpu) = sparc64_h_pc_set; - CPU_GET_IDATA (cpu) = sparc64_get_idata; - CPU_MAX_INSNS (cpu) = SPARC64_INSN_MAX; - CPU_INSN_NAME (cpu) = cgen_insn_name; - CPU_FULL_ENGINE_FN (cpu) = sparc64_engine_run_full; -#if WITH_FAST - CPU_FAST_ENGINE_FN (cpu) = sparc64_engine_run_fast; -#else - CPU_FAST_ENGINE_FN (cpu) = sparc64_engine_run_full; -#endif -} - -const MACH sparc_v9_mach = -{ - "sparc-v9", "sparc_v9", - 64, 64, & sparc_v9_models[0], & sparc64_imp_properties, - sparc_v9_init_cpu, - sparc64_prepare_run -}; - diff --git a/sim/sparc/regs32.h b/sim/sparc/regs32.h deleted file mode 100644 index 12a82d5..0000000 --- a/sim/sparc/regs32.h +++ /dev/null @@ -1,91 +0,0 @@ -/* sparc32 register definitions - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef REG32_H -#define REG32_H - -/* PSR bits */ - -#define PSR_IMPL 0xf0000000 -#define PSR_VER 0x0f000000 -#define PSR_CC 0x00f00000 -#define PSR_N 0x00800000 -#define PSR_Z 0x00400000 -#define PSR_V 0x00200000 -#define PSR_C 0x00100000 -#define PSR_EC 0x00002000 -#define PSR_EF 0x00001000 -#define PSR_PIL 0x00000f00 -#define PSR_S 0x00000080 -#define PSR_PS 0x00000040 -#define PSR_ET 0x00000020 -#define PSR_CWP 0x0000001f - -/* The PSR is a hodge-podge of various things. - ??? The final organization of this is wip. */ - -extern USI sparc32_get_h_psr_handler (SIM_CPU *); -extern void sparc32_set_h_psr_handler (SIM_CPU *, USI); -#define GET_H_PSR() sparc32_get_h_psr_handler (current_cpu) -#define SET_H_PSR(val) sparc32_set_h_psr_handler (current_cpu, (val)) - -/* The y reg is a virtual reg as it's actually one of the asr regs. - ??? To be replaced in time with get/set specs. */ -#if 0 -#define sparc32_h_y_get(cpu) (CPU_CGEN_HW (cpu)->h_asr[0]) -#define sparc32_h_y_set(cpu,val) (CPU_CGEN_HW (cpu)->h_asr[0] = (val)) -#endif -#define GET_H_Y() (CPU (h_asr) [0]) -#define SET_H_Y(newval) do { CPU (h_asr) [0] = (newval); } while (0) - -/* The Trap Base Register. */ -#define GET_H_TBR() CPU (h_tbr) -#define SET_H_TBR(newval) \ - do { \ - CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000); \ - } while (0) - -/* sparc32 register window stuff. */ - -/* Handle gets/sets of h-cwp. - This handles swapping out the current set of window registers - and swapping in the new. How the "swapping" is done depends on the - register window implementation of the day. */ -void sparc32_set_h_cwp_handler (SIM_CPU *, int); -#define GET_H_CWP() CPU (h_cwp) -#define SET_H_CWP(newval) sparc32_set_h_cwp_handler (current_cpu, (newval)) - -/* WIM accessors. */ -/* ??? Yes, mask computation assumes nwindows < 32. */ -#define GET_H_WIM() (CPU (h_wim) & ((1 << GET_NWINDOWS ()) - 1)) -#define SET_H_WIM(newval) (CPU (h_wim) = (newval)) - -/* Return non-zero if window WIN is valid in WIM. */ -#define WINDOW_VALID_P(win, wim) (((wim) & (1 << (win))) == 0) - -void sparc32_alloc_regwins (SIM_CPU *, int); -void sparc32_free_regwins (SIM_CPU *); -void sparc32_swapout_regwin (SIM_CPU *, int); -void sparc32_swapin_regwin (SIM_CPU *, int); - -void sparc32_load_regwin (SIM_CPU *, IADDR pc_, int win_); -void sparc32_flush_regwin (SIM_CPU *, IADDR pc_, int win_, int no_errors_p_); -void sparc32_flush_regwins (SIM_CPU *, IADDR pc_, int no_errors_p_); - -void sparc32_save_regwin (SIM_CPU *); -void sparc32_restore_regwin (SIM_CPU *); - -/* Integer register access macros. - Provides an interface between the cpu description and the register window - implementation of the day. To be solidified in time. */ -#define GET_H_GR(r) (current_cpu->current_regs[r]) - -/* ??? The r != 0 test may not be necessary as sufficient numbers of dni - entries can prevent this from occuring (I think). Even then though doing - this makes things more robust, and a lot of dni's would be needed. - ??? The other way to handle %g0 is to always reset it for each insn - [perhaps optimized to only do so when necessary]. */ -#define SET_H_GR(r, val) \ - ((r) != 0 ? (current_cpu->current_regs[r] = (val)) : 0) - -#endif /* REG32_H */ diff --git a/sim/sparc/regs64.h b/sim/sparc/regs64.h deleted file mode 100644 index f84d068..0000000 --- a/sim/sparc/regs64.h +++ /dev/null @@ -1,74 +0,0 @@ -/* sparc64 register definitions - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef REG64_H -#define REG64_H - -/* The PSR is a hodge-podge of various things. - ??? The final organization of this is wip. */ - -extern USI sparc32_get_h_psr_handler (SIM_CPU *); -extern void sparc32_set_h_psr_handler (SIM_CPU *, USI); -#define GET_H_PSR() sparc32_get_h_psr_handler (current_cpu) -#define SET_H_PSR(val) sparc32_set_h_psr_handler (current_cpu, (val)) - -/* The y reg is a virtual reg as it's actually one of the asr regs. - ??? To be replaced in time with get/set specs. */ -#if 0 -#define sparc32_h_y_get(cpu) (CPU_CGEN_HW (cpu)->h_asr[0]) -#define sparc32_h_y_set(cpu,val) (CPU_CGEN_HW (cpu)->h_asr[0] = (val)) -#endif -#define GET_H_Y() (CPU (h_asr) [0]) -#define SET_H_Y(newval) do { CPU (h_asr) [0] = (newval); } while (0) - -/* The Trap Base Register. */ -#define GET_H_TBR() CPU (h_tbr) -#define SET_H_TBR(newval) \ - do { \ - CPU (h_tbr) = (CPU (h_tbr) & 0xff0) | ((newval) & 0xfffff000); \ - } while (0) - -/* sparc32 register window stuff. */ - -/* Handle gets/sets of h-cwp. - This handles swapping out the current set of window registers - and swapping in the new. How the "swapping" is done depends on the - register window implementation of the day. */ -void sparc32_set_h_cwp_handler (SIM_CPU *, int); -#define GET_H_CWP() CPU (h_cwp) -#define SET_H_CWP(newval) sparc32_set_h_cwp_handler (current_cpu, (newval)) - -/* WIM accessors. */ -/* ??? Yes, mask computation assumes nwindows < 32. */ -#define GET_H_WIM() (CPU (h_wim) & ((1 << GET_NWINDOWS ()) - 1)) -#define SET_H_WIM(newval) (CPU (h_wim) = (newval)) - -/* Return non-zero if window WIN is valid in WIM. */ -#define WINDOW_VALID_P(win, wim) (((wim) & (1 << (win))) == 0) - -void sparc32_alloc_regwins (SIM_CPU *, int); -void sparc32_free_regwins (SIM_CPU *); -void sparc32_swapout_regwin (SIM_CPU *, int); -void sparc32_swapin_regwin (SIM_CPU *, int); - -void sparc32_load_regwin (SIM_CPU *, IADDR pc_, int win_); -void sparc32_flush_regwin (SIM_CPU *, IADDR pc_, int win_, int no_errors_p_); -void sparc32_flush_regwins (SIM_CPU *, IADDR pc_, int no_errors_p_); - -void sparc32_save_regwin (SIM_CPU *); -void sparc32_restore_regwin (SIM_CPU *); - -/* Integer register access macros. - Provides an interface between the cpu description and the register window - implementation of the day. To be solidified in time. */ -#define GET_H_GR(r) (current_cpu->current_regs[r]) - -/* ??? The r != 0 test may not be necessary as sufficient numbers of dni - entries can prevent this from occuring (I think). Even then though doing - this makes things more robust, and a lot of dni's would be needed. - ??? The other way to handle %g0 is to always reset it for each insn - [perhaps optimized to only do so when necessary]. */ -#define SET_H_GR(r, val) \ - ((r) != 0 ? (current_cpu->current_regs[r] = (val)) : 0) - -#endif /* REG64_H */ diff --git a/sim/sparc/sem32.c b/sim/sparc/sem32.c deleted file mode 100644 index cb8a377..0000000 --- a/sim/sparc/sem32.c +++ /dev/null @@ -1,5444 +0,0 @@ -/* Simulator instruction semantics for sparc32. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc32 -#define WANT_CPU_SPARC32 - -#include "sim-main.h" -#include "cgen-mem.h" -#include "cgen-ops.h" - -#undef GET_ATTR -#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) - -/* x-invalid: --invalid-- */ - -SEM_STATUS -SEM_FN_NAME (sparc32,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE - /* Update the recorded pc in the cpu state struct. */ - SET_H_PC (pc); -#endif - sim_engine_invalid_insn (current_cpu, pc); - sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n"); - /* NOTREACHED */ - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-after: --after-- */ - -SEM_STATUS -SEM_FN_NAME (sparc32,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC32 - sparc32_pbb_after (current_cpu, sem_arg); -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-before: --before-- */ - -SEM_STATUS -SEM_FN_NAME (sparc32,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC32 - sparc32_pbb_before (current_cpu, sem_arg); -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-cti-chain: --cti-chain-- */ - -SEM_STATUS -SEM_FN_NAME (sparc32,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC32 -#ifdef DEFINE_SWITCH - vpc = sparc32_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); - BREAK (sem); -#else - /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ - vpc = sparc32_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), - CPU_PBB_BR_NPC (current_cpu)); -#endif -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-chain: --chain-- */ - -SEM_STATUS -SEM_FN_NAME (sparc32,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC32 - vpc = sparc32_pbb_chain (current_cpu, sem_arg); -#ifdef DEFINE_SWITCH - BREAK (sem); -#endif -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-begin: --begin-- */ - -SEM_STATUS -SEM_FN_NAME (sparc32,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC32 -#ifdef DEFINE_SWITCH - /* In the switch case FAST_P is a constant, allowing several optimizations - in any called inline functions. */ - vpc = sparc32_pbb_begin (current_cpu, FAST_P); -#else - vpc = sparc32_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); -#endif -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* rd-asr: rd $rdasr,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,rd_asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_RD_ASR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_ASR_CODE - - { - SI opval = CPU (h_asr[f_rs1]); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-asr: wr $rs1,$rs2,$wrasr */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_ASR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_ASR_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - CPU (h_asr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "wrasr", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-asr-imm: wr $rs1,$simm13,$wrasr */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_asr_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_ASR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_ASR_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - CPU (h_asr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "wrasr", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* rd-psr: rd %psr,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,rd_psr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_PSR_CODE - - { - SI opval = GET_H_PSR (); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-psr: wr $rs1,$rs2,%psr */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_psr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_PSR (opval); - TRACE_RESULT (current_cpu, abuf, "psr-0", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-psr-imm: wr $rs1,$simm13,%psr */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_psr_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_PSR (opval); - TRACE_RESULT (current_cpu, abuf, "psr-0", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* rd-wim: rd %wim,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,rd_wim) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_PSR_CODE - - { - SI opval = GET_H_WIM (); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-wim: wr $rs1,$rs2,%wim */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_wim) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_WIM (opval); - TRACE_RESULT (current_cpu, abuf, "wim-0", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-wim-imm: wr $rs1,$simm13,%wim */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_wim_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_WIM (opval); - TRACE_RESULT (current_cpu, abuf, "wim-0", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* rd-tbr: rd %tbr,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,rd_tbr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_RD_PSR_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_RD_PSR_CODE - - { - SI opval = GET_H_TBR (); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-tbr: wr $rs1,$rs2,%tbr */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_tbr) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_TBR (opval); - TRACE_RESULT (current_cpu, abuf, "tbr-0", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* wr-tbr-imm: wr $rs1,$simm13,%tbr */ - -SEM_STATUS -SEM_FN_NAME (sparc32,wr_tbr_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_TBR (opval); - TRACE_RESULT (current_cpu, abuf, "tbr-0", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldstub-reg+reg: ldstub [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldstub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -sparc32_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldstub-reg+imm: ldstub [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldstub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -sparc32_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldstub-reg+reg/asi: ldstub [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldstub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - -sparc32_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* swap-reg+reg: swap [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,swap_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -sparc32_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* swap-reg+imm: swap [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,swap_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -sparc32_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* swap-reg+reg/asi: swap [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,swap_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - -sparc32_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsb-reg+reg: ldsb [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsb-reg+imm: ldsb [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsb-reg+reg/asi: ldsb [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldub-reg+reg: ldub [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldub-reg+imm: ldub [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldub-reg+reg/asi: ldub [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsh-reg+reg: ldsh [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsh-reg+imm: ldsh [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsh-reg+reg/asi: ldsh [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduh-reg+reg: lduh [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,lduh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduh-reg+imm: lduh [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,lduh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduh-reg+reg/asi: lduh [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,lduh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsw-reg+reg: ldsw [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsw-reg+imm: ldsw [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsw-reg+reg/asi: ldsw [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldsw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduw-reg+reg: lduw [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,lduw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduw-reg+imm: lduw [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,lduw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduw-reg+reg/asi: lduw [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,lduw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldd-reg+reg: ldd [$rs1+$rs2],$rdd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldd_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - -do { - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); - } - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); - SET_H_GR (((f_rd) + (1)), opval); - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldd-reg+imm: ldd [$rs1+$simm13],$rdd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldd_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - -do { - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); - } - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4))); - SET_H_GR (((f_rd) + (1)), opval); - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldd-reg+reg/asi: ldd [$rs1+$rs2]$asi,$rdd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ldd_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - -do { - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); - } - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); - SET_H_GR (((f_rd) + (1)), opval); - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stb-reg+reg: stb $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,stb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - QI opval = GET_H_GR (f_rd); - SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stb-reg+imm: stb $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,stb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - QI opval = GET_H_GR (f_rd); - SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stb-reg+reg/asi: stb $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc32,stb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - QI opval = GET_H_GR (f_rd); - SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sth-reg+reg: sth $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sth_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - HI opval = GET_H_GR (f_rd); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sth-reg+imm: sth $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sth_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - HI opval = GET_H_GR (f_rd); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sth-reg+reg/asi: sth $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sth_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - HI opval = GET_H_GR (f_rd); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* st-reg+reg: st $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,st_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* st-reg+imm: st $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,st_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* st-reg+reg/asi: st $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc32,st_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE - - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* std-reg+reg: std $rdd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,std_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - -do { - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - { - SI opval = GET_H_GR (((f_rd) + (1))); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* std-reg+imm: std $rdd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc32,std_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - -do { - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - { - SI opval = GET_H_GR (((f_rd) + (1))); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* std-reg+reg/asi: std $rdd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc32,std_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - -do { - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - { - SI opval = GET_H_GR (((f_rd) + (1))); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* fp-ld-reg+reg: ld [$rs1+$rs2],$frd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,fp_ld_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_CODE - -do { -sparc32_hw_trap (current_cpu, pc, TRAP32_FP_DIS); - { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - CPU (h_fr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* fp-ld-reg+imm: ld [$rs1+$simm13],$frd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,fp_ld_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_IMM_CODE - -do { -sparc32_hw_trap (current_cpu, pc, TRAP32_FP_DIS); - { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - CPU (h_fr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* fp-ld-reg+reg/asi: ld [$rs1+$rs2]$asi,$frd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,fp_ld_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE - -do { -sparc32_hw_trap (current_cpu, pc, TRAP32_FP_DIS); - { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - CPU (h_fr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sethi: sethi $hi22,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sethi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ - EXTRACT_IFMT_SETHI_CODE - - { - SI opval = SLLSI (f_hi22, 10); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* add: add $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* add-imm: add $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,add_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sub: sub $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sub-imm: sub $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sub_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addcc: addcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,addcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addcc-imm: addcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,addcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, 0); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subcc: subcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,subcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subcc-imm: subcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,subcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, 0); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addx: addx $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addx-imm: addx $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,addx_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subx: subx $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subx-imm: subx $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,subx_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addxcc: addxcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,addxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addxcc-imm: addxcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,addxcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subxcc: subxcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,subxcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subxcc-imm: subxcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,subxcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* and: and $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* and-imm: and $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,and_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andcc: andcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,andcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andcc-imm: andcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,andcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* or: or $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* or-imm: or $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,or_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orcc: orcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,orcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orcc-imm: orcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,orcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xor: xor $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xor-imm: xor $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xorcc: xorcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xorcc-imm: xorcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andn: andn $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,andn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andn-imm: andn $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,andn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andncc: andncc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,andncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andncc-imm: andncc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,andncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orn: orn $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,orn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orn-imm: orn $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,orn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orncc: orncc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,orncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orncc-imm: orncc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,orncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnor: xnor $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnor-imm: xnor $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xnor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnorcc: xnorcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xnorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnorcc-imm: xnorcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,xnorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sll: sll $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = SLLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sll-imm: sll $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sll_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = SLLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* srl: srl $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = SRLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* srl-imm: srl $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,srl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = SRLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sra: sra $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = SRASI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sra-imm: sra $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sra_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = SRASI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul: smul $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,smul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul-imm: smul $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,smul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul-cc: smulcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,smul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul-cc-imm: smulcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,smul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul: umul $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul-imm: umul $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,umul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul-cc: umulcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,umul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul-cc-imm: umulcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,umul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sdiv: sdiv $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sdiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTSIDI (GET_H_GR (f_rs2)))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sdiv-imm: sdiv $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sdiv_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTHIDI (f_simm13))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sdiv-cc: sdivcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sdiv_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTSIDI (GET_H_GR (f_rs2)))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (GET_H_GR (f_rd), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (GET_H_GR (f_rd), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sdiv-cc-imm: sdivcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,sdiv_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, EXTHIDI (f_simm13))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (GET_H_GR (f_rd), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (GET_H_GR (f_rd), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* udiv: udiv $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,udiv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTSIDI (GET_H_GR (f_rs2)))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* udiv-imm: udiv $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,udiv_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTHIDI (f_simm13))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* udiv-cc: udivcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,udiv_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTSIDI (GET_H_GR (f_rs2)))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (GET_H_GR (f_rd), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (GET_H_GR (f_rd), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* udiv-cc-imm: udivcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,udiv_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - DI tmp_dividend; - tmp_dividend = MAKEDI (GET_H_Y (), GET_H_GR (f_rs1)); - { - SI opval = TRUNCDISI (DIVDI (tmp_dividend, ZEXTHIDI (f_simm13))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (GET_H_GR (f_rd), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (GET_H_GR (f_rd), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* mulscc: mulscc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,mulscc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - SI tmp_rd_tmp; - SI tmp_add_tmp; - SI tmp_tmp; - tmp_tmp = SRLSI (GET_H_GR (f_rs1), 1); -if (NEBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)), 0)) { - tmp_tmp = ORSI (tmp_tmp, 0x80000000); -} -if (NESI (ANDSI (GET_H_Y (), 1), 0)) { - tmp_add_tmp = GET_H_GR (f_rs2); -} else { - tmp_add_tmp = 0; -} - tmp_rd_tmp = ADDSI (tmp_tmp, tmp_add_tmp); -do { - SI tmp_x; - tmp_x = ADDCSI (tmp_tmp, tmp_add_tmp, 0); - { - BI opval = ADDCFSI (tmp_tmp, tmp_add_tmp, 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (tmp_tmp, tmp_add_tmp, 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SRLSI (GET_H_Y (), 1); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } -if (NESI (ANDSI (GET_H_GR (f_rs1), 1), 0)) { - { - SI opval = ORSI (GET_H_Y (), 0x80000000); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } -} - { - SI opval = tmp_rd_tmp; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* save: save $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,save) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = sparc32_do_save (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* save-imm: save $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,save_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = sparc32_do_save (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* restore: restore $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,restore) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - - { - SI opval = sparc32_do_restore (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* restore-imm: restore $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,restore_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - - { - SI opval = sparc32_do_restore (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* rett: rett $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,rett) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_CODE - -do { - { - USI opval = sparc32_do_rett (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* rett-imm: rett $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,rett_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_WR_PSR_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_WR_PSR_IMM_CODE - -do { - { - USI opval = sparc32_do_rett (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* unimp: unimp $imm22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,unimp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ - EXTRACT_IFMT_UNIMP_CODE - -sparc_do_unimp (current_cpu, pc, f_imm22); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* call: call $disp30 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ - IADDR i_disp30; - EXTRACT_IFMT_CALL_CODE - i_disp30 = f_disp30; - -do { - { - SI opval = pc; - SET_H_GR (((UINT) 15), opval); - TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); - } -do { - { - USI opval = i_disp30; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* jmpl: jmpl $rs1+$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,jmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_REG_CODE - -do { - { - SI opval = pc; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - USI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* jmpl-imm: jmpl $rs1+$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc32,jmpl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSTUB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSTUB_REG_IMM_CODE - -do { - { - SI opval = pc; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - USI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ba: ba$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ba) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -do { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ta: ta $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ta) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ta-imm: ta $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ta_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bn: bn$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_BA_CODE - -do { -do { -do { } while (0); /*nop*/ -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tn: tn $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tn-imm: tn $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bne: bne$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_z))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tne: tne $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_z))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tne-imm: tne $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tne_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_z))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* be: be$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_z)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* te: te $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,te) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_z)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* te-imm: te $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,te_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_z)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bg: bg$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tg: tg $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tg-imm: tg $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ble: ble$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tle: tle $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tle) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tle-imm: tle $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tle_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bge: bge$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tge: tge $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tge-imm: tge $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tge_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bl: bl$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tl: tl $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tl-imm: tl $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bgu: bgu$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tgu: tgu $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tgu-imm: tgu $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tgu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bleu: bleu$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tleu: tleu $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tleu-imm: tleu $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tleu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bcc: bcc$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_c))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcc: tcc $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_c))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcc-imm: tcc $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_c))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bcs: bcs$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_c)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcs: tcs $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_c)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcs-imm: tcs $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tcs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_c)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpos: bpos$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_n))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tpos: tpos $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_n))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tpos-imm: tpos $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tpos_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_n))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bneg: bneg$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_n)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tneg: tneg $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_n)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tneg-imm: tneg $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tneg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_n)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bvc: bvc$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_v))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvc: tvc $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_v))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvc-imm: tvc $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tvc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_v))) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bvs: bvs$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,bvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_v)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_ANNUL-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvs: tvs $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_v)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvs-imm: tvs $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc32,tvs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_v)) { - { - USI opval = sparc32_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - diff --git a/sim/sparc/sem64.c b/sim/sparc/sem64.c deleted file mode 100644 index 17bec6f..0000000 --- a/sim/sparc/sem64.c +++ /dev/null @@ -1,7569 +0,0 @@ -/* Simulator instruction semantics for sparc64. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#define WANT_CPU sparc64 -#define WANT_CPU_SPARC64 - -#include "sim-main.h" -#include "cgen-mem.h" -#include "cgen-ops.h" - -#undef GET_ATTR -#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) - -/* x-invalid: --invalid-- */ - -SEM_STATUS -SEM_FN_NAME (sparc64,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE - /* Update the recorded pc in the cpu state struct. */ - SET_H_PC (pc); -#endif - sim_engine_invalid_insn (current_cpu, pc); - sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n"); - /* NOTREACHED */ - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-after: --after-- */ - -SEM_STATUS -SEM_FN_NAME (sparc64,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC64 - sparc64_pbb_after (current_cpu, sem_arg); -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-before: --before-- */ - -SEM_STATUS -SEM_FN_NAME (sparc64,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC64 - sparc64_pbb_before (current_cpu, sem_arg); -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-cti-chain: --cti-chain-- */ - -SEM_STATUS -SEM_FN_NAME (sparc64,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC64 -#ifdef DEFINE_SWITCH - vpc = sparc64_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); - BREAK (sem); -#else - /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ - vpc = sparc64_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), - CPU_PBB_BR_NPC (current_cpu)); -#endif -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-chain: --chain-- */ - -SEM_STATUS -SEM_FN_NAME (sparc64,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC64 - vpc = sparc64_pbb_chain (current_cpu, sem_arg); -#ifdef DEFINE_SWITCH - BREAK (sem); -#endif -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* x-begin: --begin-- */ - -SEM_STATUS -SEM_FN_NAME (sparc64,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE - - { -#if WITH_SCACHE_PBB_SPARC64 -#ifdef DEFINE_SWITCH - /* In the switch case FAST_P is a constant, allowing several optimizations - in any called inline functions. */ - vpc = sparc64_pbb_begin (current_cpu, FAST_P); -#else - vpc = sparc64_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); -#endif -#endif - } - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_PBB-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_VIRTUAL-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* beqz: beqz$a$p $rs1,$disp16 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - -do { -if (EQSI (GET_H_GR (f_rs1), 0)) { - { - USI opval = i_disp16; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bgez: bgez$a$p $rs1,$disp16 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - -do { -if (GESI (GET_H_GR (f_rs1), 0)) { - { - USI opval = i_disp16; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bgtz: bgtz$a$p $rs1,$disp16 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - -do { -if (GTSI (GET_H_GR (f_rs1), 0)) { - { - USI opval = i_disp16; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* blez: blez$a$p $rs1,$disp16 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - -do { -if (LESI (GET_H_GR (f_rs1), 0)) { - { - USI opval = i_disp16; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bltz: bltz$a$p $rs1,$disp16 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - -do { -if (LTSI (GET_H_GR (f_rs1), 0)) { - { - USI opval = i_disp16; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bnez: bnez$a$p $rs1,$disp16 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BEQZ_VARS /* f-disp16 f-rs1 f-p f-op2 f-fmt2-rcond f-bpr-res28-1 f-a f-op */ - IADDR i_disp16; - EXTRACT_IFMT_BEQZ_CODE - i_disp16 = f_disp16; - -do { -if (NESI (GET_H_GR (f_rs1), 0)) { - { - USI opval = i_disp16; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-ba: ba$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_ba) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -do { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bn: bn$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_BPCC_BA_CODE - -do { -do { -do { } while (0); /*nop*/ -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bne: bne$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_xcc_z))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-be: be$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_be) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_xcc_z)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bg: bg$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v))))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-ble: ble$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bge: bge$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bl: bl$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (XORBI (CPU (h_xcc_n), CPU (h_xcc_v))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bgu: bgu$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (ORBI (CPU (h_xcc_c), CPU (h_xcc_z)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bleu: bleu$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (ORBI (CPU (h_xcc_c), CPU (h_xcc_z))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bcc: bcc$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_xcc_c))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bcs: bcs$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_xcc_c)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bpos: bpos$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_xcc_n))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bneg: bneg$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_xcc_n)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bvc: bvc$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_xcc_v))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpcc-bvs: bvs$a$p %xcc,$disp19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpcc_bvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BPCC_BA_VARS /* f-disp19 f-p f-fmt2-cc0 f-fmt2-cc1 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BPCC_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_xcc_v)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* done: done */ - -SEM_STATUS -SEM_FN_NAME (sparc64,done) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ - EXTRACT_IFMT_DONE_CODE - -sparc64_done (current_cpu, pc); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* retry: done */ - -SEM_STATUS -SEM_FN_NAME (sparc64,retry) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_DONE_VARS /* f-res-18-19 f-op3 f-fcn f-op */ - EXTRACT_IFMT_DONE_CODE - -sparc64_retry (current_cpu, pc); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* flush: flush */ - -SEM_STATUS -SEM_FN_NAME (sparc64,flush) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_CODE - -sparc64_flush (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* flush-imm: flush */ - -SEM_STATUS -SEM_FN_NAME (sparc64,flush_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_IMM_CODE - -sparc64_flush (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* flushw: flushw */ - -SEM_STATUS -SEM_FN_NAME (sparc64,flushw) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FLUSHW_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSHW_CODE - -sparc64_flushw (current_cpu, pc); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* impdep1: impdep1 $impdep5,$impdep19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,impdep1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ - EXTRACT_IFMT_IMPDEP1_CODE - -sparc64_impdep1 (current_cpu, pc, f_impdep5, f_impdep19); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* impdep2: impdep2 $impdep5,$impdep19 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,impdep2) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_IMPDEP1_VARS /* f-impdep19 f-op3 f-impdep5 f-op */ - EXTRACT_IFMT_IMPDEP1_CODE - -sparc64_impdep2 (current_cpu, pc, f_impdep5, f_impdep19); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* membar: member $membarmask */ - -SEM_STATUS -SEM_FN_NAME (sparc64,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MEMBAR_VARS /* f-membarmask f-membar-res12-6 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_MEMBAR_CODE - -sparc64_membar (current_cpu, pc, f_membarmask); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* mova-icc-icc: mova-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,mova_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* mova-imm-icc-icc: mova-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,mova_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* mova-xcc-xcc: mova-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,mova_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* mova-imm-xcc-xcc: mova-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,mova_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movn-icc-icc: movn-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movn_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movn-imm-icc-icc: movn-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movn_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movn-xcc-xcc: movn-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movn_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movn-imm-xcc-xcc: movn-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movn_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movne-icc-icc: movne-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movne_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_z))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movne-imm-icc-icc: movne-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movne_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_z))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movne-xcc-xcc: movne-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movne_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_z))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movne-imm-xcc-xcc: movne-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movne_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_z))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* move-icc-icc: move-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,move_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_icc_z)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* move-imm-icc-icc: move-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,move_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_icc_z)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* move-xcc-xcc: move-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,move_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_xcc_z)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* move-imm-xcc-xcc: move-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,move_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_xcc_z)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movg-icc-icc: movg-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movg_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movg-imm-icc-icc: movg-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movg_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movg-xcc-xcc: movg-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movg_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v))))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movg-imm-xcc-xcc: movg-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movg_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v))))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movle-icc-icc: movle-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movle_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movle-imm-icc-icc: movle-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movle_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movle-xcc-xcc: movle-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movle_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movle-imm-xcc-xcc: movle-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movle_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (ORBI (CPU (h_xcc_z), XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movge-icc-icc: movge-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movge_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movge-imm-icc-icc: movge-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movge_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movge-xcc-xcc: movge-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movge_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movge-imm-xcc-xcc: movge-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movge_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (XORBI (CPU (h_xcc_n), CPU (h_xcc_v)))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movl-icc-icc: movl-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movl_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movl-imm-icc-icc: movl-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movl_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movl-xcc-xcc: movl-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movl_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (XORBI (CPU (h_xcc_n), CPU (h_xcc_v))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movl-imm-xcc-xcc: movl-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movl_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (XORBI (CPU (h_xcc_n), CPU (h_xcc_v))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movgu-icc-icc: movgu-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movgu_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movgu-imm-icc-icc: movgu-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movgu_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movgu-xcc-xcc: movgu-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movgu_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_xcc_c), CPU (h_xcc_z)))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movgu-imm-xcc-xcc: movgu-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movgu_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (ORBI (CPU (h_xcc_c), CPU (h_xcc_z)))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movleu-icc-icc: movleu-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movleu_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movleu-imm-icc-icc: movleu-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movleu_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movleu-xcc-xcc: movleu-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movleu_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (ORBI (CPU (h_xcc_c), CPU (h_xcc_z))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movleu-imm-xcc-xcc: movleu-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movleu_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (ORBI (CPU (h_xcc_c), CPU (h_xcc_z))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcc-icc-icc: movcc-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcc_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_c))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcc-imm-icc-icc: movcc-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcc_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_c))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcc-xcc-xcc: movcc-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcc_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_c))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcc-imm-xcc-xcc: movcc-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcc_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_c))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcs-icc-icc: movcs-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcs_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_icc_c)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcs-imm-icc-icc: movcs-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcs_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_icc_c)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcs-xcc-xcc: movcs-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcs_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_xcc_c)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movcs-imm-xcc-xcc: movcs-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movcs_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_xcc_c)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movpos-icc-icc: movpos-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movpos_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_n))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movpos-imm-icc-icc: movpos-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movpos_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_n))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movpos-xcc-xcc: movpos-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movpos_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_n))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movpos-imm-xcc-xcc: movpos-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movpos_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_n))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movneg-icc-icc: movneg-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movneg_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_icc_n)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movneg-imm-icc-icc: movneg-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movneg_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_icc_n)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movneg-xcc-xcc: movneg-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movneg_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_xcc_n)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movneg-imm-xcc-xcc: movneg-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movneg_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_xcc_n)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvc-icc-icc: movvc-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvc_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_v))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvc-imm-icc-icc: movvc-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvc_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_icc_v))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvc-xcc-xcc: movvc-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvc_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_v))) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvc-imm-xcc-xcc: movvc-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvc_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (NOTBI (CPU (h_xcc_v))) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvs-icc-icc: movvs-icc %icc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvs_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_icc_v)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvs-imm-icc-icc: movvs-imm-icc %icc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvs_imm_icc_icc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_icc_v)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvs-xcc-xcc: movvs-xcc %xcc,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvs_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_ICC_ICC_VARS /* f-rs2 f-fmt4-res10-6 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_ICC_ICC_CODE - -if (CPU (h_xcc_v)) { - { - SI opval = GET_H_GR (f_rs2); - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* movvs-imm-xcc-xcc: movvs-imm-xcc %xcc,$simm11,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,movvs_imm_xcc_xcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_VARS /* f-simm11 f-fmt4-cc1-0 f-i f-fmt4-cc2 f-op3 f-fmt2-cond f-rd f-op */ - EXTRACT_IFMT_MOVA_IMM_ICC_ICC_CODE - -if (CPU (h_xcc_v)) { - { - SI opval = f_simm11; - SET_H_GR (f_rd, opval); - written |= (1 << 2); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} - - abuf->written = written; - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsb-reg+reg: ldsb [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsb-reg+imm: ldsb [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsb-reg+reg/asi: ldsb [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldub-reg+reg: ldub [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldub-reg+imm: ldub [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldub-reg+reg/asi: ldub [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - QI opval = GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsh-reg+reg: ldsh [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsh-reg+imm: ldsh [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsh-reg+reg/asi: ldsh [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduh-reg+reg: lduh [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,lduh_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduh-reg+imm: lduh [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,lduh_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduh-reg+reg/asi: lduh [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,lduh_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - HI opval = GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsw-reg+reg: ldsw [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsw-reg+imm: ldsw [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldsw-reg+reg/asi: ldsw [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldsw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduw-reg+reg: lduw [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,lduw_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduw-reg+imm: lduw [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,lduw_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* lduw-reg+reg/asi: lduw [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,lduw_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldx-reg+reg: ldx [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldx_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - DI opval = GETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldx-reg+imm: ldx [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldx_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - DI opval = GETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldx-reg+reg/asi: ldx [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldx_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - DI opval = GETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldd-reg+reg: ldd [$rs1+$rs2],$rdd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldd_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - -do { - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); - } - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); - SET_H_GR (((f_rd) + (1)), opval); - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldd-reg+imm: ldd [$rs1+$simm13],$rdd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldd_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - -do { - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); - } - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4))); - SET_H_GR (((f_rd) + (1)), opval); - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldd-reg+reg/asi: ldd [$rs1+$rs2]$asi,$rdd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldd_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - -do { - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rdd", 'x', opval); - } - { - SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4))); - SET_H_GR (((f_rd) + (1)), opval); - TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-regno-rdd-const:-WI-1", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stb-reg+reg: stb $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,stb_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - QI opval = GET_H_GR (f_rd); - SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stb-reg+imm: stb $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,stb_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - QI opval = GET_H_GR (f_rd); - SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stb-reg+reg/asi: stb $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc64,stb_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - QI opval = GET_H_GR (f_rd); - SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sth-reg+reg: sth $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sth_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - HI opval = GET_H_GR (f_rd); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sth-reg+imm: sth $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sth_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - HI opval = GET_H_GR (f_rd); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sth-reg+reg/asi: sth $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sth_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - HI opval = GET_H_GR (f_rd); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* st-reg+reg: st $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,st_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* st-reg+imm: st $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,st_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* st-reg+reg/asi: st $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc64,st_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stx-reg+reg: stx $rd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,stx_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - DI opval = GET_H_GR (f_rd); - SETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stx-reg+imm: stx $rd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,stx_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - DI opval = GET_H_GR (f_rd); - SETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* stx-reg+reg/asi: stx $rd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc64,stx_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - - { - DI opval = GET_H_GR (f_rd); - SETMEMDI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* std-reg+reg: std $rdd,[$rs1+$rs2] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,std_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_CODE - -do { - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - { - SI opval = GET_H_GR (((f_rd) + (1))); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* std-reg+imm: std $rdd,[$rs1+$simm13] */ - -SEM_STATUS -SEM_FN_NAME (sparc64,std_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_IMM_CODE - -do { - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - { - SI opval = GET_H_GR (((f_rd) + (1))); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDHI (f_simm13, 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* std-reg+reg/asi: std $rdd,[$rs1+$rs2]$asi */ - -SEM_STATUS -SEM_FN_NAME (sparc64,std_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDD_REG_REG_ASI_CODE - -do { - { - SI opval = GET_H_GR (f_rd); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } - { - SI opval = GET_H_GR (((f_rd) + (1))); - SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), ADDSI (GET_H_GR (f_rs2), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* fp-ld-reg+reg: ld [$rs1+$rs2],$frd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,fp_ld_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FP_LD_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_CODE - -do { -sparc64_hw_trap (current_cpu, pc, TRAP32_FP_DIS); - { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - CPU (h_fr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* fp-ld-reg+imm: ld [$rs1+$simm13],$frd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,fp_ld_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FP_LD_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_IMM_CODE - -do { -sparc64_hw_trap (current_cpu, pc, TRAP32_FP_DIS); - { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), f_simm13)); - CPU (h_fr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* fp-ld-reg+reg/asi: ld [$rs1+$rs2]$asi,$frd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,fp_ld_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE - -do { -sparc64_hw_trap (current_cpu, pc, TRAP32_FP_DIS); - { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2))); - CPU (h_fr[f_rd]) = opval; - TRACE_RESULT (current_cpu, abuf, "frd", 'f', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sethi: sethi $hi22,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sethi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_SETHI_VARS /* f-hi22 f-op2 f-rd f-op */ - EXTRACT_IFMT_SETHI_CODE - - { - SI opval = SLLSI (f_hi22, 10); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* add: add $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* add-imm: add $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,add_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sub: sub $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sub-imm: sub $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sub_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addcc: addcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,addcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addcc-imm: addcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,addcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, 0); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subcc: subcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,subcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subcc-imm: subcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,subcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, 0); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addc: addc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addc-imm: addc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,addc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subc: subc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subc-imm: subc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,subc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addccc: addccc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,addccc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* addccc-imm: addccc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,addccc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - { - BI opval = ADDCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = ADDCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subccc: subccc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,subccc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBCSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2), CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* subccc-imm: subccc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,subccc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - SI tmp_x; - tmp_x = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - { - BI opval = SUBCFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = SUBOFSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SUBCSI (GET_H_GR (f_rs1), f_simm13, CPU (h_icc_c)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* and: and $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* and-imm: and $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,and_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andcc: andcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,andcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andcc-imm: andcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,andcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* or: or $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* or-imm: or $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,or_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orcc: orcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,orcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orcc-imm: orcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,orcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xor: xor $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xor-imm: xor $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xorcc: xorcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xorcc-imm: xorcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), f_simm13), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andn: andn $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,andn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andn-imm: andn $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,andn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andncc: andncc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,andncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* andncc-imm: andncc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,andncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ANDSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orn: orn $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,orn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orn-imm: orn $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,orn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orncc: orncc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,orncc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* orncc-imm: orncc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,orncc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = ORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnor: xnor $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnor-imm: xnor $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xnor_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnorcc: xnorcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xnorcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), INVSI (GET_H_GR (f_rs2))); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* xnorcc-imm: xnorcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,xnorcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { -do { - { - BI opval = EQSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); - { - SI opval = XORSI (GET_H_GR (f_rs1), INVHI (f_simm13)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sll: sll $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = SLLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sll-imm: sll $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sll_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = SLLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* srl: srl $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = SRLSI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* srl-imm: srl $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,srl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = SRLSI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sra: sra $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = SRASI (GET_H_GR (f_rs1), ANDSI (GET_H_GR (f_rs2), 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* sra-imm: sra $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,sra_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = SRASI (GET_H_GR (f_rs1), ANDHI (f_simm13, 31)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul: smul $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,smul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul-imm: smul $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,smul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul-cc: smulcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,smul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* smul-cc-imm: smulcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,smul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (EXTSIDI (GET_H_GR (f_rs1)), EXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul: umul $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul-imm: umul $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,umul_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul-cc: umulcc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,umul_cc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTSIDI (GET_H_GR (f_rs2))); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* umul-cc-imm: umulcc $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,umul_cc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { - DI tmp_res; - tmp_res = MULDI (ZEXTSIDI (GET_H_GR (f_rs1)), ZEXTHIDI (f_simm13)); - { - SI opval = TRUNCDISI (SRLDI (tmp_res, 32)); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } - { - SI opval = TRUNCDISI (tmp_res); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - BI opval = EQSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } - { - BI opval = LTSI (TRUNCDISI (tmp_res), 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = 0; - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* mulscc: mulscc $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,mulscc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { - SI tmp_rd_tmp; - SI tmp_add_tmp; - SI tmp_tmp; - tmp_tmp = SRLSI (GET_H_GR (f_rs1), 1); -if (NEBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)), 0)) { - tmp_tmp = ORSI (tmp_tmp, 0x80000000); -} -if (NESI (ANDSI (GET_H_Y (), 1), 0)) { - tmp_add_tmp = GET_H_GR (f_rs2); -} else { - tmp_add_tmp = 0; -} - tmp_rd_tmp = ADDSI (tmp_tmp, tmp_add_tmp); -do { - SI tmp_x; - tmp_x = ADDCSI (tmp_tmp, tmp_add_tmp, 0); - { - BI opval = ADDCFSI (tmp_tmp, tmp_add_tmp, 0); - CPU (h_icc_c) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-c", 'x', opval); - } - { - BI opval = ADDOFSI (tmp_tmp, tmp_add_tmp, 0); - CPU (h_icc_v) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-v", 'x', opval); - } - { - BI opval = LTSI (tmp_x, 0); - CPU (h_icc_n) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-n", 'x', opval); - } - { - BI opval = EQSI (tmp_x, 0); - CPU (h_icc_z) = opval; - TRACE_RESULT (current_cpu, abuf, "icc-z", 'x', opval); - } -} while (0); - { - SI opval = SRLSI (GET_H_Y (), 1); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } -if (NESI (ANDSI (GET_H_GR (f_rs1), 1), 0)) { - { - SI opval = ORSI (GET_H_Y (), 0x80000000); - SET_H_Y (opval); - TRACE_RESULT (current_cpu, abuf, "y-0", 'x', opval); - } -} - { - SI opval = tmp_rd_tmp; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -} while (0); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* save: save $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,save) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = sparc64_do_save (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* save-imm: save $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,save_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = sparc64_do_save (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* restore: restore $rs1,$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,restore) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - - { - SI opval = sparc64_do_restore (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* restore-imm: restore $rs1,$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,restore_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - - { - SI opval = sparc64_do_restore (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* rett: rett $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,rett) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FLUSH_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_CODE - -do { - { - USI opval = sparc64_do_rett (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* rett-imm: rett $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,rett_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_FLUSH_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_FLUSH_IMM_CODE - -do { - { - USI opval = sparc64_do_rett (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* unimp: unimp $imm22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,unimp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_UNIMP_VARS /* f-imm22 f-op2 f-rd-res f-op */ - EXTRACT_IFMT_UNIMP_CODE - -sparc_do_unimp (current_cpu, pc, f_imm22); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* call: call $disp30 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_CALL_VARS /* f-disp30 f-op */ - IADDR i_disp30; - EXTRACT_IFMT_CALL_CODE - i_disp30 = f_disp30; - -do { - { - SI opval = pc; - SET_H_GR (((UINT) 15), opval); - TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); - } -do { - { - USI opval = i_disp30; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* jmpl: jmpl $rs1+$rs2,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,jmpl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -do { - { - SI opval = pc; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - USI opval = ADDSI (GET_H_GR (f_rs1), GET_H_GR (f_rs2)); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* jmpl-imm: jmpl $rs1+$simm13,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,jmpl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -do { - { - SI opval = pc; - SET_H_GR (f_rd, opval); - TRACE_RESULT (current_cpu, abuf, "rd", 'x', opval); - } -do { - { - USI opval = ADDSI (GET_H_GR (f_rs1), f_simm13); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ba: ba$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ba) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -do { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} while (0); -} while (0); - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ta: ta $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ta) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ta-imm: ta $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ta_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } - - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_UNCOND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bn: bn$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_BA_CODE - -do { -do { -do { } while (0); /*nop*/ -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} while (0); -} while (0); - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tn: tn $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tn) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tn-imm: tn $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tn_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -do { } while (0); /*nop*/ - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bne: bne$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_z))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tne: tne $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_z))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tne-imm: tne $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tne_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_z))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* be: be$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_z)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* te: te $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,te) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_z)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* te-imm: te $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,te_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_z)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bg: bg$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tg: tg $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tg-imm: tg $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v))))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ble: ble$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tle: tle $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tle) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tle-imm: tle $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tle_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (ORBI (CPU (h_icc_z), XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bge: bge$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tge: tge $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tge) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tge-imm: tge $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tge_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (XORBI (CPU (h_icc_n), CPU (h_icc_v)))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bl: bl$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tl: tl $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tl-imm: tl $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tl_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (XORBI (CPU (h_icc_n), CPU (h_icc_v))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bgu: bgu$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tgu: tgu $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tgu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tgu-imm: tgu $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tgu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (ORBI (CPU (h_icc_c), CPU (h_icc_z)))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bleu: bleu$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tleu: tleu $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tleu-imm: tleu $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tleu_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (ORBI (CPU (h_icc_c), CPU (h_icc_z))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bcc: bcc$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_c))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcc: tcc $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tcc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_c))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcc-imm: tcc $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tcc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_c))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bcs: bcs$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_c)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcs: tcs $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tcs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_c)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tcs-imm: tcs $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tcs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_c)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bpos: bpos$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_n))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tpos: tpos $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tpos) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_n))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tpos-imm: tpos $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tpos_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_n))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bneg: bneg$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_n)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tneg: tneg $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tneg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_n)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tneg-imm: tneg $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tneg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_n)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bvc: bvc$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (NOTBI (CPU (h_icc_v))) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvc: tvc $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tvc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (NOTBI (CPU (h_icc_v))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvc-imm: tvc $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tvc_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (NOTBI (CPU (h_icc_v))) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* bvs: bvs$a $disp22 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,bvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_BA_VARS /* f-disp22 f-op2 f-fmt2-cond f-a f-op */ - IADDR i_disp22; - EXTRACT_IFMT_BA_CODE - i_disp22 = f_disp22; - -do { -if (CPU (h_icc_v)) { - { - USI opval = i_disp22; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} else { -SEM_ANNUL_INSN (current_cpu, pc, f_a); -} -} while (0); - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_DELAY_SLOT-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvs: tvs $rs1,$rs2 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_CODE - -if (CPU (h_icc_v)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), GET_H_GR (f_rs2)); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* tvs-imm: tvs $rs1,$simm13 */ - -SEM_STATUS -SEM_FN_NAME (sparc64,tvs_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_BRANCH_INIT - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_TA_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-fmt2-cond f-a f-op */ - EXTRACT_IFMT_TA_IMM_CODE - -if (CPU (h_icc_v)) { - { - USI opval = sparc64_sw_trap (current_cpu, pc, GET_H_GR (f_rs1), f_simm13); -; - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); - } -} - - abuf->written = written; - SEM_BRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_TRAP-CGEN_ATTR_BOOL_OFFSET))|(1<<(CGEN_INSN_COND_CTI-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* ldstub-reg+reg: ldstub [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldstub_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -sparc64_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldstub-reg+imm: ldstub [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldstub_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -sparc64_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* ldstub-reg+reg/asi: ldstub [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,ldstub_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - -sparc64_do_ldstub (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); - - SEM_NBRANCH_FINI (vpc, 0); - return status; -} - -/* swap-reg+reg: swap [$rs1+$rs2],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,swap_reg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_VARS /* f-rs2 f-res-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_CODE - -sparc64_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), -1); - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* swap-reg+imm: swap [$rs1+$simm13],$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,swap_reg_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_IMM_VARS /* f-simm13 f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_IMM_CODE - -sparc64_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), f_simm13, -1); - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - -/* swap-reg+reg/asi: swap [$rs1+$rs2]$asi,$rd */ - -SEM_STATUS -SEM_FN_NAME (sparc64,swap_reg_reg_asi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, CGEN_INSN_INT insn) -{ - SEM_STATUS status = 0; - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = GET_H_PC (); - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - EXTRACT_IFMT_LDSB_REG_REG_ASI_VARS /* f-rs2 f-asi f-i f-rs1 f-op3 f-rd f-op */ - EXTRACT_IFMT_LDSB_REG_REG_ASI_CODE - -sparc64_do_swap (current_cpu, pc, f_rd, GET_H_GR (f_rs1), GET_H_GR (f_rs2), f_asi); - - SEM_NBRANCH_FINI (vpc, 0|(1<<(CGEN_INSN_V9_DEPRECATED-CGEN_ATTR_BOOL_OFFSET))); - return status; -} - diff --git a/sim/sparc/sim-if.c b/sim/sparc/sim-if.c deleted file mode 100644 index 6d44075..0000000 --- a/sim/sparc/sim-if.c +++ /dev/null @@ -1,245 +0,0 @@ -/* Main simulator entry points for the SPARC. - Copyright (C) 1999 Cygnus Solutions. */ - -#include "sim-main.h" -#include <signal.h> -#ifdef HAVE_STDLIB_H -#include <stdlib.h> -#endif -#include "libiberty.h" -#include "bfd.h" -#include "sim-core.h" -#include "dev32.h" - -/* FIXME: Do we *need* to pass state to the semantic routines? */ -SIM_DESC current_state; - -static MODULE_SUSPEND_FN regwin_suspend; - -/* Cover function of sim_state_free to free the cpu buffers as well. */ - -static void -free_state (SIM_DESC sd) -{ - if (STATE_MODULES (sd) != NULL) - sim_module_uninstall (sd); - sim_cpu_free_all (sd); - sim_state_free (sd); -} - -/* Create an instance of the simulator. */ - -SIM_DESC -sim_open (kind, callback, abfd, argv) - SIM_OPEN_KIND kind; - host_callback *callback; - struct _bfd *abfd; - char **argv; -{ - char c; - int i; - SIM_DESC sd = sim_state_alloc (kind, callback); - - /* The cpu data is kept in a separately allocated chunk of memory. */ - if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) - { - free_state (sd); - return 0; - } - - if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) - { - free_state (sd); - return 0; - } - -#if 0 /* FIXME: 'twould be nice if we could do this */ - /* These options override any module options. - Obviously ambiguity should be avoided, however the caller may wish to - augment the meaning of an option. */ - if (extra_options != NULL) - sim_add_option_table (sd, extra_options); -#endif - - /* Make the default --environment=operating to be compatible with erc32. */ - STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT; - - /* getopt will print the error message so we just have to exit if this fails. - FIXME: Hmmm... in the case of gdb we need getopt to call - print_filtered. */ - if (sim_parse_args (sd, argv) != SIM_RC_OK) - { - free_state (sd); - return 0; - } - - /* check for/establish the a reference program image */ - if (sim_analyze_program (sd, - (STATE_PROG_ARGV (sd) != NULL - ? *STATE_PROG_ARGV (sd) - : NULL), - abfd) != SIM_RC_OK) - { - free_state (sd); - return 0; - } - - /* Establish any remaining configuration options. */ - if (sim_config (sd) != SIM_RC_OK) - { - free_state (sd); - return 0; - } - - if (sim_post_argv_init (sd) != SIM_RC_OK) - { - free_state (sd); - return 0; - } - - /* Initialize various cgen things not done by common framework. */ - cgen_init (sd); - - /* Open a copy of the opcode table. */ - STATE_OPCODE_TABLE (sd) = sparc_cgen_opcode_open (STATE_ARCHITECTURE (sd)->mach, - CGEN_ENDIAN_BIG); - sparc_cgen_init_dis (STATE_OPCODE_TABLE (sd)); - - /* Allocate a handler for the control registers and other devices - if no memory for that range has been allocated by the user. - All are allocated in one chunk to keep things from being - unnecessarily complicated. */ - if (sim_core_read_buffer (sd, NULL, read_map, &c, ERC32_DEVICE_ADDR, 1) == 0) - sim_core_attach (sd, NULL, - 0 /*level*/, - access_read_write, - 0 /*space ???*/, - ERC32_DEVICE_ADDR, ERC32_DEVICE_LEN /*nr_bytes*/, - 0 /*modulo*/, - &sparc_devices, - NULL /*buffer*/); - - /* Allocate core managed memory if none specified by user. */ - /* Use address 4 here in case the user wanted address 0 unmapped. */ - if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) - sim_do_commandf (sd, "memory region 0,0x%x", SPARC_DEFAULT_MEM_SIZE); - /* FIXME: magic number */ - if (sim_core_read_buffer (sd, NULL, read_map, &c, 0x2000000, 1) == 0) - sim_do_commandf (sd, "memory region 0x%x,0x%x", 0x2000000, 0x200000); - -#ifdef HAVE_SPARC32 - if (! ARCH64_P (sd)) - { - sparc32_alloc_regwins (STATE_CPU (sd, 0), NWINDOWS); - } -#endif -#ifdef HAVE_SPARC64 - if (ARCH64_P (sd)) - { - sparc64_alloc_regwins (STATE_CPU (sd, 0), NWINDOWS); - } -#endif - - sim_module_add_suspend_fn (sd, regwin_suspend); - - /* Perform a cold-reset of the cpu(s). */ - - for (i = 0; i < MAX_NR_PROCESSORS; ++i) - sparc32_cold_reset (STATE_CPU (sd, i), 0); - - /* Store in a global so things like sparc32_dump_regs can be invoked - from the gdb command line. */ - current_state = sd; - - return sd; -} - -void -sim_close (sd, quitting) - SIM_DESC sd; - int quitting; -{ -#ifdef HAVE_SPARC32 - if (! ARCH64_P (sd)) - sparc32_free_regwins (STATE_CPU (sd, 0)); -#endif -#ifdef HAVE_SPARC64 - if (ARCH64_P (sd)) - sparc64_free_regwins (STATE_CPU (sd, 0)); -#endif - sim_module_uninstall (sd); -} - -SIM_RC -sim_create_inferior (sd, abfd, argv, envp) - SIM_DESC sd; - struct _bfd *abfd; - char **argv; - char **envp; -{ - SIM_ADDR addr; - - if (abfd) - addr = bfd_get_start_address (abfd); - else - addr = 0; - -#if 0 - STATE_ARGV (sd) = sim_copy_argv (argv); - STATE_ENVP (sd) = sim_copy_argv (envp); -#endif - -#ifdef HAVE_SPARC32 - if (! ARCH64_P (sd)) - { - sparc32_cold_reset (STATE_CPU (sd, 0), 1); - sparc32_init_pc (STATE_CPU (sd, 0), addr, addr + 4); - } -#endif -#ifdef HAVE_SPARC64 - if (ARCH64_P (sd)) - { - sparc64_cold_reset (STATE_CPU (sd, 0), 1); - sparc64_init_pc (STATE_CPU (sd, 0), addr, addr + 4); - } -#endif - - return SIM_RC_OK; -} - -/* Flush the register windows when we suspend so we can walk the stack - in gdb. - ??? Extremely inefficient in case where gdb is running a program - by stepping it. - ??? Also interferes with debugging of --environment=operating. */ - -static SIM_RC -regwin_suspend (SIM_DESC sd) -{ - int c; - - for (c = 0; c < MAX_NR_PROCESSORS; ++c) - { - SIM_CPU *cpu = STATE_CPU (sd, c); - -#ifdef HAVE_SPARC32 - if (ARCH32_P (cpu)) - sparc32_flush_regwins (cpu, sim_pc_get (cpu), 1 /* no errors */); -#endif -#ifdef HAVE_SPARC64 - if (ARCH64_P (cpu)) - sparc64_flush_regwins (cpu, sim_pc_get (cpu), 1 /* no errors */); -#endif - } - - return SIM_RC_OK; -} - -void -sim_do_command (sd, cmd) - SIM_DESC sd; - char *cmd; -{ - if (sim_args_command (sd, cmd) != SIM_RC_OK) - sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); -} diff --git a/sim/sparc/sim-main.h b/sim/sparc/sim-main.h deleted file mode 100644 index caa94aa..0000000 --- a/sim/sparc/sim-main.h +++ /dev/null @@ -1,135 +0,0 @@ -/* Main header for sparc. */ - -#ifndef SIM_MAIN_H -#define SIM_MAIN_H - -#define USING_SIM_BASE_H /* FIXME: quick hack */ - -/* FIXME: For now always provide sparc32 support. */ -#define HAVE_SPARC32 -#undef HAVE_SPARC64 /* FIXME:wip */ - -/* ??? May eventually want this model (and perhaps runtime) selectable. */ -#define NWINDOWS 8 - -struct _sim_cpu; /* FIXME: should be in sim-basics.h */ -typedef struct _sim_cpu SIM_CPU; - -#include "symcat.h" -#include "sim-basics.h" -#include "cgen-types.h" -#include "cpu-opc.h" -#include "arch.h" - -/* These must be defined before sim-base.h. */ -typedef USI sim_cia; -typedef int SEMRES; - -#define CIA_GET(cpu) CPU_PC_GET (cpu) -#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val)) - -#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \ -do { \ - if (cpu) /* null if ctrl-c */ \ - sim_pc_set ((cpu), (cia)); \ -} while (0) -#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \ -do { \ - sim_pc_set ((cpu), (cia)); \ -} while (0) - -#include "sim-base.h" -#include "cgen-sim.h" - -#ifdef WANT_CPU -#include "cpu-sim.h" -#endif -#if defined (WANT_CPU_SPARC32) -#include "regs32.h" -#include "trap32.h" -#elif defined (WANT_CPU_SPARC64) -#include "regs64.h" -#include "trap64.h" -#endif - -/* The sim_cpu struct. */ - -struct _sim_cpu { - /* sim/common cpu base. */ - sim_cpu_base base; - - /* Static parts of cgen. */ - CGEN_CPU cgen_cpu; - - /* CPU specific parts go here. - Note that in files that don't need to access these pieces WANT_CPU_FOO - won't be defined and thus these parts won't appear. This is ok in the - sense that things work. It is a source of bugs though. - One has to of course be careful to not take the size of this - struct and no structure members accessed in non-cpu specific files can - go after here. Oh for a better language. */ - -#if defined (WANT_CPU_SPARC32) - - /* Machine generated registers. */ - SPARC32_CPU_DATA cpu_data; -#if 0 - /* Working variables for generating profiling information. */ - SPARC32_CPU_PROFILE cpu_profile; -#endif - /* Actual values of the window regs. */ - SI win_regs[NWINDOWS][16]; - /* g0-g7, normal and alternate - ??? handling the alternate regs still wip, need REAL_GREGS to dtrt. */ - SI global_regs[2][8]; - /* Working copies of integer regs, swapped in/out on each window change. - ??? Doing things this way means the .cpu file needn't mark these as - virtual. */ - SI current_regs[32]; - -#elif defined (WANT_CPU_SPARC64) - - /* Machine generated registers. */ - SPARC64_CPU_DATA cpu_data; -#if 0 - /* Working variables for generating profiling information. */ - SPARC64_CPU_PROFILE cpu_profile; -#endif - /* Actual values of the window regs. */ - DI win_regs[NWINDOWS][16]; - /* g0-g7, normal and alternate */ - DI global_regs[2][8]; - /* Working copies of integer regs, swapped in/out on each window change. - ??? Doing things this way means .cpu file needn't mark these as - virtual. */ - DI current_regs[32]; - -#endif -}; - -#define ARCH32_P(cpu) 1 /*FIXME*/ -#define ARCH64_P(cpu) (! ARCH32_P (cpu)) - -/* The sim_state struct. */ - -struct sim_state { - sim_cpu *cpu; -#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu) - - CGEN_STATE cgen_state; - - sim_state_base base; -}; - -/* Misc. */ - -/* Catch address exceptions. */ -extern SIM_CORE_SIGNAL_FN sparc_core_signal; -#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ -sparc_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \ - (TRANSFER), (ERROR)) - -/* Default memory size. */ -#define SPARC_DEFAULT_MEM_SIZE 0x800000 /* 8M */ - -#endif /* SIM_MAIN_H */ diff --git a/sim/sparc/sparc-opc.h b/sim/sparc/sparc-opc.h deleted file mode 100644 index 37ec9ba..0000000 --- a/sim/sparc/sparc-opc.h +++ /dev/null @@ -1,175 +0,0 @@ -/* Instruction opcode header for sparc. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright (C) 1999 Cygnus Solutions, Inc. - -This file is part of the Cygnus Simulators. - - -*/ - -#ifndef SPARC_OPC_H -#define SPARC_OPC_H - -/* -- opc.h */ - -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 256 -#undef CGEN_DIS_HASH -extern const unsigned int sparc_cgen_opcode_bits[]; -#define CGEN_DIS_HASH(buffer, insn) \ -((((insn) >> 24) & 0xc0) \ - | (((insn) & sparc_cgen_opcode_bits[((insn) >> 30) & 3]) >> 19)) - -/* -- */ -/* Enum declaration for sparc instruction types. */ -typedef enum cgen_insn_type { - SPARC_INSN_INVALID, SPARC_INSN_RD_ASR, SPARC_INSN_WR_ASR, SPARC_INSN_WR_ASR_IMM - , SPARC_INSN_RD_PSR, SPARC_INSN_WR_PSR, SPARC_INSN_WR_PSR_IMM, SPARC_INSN_RD_WIM - , SPARC_INSN_WR_WIM, SPARC_INSN_WR_WIM_IMM, SPARC_INSN_RD_TBR, SPARC_INSN_WR_TBR - , SPARC_INSN_WR_TBR_IMM, SPARC_INSN_BEQZ, SPARC_INSN_BGEZ, SPARC_INSN_BGTZ - , SPARC_INSN_BLEZ, SPARC_INSN_BLTZ, SPARC_INSN_BNEZ, SPARC_INSN_BPCC_BA - , SPARC_INSN_BPCC_BN, SPARC_INSN_BPCC_BNE, SPARC_INSN_BPCC_BE, SPARC_INSN_BPCC_BG - , SPARC_INSN_BPCC_BLE, SPARC_INSN_BPCC_BGE, SPARC_INSN_BPCC_BL, SPARC_INSN_BPCC_BGU - , SPARC_INSN_BPCC_BLEU, SPARC_INSN_BPCC_BCC, SPARC_INSN_BPCC_BCS, SPARC_INSN_BPCC_BPOS - , SPARC_INSN_BPCC_BNEG, SPARC_INSN_BPCC_BVC, SPARC_INSN_BPCC_BVS, SPARC_INSN_DONE - , SPARC_INSN_RETRY, SPARC_INSN_FLUSH, SPARC_INSN_FLUSH_IMM, SPARC_INSN_FLUSHW - , SPARC_INSN_IMPDEP1, SPARC_INSN_IMPDEP2, SPARC_INSN_MEMBAR, SPARC_INSN_MOVA_ICC_ICC - , SPARC_INSN_MOVA_IMM_ICC_ICC, SPARC_INSN_MOVA_XCC_XCC, SPARC_INSN_MOVA_IMM_XCC_XCC, SPARC_INSN_MOVN_ICC_ICC - , SPARC_INSN_MOVN_IMM_ICC_ICC, SPARC_INSN_MOVN_XCC_XCC, SPARC_INSN_MOVN_IMM_XCC_XCC, SPARC_INSN_MOVNE_ICC_ICC - , SPARC_INSN_MOVNE_IMM_ICC_ICC, SPARC_INSN_MOVNE_XCC_XCC, SPARC_INSN_MOVNE_IMM_XCC_XCC, SPARC_INSN_MOVE_ICC_ICC - , SPARC_INSN_MOVE_IMM_ICC_ICC, SPARC_INSN_MOVE_XCC_XCC, SPARC_INSN_MOVE_IMM_XCC_XCC, SPARC_INSN_MOVG_ICC_ICC - , SPARC_INSN_MOVG_IMM_ICC_ICC, SPARC_INSN_MOVG_XCC_XCC, SPARC_INSN_MOVG_IMM_XCC_XCC, SPARC_INSN_MOVLE_ICC_ICC - , SPARC_INSN_MOVLE_IMM_ICC_ICC, SPARC_INSN_MOVLE_XCC_XCC, SPARC_INSN_MOVLE_IMM_XCC_XCC, SPARC_INSN_MOVGE_ICC_ICC - , SPARC_INSN_MOVGE_IMM_ICC_ICC, SPARC_INSN_MOVGE_XCC_XCC, SPARC_INSN_MOVGE_IMM_XCC_XCC, SPARC_INSN_MOVL_ICC_ICC - , SPARC_INSN_MOVL_IMM_ICC_ICC, SPARC_INSN_MOVL_XCC_XCC, SPARC_INSN_MOVL_IMM_XCC_XCC, SPARC_INSN_MOVGU_ICC_ICC - , SPARC_INSN_MOVGU_IMM_ICC_ICC, SPARC_INSN_MOVGU_XCC_XCC, SPARC_INSN_MOVGU_IMM_XCC_XCC, SPARC_INSN_MOVLEU_ICC_ICC - , SPARC_INSN_MOVLEU_IMM_ICC_ICC, SPARC_INSN_MOVLEU_XCC_XCC, SPARC_INSN_MOVLEU_IMM_XCC_XCC, SPARC_INSN_MOVCC_ICC_ICC - , SPARC_INSN_MOVCC_IMM_ICC_ICC, SPARC_INSN_MOVCC_XCC_XCC, SPARC_INSN_MOVCC_IMM_XCC_XCC, SPARC_INSN_MOVCS_ICC_ICC - , SPARC_INSN_MOVCS_IMM_ICC_ICC, SPARC_INSN_MOVCS_XCC_XCC, SPARC_INSN_MOVCS_IMM_XCC_XCC, SPARC_INSN_MOVPOS_ICC_ICC - , SPARC_INSN_MOVPOS_IMM_ICC_ICC, SPARC_INSN_MOVPOS_XCC_XCC, SPARC_INSN_MOVPOS_IMM_XCC_XCC, SPARC_INSN_MOVNEG_ICC_ICC - , SPARC_INSN_MOVNEG_IMM_ICC_ICC, SPARC_INSN_MOVNEG_XCC_XCC, SPARC_INSN_MOVNEG_IMM_XCC_XCC, SPARC_INSN_MOVVC_ICC_ICC - , SPARC_INSN_MOVVC_IMM_ICC_ICC, SPARC_INSN_MOVVC_XCC_XCC, SPARC_INSN_MOVVC_IMM_XCC_XCC, SPARC_INSN_MOVVS_ICC_ICC - , SPARC_INSN_MOVVS_IMM_ICC_ICC, SPARC_INSN_MOVVS_XCC_XCC, SPARC_INSN_MOVVS_IMM_XCC_XCC, SPARC_INSN_LDSB_REG_REG - , SPARC_INSN_LDSB_REG_IMM, SPARC_INSN_LDSB_REG_REG_ASI, SPARC_INSN_LDUB_REG_REG, SPARC_INSN_LDUB_REG_IMM - , SPARC_INSN_LDUB_REG_REG_ASI, SPARC_INSN_LDSH_REG_REG, SPARC_INSN_LDSH_REG_IMM, SPARC_INSN_LDSH_REG_REG_ASI - , SPARC_INSN_LDUH_REG_REG, SPARC_INSN_LDUH_REG_IMM, SPARC_INSN_LDUH_REG_REG_ASI, SPARC_INSN_LDSW_REG_REG - , SPARC_INSN_LDSW_REG_IMM, SPARC_INSN_LDSW_REG_REG_ASI, SPARC_INSN_LDUW_REG_REG, SPARC_INSN_LDUW_REG_IMM - , SPARC_INSN_LDUW_REG_REG_ASI, SPARC_INSN_LDX_REG_REG, SPARC_INSN_LDX_REG_IMM, SPARC_INSN_LDX_REG_REG_ASI - , SPARC_INSN_LD_REG_REG, SPARC_INSN_LD_REG_IMM, SPARC_INSN_LD_REG_REG_ASI, SPARC_INSN_LDD_REG_REG - , SPARC_INSN_LDD_REG_IMM, SPARC_INSN_LDD_REG_REG_ASI, SPARC_INSN_STB_REG_REG, SPARC_INSN_STB_REG_IMM - , SPARC_INSN_STB_REG_REG_ASI, SPARC_INSN_STH_REG_REG, SPARC_INSN_STH_REG_IMM, SPARC_INSN_STH_REG_REG_ASI - , SPARC_INSN_ST_REG_REG, SPARC_INSN_ST_REG_IMM, SPARC_INSN_ST_REG_REG_ASI, SPARC_INSN_STX_REG_REG - , SPARC_INSN_STX_REG_IMM, SPARC_INSN_STX_REG_REG_ASI, SPARC_INSN_STD_REG_REG, SPARC_INSN_STD_REG_IMM - , SPARC_INSN_STD_REG_REG_ASI, SPARC_INSN_FP_LD_REG_REG, SPARC_INSN_FP_LD_REG_IMM, SPARC_INSN_FP_LD_REG_REG_ASI - , SPARC_INSN_SETHI, SPARC_INSN_ADD, SPARC_INSN_ADD_IMM, SPARC_INSN_SUB - , SPARC_INSN_SUB_IMM, SPARC_INSN_ADDCC, SPARC_INSN_ADDCC_IMM, SPARC_INSN_SUBCC - , SPARC_INSN_SUBCC_IMM, SPARC_INSN_ADDX, SPARC_INSN_ADDX_IMM, SPARC_INSN_SUBX - , SPARC_INSN_SUBX_IMM, SPARC_INSN_ADDXCC, SPARC_INSN_ADDXCC_IMM, SPARC_INSN_SUBXCC - , SPARC_INSN_SUBXCC_IMM, SPARC_INSN_ADDC, SPARC_INSN_ADDC_IMM, SPARC_INSN_SUBC - , SPARC_INSN_SUBC_IMM, SPARC_INSN_ADDCCC, SPARC_INSN_ADDCCC_IMM, SPARC_INSN_SUBCCC - , SPARC_INSN_SUBCCC_IMM, SPARC_INSN_AND, SPARC_INSN_AND_IMM, SPARC_INSN_ANDCC - , SPARC_INSN_ANDCC_IMM, SPARC_INSN_OR, SPARC_INSN_OR_IMM, SPARC_INSN_ORCC - , SPARC_INSN_ORCC_IMM, SPARC_INSN_XOR, SPARC_INSN_XOR_IMM, SPARC_INSN_XORCC - , SPARC_INSN_XORCC_IMM, SPARC_INSN_ANDN, SPARC_INSN_ANDN_IMM, SPARC_INSN_ANDNCC - , SPARC_INSN_ANDNCC_IMM, SPARC_INSN_ORN, SPARC_INSN_ORN_IMM, SPARC_INSN_ORNCC - , SPARC_INSN_ORNCC_IMM, SPARC_INSN_XNOR, SPARC_INSN_XNOR_IMM, SPARC_INSN_XNORCC - , SPARC_INSN_XNORCC_IMM, SPARC_INSN_SLL, SPARC_INSN_SLL_IMM, SPARC_INSN_SRL - , SPARC_INSN_SRL_IMM, SPARC_INSN_SRA, SPARC_INSN_SRA_IMM, SPARC_INSN_SMUL - , SPARC_INSN_SMUL_IMM, SPARC_INSN_SMUL_CC, SPARC_INSN_SMUL_CC_IMM, SPARC_INSN_UMUL - , SPARC_INSN_UMUL_IMM, SPARC_INSN_UMUL_CC, SPARC_INSN_UMUL_CC_IMM, SPARC_INSN_SDIV - , SPARC_INSN_SDIV_IMM, SPARC_INSN_SDIV_CC, SPARC_INSN_SDIV_CC_IMM, SPARC_INSN_UDIV - , SPARC_INSN_UDIV_IMM, SPARC_INSN_UDIV_CC, SPARC_INSN_UDIV_CC_IMM, SPARC_INSN_MULSCC - , SPARC_INSN_SAVE, SPARC_INSN_SAVE_IMM, SPARC_INSN_RESTORE, SPARC_INSN_RESTORE_IMM - , SPARC_INSN_RETT, SPARC_INSN_RETT_IMM, SPARC_INSN_UNIMP, SPARC_INSN_CALL - , SPARC_INSN_JMPL, SPARC_INSN_JMPL_IMM, SPARC_INSN_BA, SPARC_INSN_TA - , SPARC_INSN_TA_IMM, SPARC_INSN_BN, SPARC_INSN_TN, SPARC_INSN_TN_IMM - , SPARC_INSN_BNE, SPARC_INSN_TNE, SPARC_INSN_TNE_IMM, SPARC_INSN_BE - , SPARC_INSN_TE, SPARC_INSN_TE_IMM, SPARC_INSN_BG, SPARC_INSN_TG - , SPARC_INSN_TG_IMM, SPARC_INSN_BLE, SPARC_INSN_TLE, SPARC_INSN_TLE_IMM - , SPARC_INSN_BGE, SPARC_INSN_TGE, SPARC_INSN_TGE_IMM, SPARC_INSN_BL - , SPARC_INSN_TL, SPARC_INSN_TL_IMM, SPARC_INSN_BGU, SPARC_INSN_TGU - , SPARC_INSN_TGU_IMM, SPARC_INSN_BLEU, SPARC_INSN_TLEU, SPARC_INSN_TLEU_IMM - , SPARC_INSN_BCC, SPARC_INSN_TCC, SPARC_INSN_TCC_IMM, SPARC_INSN_BCS - , SPARC_INSN_TCS, SPARC_INSN_TCS_IMM, SPARC_INSN_BPOS, SPARC_INSN_TPOS - , SPARC_INSN_TPOS_IMM, SPARC_INSN_BNEG, SPARC_INSN_TNEG, SPARC_INSN_TNEG_IMM - , SPARC_INSN_BVC, SPARC_INSN_TVC, SPARC_INSN_TVC_IMM, SPARC_INSN_BVS - , SPARC_INSN_TVS, SPARC_INSN_TVS_IMM, SPARC_INSN_LDSTUB_REG_REG, SPARC_INSN_LDSTUB_REG_IMM - , SPARC_INSN_LDSTUB_REG_REG_ASI, SPARC_INSN_SWAP_REG_REG, SPARC_INSN_SWAP_REG_IMM, SPARC_INSN_SWAP_REG_REG_ASI - , SPARC_INSN_MAX -} CGEN_INSN_TYPE; - -/* Index of `invalid' insn place holder. */ -#define CGEN_INSN_INVALID SPARC_INSN_INVALID - -/* Total number of insns in table. */ -#define MAX_INSNS ((int) SPARC_INSN_MAX) - -/* This struct records data prior to insertion or after extraction. */ -struct cgen_fields -{ - int length; - long f_nil; - long f_op; - long f_op2; - long f_op3; - long f_rs1; - long f_rs2; - long f_rd; - long f_rd_res; - long f_i; - long f_simm13; - long f_imm22; - long f_hi22; - long f_a; - long f_fmt2_cond; - long f_disp22; - long f_disp30; - long f_opf; - long f_res_12_8; - long f_simm10; - long f_fmt2_cc; - long f_fmt3_cc; - long f_x; - long f_shcnt32; - long f_fcn; - long f_imm_asi; - long f_asi; - long f_res_asi; - long f_fmt4_cc; - long f_soft_trap; - long f_opf_low5; - long f_opf_low6; - long f_opf_cc; - long f_fmt2_cc1; - long f_fmt2_cc0; - long f_p; - long f_fmt2_rcond; - long f_disp19; - long f_fmt3_rcond; - long f_shcnt64; - long f_fmt4_cond; - long f_fmt4_ccx_hi; - long f_fmt4_ccx_lo; - long f_fmt4_rcond; - long f_fmt4_cc2; - long f_fmt4_cc1_0; - long f_fmt4_res10_6; - long f_disp16_hi; - long f_disp16_lo; - long f_disp16; - long f_res_18_19; - long f_bpr_res28_1; - long f_impdep5; - long f_impdep19; - long f_membar_res12_6; - long f_cmask; - long f_mmask; - long f_membarmask; - long f_simm11; -}; - - - -#endif /* SPARC_OPC_H */ diff --git a/sim/sparc/sparc-sim.h b/sim/sparc/sparc-sim.h deleted file mode 100644 index 1bbf3df..0000000 --- a/sim/sparc/sparc-sim.h +++ /dev/null @@ -1,258 +0,0 @@ -/* collection of junk waiting time to sort out - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef SPARC_SIM_H -#define SPARC_SIM_H - -/* GDB register numbers, will eventually live in more public place. */ -#define SPARC32_PC_REGNUM 68 -#define SPARC32_NPC_REGNUM 69 -#define SPARC64_PC_REGNUM ? -#define SPARC64_NPC_REGNUM ? - -/* Commonly used registers. */ -#define REG_O0 8 -#define REG_O1 9 -#define REG_O2 10 -#define REG_O3 11 -#define REG_O4 12 -#define REG_O5 13 -#define REG_SP 14 -#define REG_FP 30 - -#define CURRENT_GREGS(cpu) (& (cpu)->current_regs[0]) -#define CURRENT_OREGS(cpu) (& (cpu)->current_regs[8]) -#define CURRENT_LREGS(cpu) (& (cpu)->current_regs[16]) -#define CURRENT_IREGS(cpu) (& (cpu)->current_regs[24]) - -/* The register windows are recorded in a seemingly backwards manner. - %i0-7 live at lower addresses in memory than %o0-7 (even though they - have higher register numbers). This is because on v9 the stack grows - upwards in the sense that CWP increases during a "push" (save) operation. - On v8 CWP decreases during a "push" (save) operation. */ - -#define REAL_GREGS(cpu) \ - (& (cpu)->global_regs[0]) -#define REAL_IREGS(cpu, win) \ - (& (cpu)->win_regs[win][0]) -#define REAL_LREGS(cpu, win) \ - (& (cpu)->win_regs[win][8]) -#ifdef WANT_CPU_SPARC32 -#define REAL_OREGS(cpu, win) \ - (& (cpu)->win_regs[ROUND_WIN ((win) - 1)][0]) -#endif -#ifdef WANT_CPU_SPARC64 -#define REAL_OREGS(cpu, win) \ - (& (cpu)->win_regs[ROUND_WIN ((win) + 1)][0]) -#endif - -/* Window state. */ - -/* Various ways to handle register windows: - - don't, do all index calculations at runtime - - table of lookup tables, one entry for each window - - working copy of registers that is swapped in/out on each - register window change - - table of 32 pointers, one for each regs - - table of 4 pointers, one for each of g,o,l,i regs - - ??? -*/ - -/* FIXME: Hardcodes number of windows. */ -#define GET_NWINDOWS() NWINDOWS - -/* We take advantage of the fact that NWINDOWS is always a power of two. */ -#define ROUND_WIN(x) ((x) & (NWINDOWS - 1)) - -/* Return the next and previous windows of WIN. - Note that the next window for sparc32 is win-1 whereas the next window - for sparc64 is win+1. */ -#ifdef WANT_CPU_SPARC32 -#define NEXT_WIN(win) ROUND_WIN ((win) - 1) -#define PREV_WIN(win) ROUND_WIN ((win) + 1) -#endif -#ifdef WANT_CPU_SPARC64 -#define NEXT_WIN(win) ROUND_WIN ((win) + 1) -#define PREV_WIN(win) ROUND_WIN ((win) - 1) -#endif - -#if 0 /* FIXME: Use GET_H_FOO */ -/* These are v9 specific. */ -#define GET_CANSAVE(cpu_) (cpu_->cgen_cpu.cpu.h_cansave) -#define GET_CANRESTORE(cpu_) (cpu_->cgen_cpu.cpu.h_canrestore) -#define GET_CLEANWIN(cpu_) (cpu_->cgen_cpu.cpu.h_cleanwin) -#define GET_OTHERWIN(cpu_) (cpu_->cgen_cpu.cpu.h_otherwin) -#define GET_WSTATE(cpu_) (cpu_->cgen_cpu.cpu.h_wstate) - -/* These are v9 specific. */ -#define SET_CANSAVE(cpu_, x) (cpu_->cgen_cpu.cpu.h_cansave = (x)) -#define SET_CANRESTORE(cpu_, x) (cpu_->cgen_cpu.cpu.h_canrestore = (x)) -#define SET_CLEANWIN(cpu_, x) (cpu_->cgen_cpu.cpu.h_cleanwin = (x)) -#define SET_OTHERWIN(cpu_, x) (cpu_->cgen_cpu.cpu.h_otherwin = (x)) -#define SET_WSTATE(cpu_, x) (cpu_->cgen_cpu.cpu.h_wstate = (x)) -#endif - -#define CPU32_CGEN(cpu) (& (cpu)->sparc_cpu.sparc32.cpu_cgen) - -#ifdef WANT_CPU_SPARC32 -/*#define ARGBUF SPARC32_ARGBUF*/ -#define CPU_PROFILE_STATE(cpu) (& CPU32 (cpu)->cpu_profile) -/* Macro to access heart of cpu: the registers, etc. */ -#define CPU_CGEN(cpu) CPU32_CGEN (cpu) -#endif - -#define CPU64_CGEN(cpu) (& (cpu)->sparc_cpu.sparc64.cpu_cgen) - -#ifdef WANT_CPU_SPARC64 -/*#define ARGBUF SPARC64_ARGBUF*/ -#define CPU_PROFILE_STATE(cpu) (& CPU64 (cpu)->cpu_profile) -/* Macro to access heart of cpu: the registers, etc. */ -#define CPU_CGEN(cpu) CPU64_CGEN (cpu) -#endif - -/* ASI accesses. */ - -#define DECLARE_GETMEM(mode, size) \ -extern mode XCONCAT3 (GETMEM,mode,ASI) (SIM_CPU *, IADDR, ADDR, INT); - -DECLARE_GETMEM (QI, 1) -DECLARE_GETMEM (UQI, 1) -DECLARE_GETMEM (HI, 2) -DECLARE_GETMEM (UHI, 2) -DECLARE_GETMEM (SI, 4) -DECLARE_GETMEM (USI, 4) -DECLARE_GETMEM (DI, 8) -DECLARE_GETMEM (UDI, 8) - -#undef DECLARE_GETMEM - -#define DECLARE_SETMEM(mode, size) \ -extern void XCONCAT3 (SETMEM,mode,ASI) (SIM_CPU *, IADDR, ADDR, INT, mode); - -DECLARE_SETMEM (QI, 1) -DECLARE_SETMEM (UQI, 1) -DECLARE_SETMEM (HI, 2) -DECLARE_SETMEM (UHI, 2) -DECLARE_SETMEM (SI, 4) -DECLARE_SETMEM (USI, 4) -DECLARE_SETMEM (DI, 8) -DECLARE_SETMEM (UDI, 8) - -#undef DECLARE_SETMEM - -/* Misc. support routines. */ - -void sparc32_cold_reset (SIM_CPU *, int userland_p_); - -SI sparc32_do_restore (SIM_CPU *, IADDR pc_, SI rs1_, SI rs2_simm13_); -SI sparc32_do_save (SIM_CPU *, IADDR pc_, SI rs1_, SI rs2_simm13_); - -void sparc32_do_ldstub (SIM_CPU *, IADDR pc_, INT rd_regno_, - SI rs1_, SI rs2_simm13_, INT asi_); -void sparc32_do_swap (SIM_CPU *, IADDR pc_, INT rd_regno_, - SI rs1_, SI rs2_simm13_, INT asi_); - -void sparc32_invalid_insn (SIM_CPU *, IADDR pc_); -void sparc32_core_signal (SIM_DESC, SIM_CPU *, sim_cia pc_, - unsigned int map_, int nr_bytes_, address_word addr_, - transfer_type transfer_, sim_core_signals sig_); - -/* Profiling support. */ - -void model_mark_get_h_gr (SIM_CPU *, void *); -void model_mark_set_h_gr (SIM_CPU *, void *); -void model_mark_busy_reg (SIM_CPU *, void *); -void model_mark_unbusy_reg (SIM_CPU *, void *); - -/* Called by semantic code to annul the next insn. */ - -#define SEM_ANNUL_INSN(cpu, pc, yes) \ -do { CPU_CGEN_HW (cpu)->h_annul_p = (yes); } while (0) - -#if 0 /* old experiment */ - -/* Macros used by the semantic code generator and cgen-run.c to control - branches. */ - -/* Value returned for the next PC when a branch has occured. */ -#define PC_BRANCH_INSN 3 - -/* Value of npc when there is no delay slot. */ -#define NPC_NO_DELAY_INSN 3 - -/* CURRENT_CPU isn't used, a variable of same name must exist for SET_H_NPC */ -#define BRANCH_NEW_PC(current_cpu, var, addr) \ -do { \ - SET_H_PC (var); \ - SET_H_NPC (addr); \ - var = PC_BRANCH_INSN; \ -} while (0) - -/* Mark the next instruction as being annulled if YES is non-zero. - VAR is the local variable that contains the next PC value. - CURRENT_CPU isn't used, a variable of same name must exist for SET_H_NPC */ -#define ANNUL_NEXT_INSN(current_cpu, var, yes) \ -do { \ - if (yes) \ - { \ - SET_H_ANNUL_P (yes); \ - var = PC_BRANCH_INSN; \ - } \ -} while (0) - -/* Update the PC. - We also have to watch for delay slots and annulled insns. - current_cpu isn't used, a variable of same name must exist for SET_H_PC */ -#define UPDATE_PC(current_cpu, new_pc) \ -do { \ - if ((new_pc) == PC_BRANCH_INSN) \ - { \ - int annul_p = GET_H_ANNUL_P (); \ - PCADDR npc = GET_H_NPC (); \ - SET_H_ANNUL_P (0); \ - if (npc != NPC_NO_DELAY_INSN) \ - { \ - if (annul_p) \ - { \ - /* FIXME: Could update cycle count. */ \ - SET_H_PC (npc); \ - SET_H_NPC (NPC_NO_DELAY_INSN) ; \ - } \ - else \ - goto GotoFirstInsn; \ - } \ - else \ - { \ - /* Untaken annulled branch. */ \ - /* FIXME: Could update cycle count. */ \ - ASSERT (annul_p); \ - SET_H_PC (GET_H_PC () + 8); \ - } \ - } \ - else \ - SET_H_PC (new_pc); \ -} while (0) - -/* Return nonzero if in non-annulled delay slot. */ -#define EXECUTE_FIRST_INSN_P(current_cpu) \ -(GET_H_NPC () != NPC_NO_DELAY_INSN) - -/* Called when the first instruction is in non-annulled delay slot. */ - -#define EXECUTE_FIRST_INSN(current_cpu, sc, fast_p) \ -do { \ - PCADDR new_pc = execute (current_cpu, sc, fast_p); \ - if (new_pc == PC_BRANCH_INSN) \ - { \ - abort (); /* FIXME: dcti in delay slot not handled yet */ \ - } \ - else \ - { \ - SET_H_PC (GET_H_NPC ()); \ - SET_H_NPC (NPC_NO_DELAY_INSN); \ - } \ -} while (0) - -#endif /* old experiment */ - -#endif /* SPARC_SIM_H */ diff --git a/sim/sparc/sparc.c b/sim/sparc/sparc.c deleted file mode 100644 index a439ae2..0000000 --- a/sim/sparc/sparc.c +++ /dev/null @@ -1,62 +0,0 @@ -/* sparc simulator support code, generic to all sparcs - Copyright (C) 1999 Cygnus Solutions. */ - -#include "sim-main.h" -#include "libiberty.h" -#include "bfd.h" -#include "cgen-mem.h" -#include "cgen-ops.h" - -#ifdef HAVE_SPARC64 -#define WI DI -#else -#define WI SI -#endif - -void -sparc_do_unimp (SIM_CPU *current_cpu, IADDR pc, SI imm22) -{ - sim_engine_invalid_insn (current_cpu, pc); -} - -void -do_ldstub () -{ -} - -void -do_swap () -{ -} - -/* The semantic code invokes this for invalid (unrecognized) instructions. */ - -void -sim_engine_invalid_insn (SIM_CPU *cpu, IADDR pc) -{ -#ifdef HAVE_SPARC32 - if (ARCH32_P (cpu)) - sparc32_invalid_insn (cpu, pc); -#endif -#ifdef HAVE_SPARC64 - if (ARCH64_P (cpu)) - sparc64_invalid_insn (cpu, pc); -#endif -} - -/* Process an address exception. */ - -void -sparc_core_signal (SIM_DESC sd, SIM_CPU *cpu, sim_cia pc, - unsigned int map, int nr_bytes, address_word addr, - transfer_type transfer, sim_core_signals sig) -{ -#ifdef HAVE_SPARC32 - if (ARCH32_P (cpu)) - sparc32_core_signal (sd, cpu, pc, map, nr_bytes, addr, transfer, sig); -#endif -#ifdef HAVE_SPARC64 - if (ARCH64_P (cpu)) - sparc64_core_signal (sd, cpu, pc, map, nr_bytes, addr, transfer, sig); -#endif -} diff --git a/sim/sparc/sparc32.c b/sim/sparc/sparc32.c deleted file mode 100644 index 6e7205a..0000000 --- a/sim/sparc/sparc32.c +++ /dev/null @@ -1,568 +0,0 @@ -/* sparc32 simulator support code - Copyright (C) 1999 Cygnus Solutions. */ - -#define WANT_CPU sparc32 -#define WANT_CPU_SPARC32 - -#include "sim-main.h" -#include <signal.h> -#include "libiberty.h" -#include "bfd.h" -#include "cgen-mem.h" -#include "cgen-ops.h" -#include "targ-vals.h" - -static void sparc32_init_regwins (SIM_CPU *current_cpu); -static void sparc32_set_psr_no_cwp (SIM_CPU *current_cpu, USI newval); - -/* gdb register access support. - The contents of BUF are in target byte order. */ - -int -sparc32_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) -{ - if (rn < 32) - { - SETTSI (buf, a_sparc_h_gr_get (current_cpu, rn)); - } - else - switch (rn) - { - case SPARC32_PC_REGNUM : - SETTSI (buf, a_sparc_h_pc_get (current_cpu)); - break; - case SPARC32_NPC_REGNUM : - { - USI npc = a_sparc_h_npc_get (current_cpu); -#if 0 /* experiment */ - if (npc == NPC_NO_DELAY_INSN) - npc = a_sparc_h_pc_get (current_cpu) + 4; -#endif - SETTSI (buf, npc); - break; - } - default : - return 0; - } - - return -1; /*FIXME*/ -} - -/* gdb register access support. - The contents of BUF are in target byte order. */ - -int -sparc32_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) -{ - if (rn < 32) - { - a_sparc_h_gr_set (current_cpu, rn, GETTSI (buf)); - } - else - switch (rn) - { - case SPARC32_PC_REGNUM : - a_sparc_h_pc_set (current_cpu, GETTSI (buf)); - break; - case SPARC32_NPC_REGNUM : - a_sparc_h_npc_set (current_cpu, GETTSI (buf)); - break; - default : - return 0; - } - - return -1; /*FIXME*/ -} - -/* Initialization. */ - -/* Initialize the program counter. */ - -void -sparc32_init_pc (SIM_CPU *current_cpu, SI pc, SI npc) -{ - SET_H_PC (pc); - SET_H_NPC (npc); -} - -/* Do a pseudo power-on-reset. - USERLAND_P is non-zero to prepare to run a user-land program. */ - -void -sparc32_cold_reset (SIM_CPU *current_cpu, int userland_p) -{ - int i; - - /* Initialize the PSR. - This has to be careful as we just want to initialize the CWP, we don't - want to "set" it (which causes the old window to be "swapped out"). - ??? impl,ver need better values. */ - sparc32_set_psr_no_cwp (current_cpu, 0 | PSR_S); - - /* Initialize cwp directly (bypassing SET_H_CWP and SET_H_PSR) as we just - want to initialize things, not "swap" the current window out. */ - CPU (h_cwp) = 0; - sparc32_init_regwins (current_cpu); - - /* Mark the last window as invalid. This creates a distinguishable end - of register window stack. The last window is window 1 (mask 2) as - saves decrement CWP. - Note that the last and first window overlap. */ - SET_H_WIM (2); - - sparc32_init_pc (current_cpu, 0, 4); - - for (i = 0; i < 32; ++i) - SET_H_GR (i, 0); - SET_H_FSR (0); -} - -/* Do a warm reset (the reset trap). */ - -void -sparc32_warm_reset (SIM_CPU *current_cpu) -{ - /* FIXME: unimplemented yet */ -} - -/* Special purpose registers. */ - -/* The PSR. - ??? add ability to specify a register as a set of bitfields. */ - -USI -sparc32_get_h_psr_handler (SIM_CPU *current_cpu) -{ - USI val; - val = CPU (h_psr) & (PSR_IMPL | PSR_VER); - val |= GET_H_ICC_C () ? PSR_C : 0; - val |= GET_H_ICC_N () ? PSR_N : 0; - val |= GET_H_ICC_V () ? PSR_V : 0; - val |= GET_H_ICC_Z () ? PSR_Z : 0; - val |= GET_H_EC () ? PSR_EC : 0; - val |= GET_H_EF () ? PSR_EF : 0; - val |= (GET_H_PIL () & 0xf) << 8; - val |= GET_H_S () ? PSR_S : 0; - val |= GET_H_PS () ? PSR_PS : 0; - val |= GET_H_ET () ? PSR_ET : 0; - val |= GET_H_CWP (); - return val; -} - -/* Utility to set everything in the PSR except CWP - (needed by sparc32_cold_reset). */ - -static void -sparc32_set_psr_no_cwp (SIM_CPU *current_cpu, USI newval) -{ - SET_H_ICC_C ((newval & PSR_C) != 0); - SET_H_ICC_N ((newval & PSR_N) != 0); - SET_H_ICC_V ((newval & PSR_V) != 0); - SET_H_ICC_Z ((newval & PSR_Z) != 0); - SET_H_EC ((newval & PSR_EC) != 0); - SET_H_EF ((newval & PSR_EF) != 0); - SET_H_PIL ((newval & PSR_PIL) >> 8); - SET_H_S ((newval & PSR_S) != 0); - SET_H_PS ((newval & PSR_PS) != 0); - SET_H_ET ((newval & PSR_ET) != 0); -} - -void -sparc32_set_h_psr_handler (SIM_CPU *current_cpu, USI newval) -{ - sparc32_set_psr_no_cwp (current_cpu, newval); - SET_H_CWP (newval & PSR_CWP); -} - -/* Register window support. */ - -/* Allocate space for the register window mechanism. - This version doesn't have much to do. - Other register window implementations have more to do. */ - -void -sparc32_alloc_regwins (SIM_CPU *current_cpu, int nwindows) -{ - /* nothing to do in current window implementation */ -} - -void -sparc32_free_regwins (SIM_CPU *current_cpu) -{ - /* nothing to do in current window implementation */ -} - -/* Initialize the register window control registers for running - user programs. */ - -static void -sparc32_init_regwins (SIM_CPU *current_cpu) -{ - /* nothing to do in current window implementation */ -} - -/* Assign a new value to CWP. - SET_H_CWP calls this. - - This swaps out the current values of the o/l/i regs from `current_regs' - and swaps in the new values. */ - -void -sparc32_set_h_cwp_handler (SIM_CPU *current_cpu, int new) -{ - int old = GET_H_CWP (); - - if (new < 0 || new >= GET_NWINDOWS ()) - abort (); - - CPU (h_cwp) = new; - - /* Swap current values out of `current_regs'. - Do this even if old == new. */ - sparc32_swapout_regwin (current_cpu, old); - - /* Swap new values into `current_regs'. */ - if (old != new) - sparc32_swapin_regwin (current_cpu, new); -} - -/* Swap out the values in `current_regs'. */ - -void -sparc32_swapout_regwin (SIM_CPU *current_cpu, int win) -{ - int n = 8 * sizeof (SI); - - memcpy (REAL_OREGS (current_cpu, win), CURRENT_OREGS (current_cpu), n); - memcpy (REAL_LREGS (current_cpu, win), CURRENT_LREGS (current_cpu), n); - memcpy (REAL_IREGS (current_cpu, win), CURRENT_IREGS (current_cpu), n); -} - -/* Swap int values for `current_regs'. */ - -void -sparc32_swapin_regwin (SIM_CPU *current_cpu, int win) -{ - int n = 8 * sizeof (SI); - - memcpy (CURRENT_OREGS (current_cpu), REAL_OREGS (current_cpu, win), n); - memcpy (CURRENT_LREGS (current_cpu), REAL_LREGS (current_cpu, win), n); - memcpy (CURRENT_IREGS (current_cpu), REAL_IREGS (current_cpu, win), n); -} - -/* Create a new window. We assume there is room. */ - -void -sparc32_save_regwin (SIM_CPU *current_cpu) -{ - SET_H_CWP (NEXT_WIN (GET_H_CWP ())); -} - -/* Pop a window. We assume no traps possible. */ - -void -sparc32_restore_regwin (SIM_CPU *current_cpu) -{ - SET_H_CWP (PREV_WIN (GET_H_CWP ())); -} - -/* Flush the register windows to memory. - This is necessary, for example, when we want to walk the stack in gdb. - NO_ERRORS_P is non-zero if memory faults must be avoided. This is important - when returning to gdb, the processor has "stopped". - - ??? At present we only handle user programs. */ - -void -sparc32_flush_regwins (SIM_CPU *current_cpu, IADDR pc, int no_errors_p) -{ - int i, win; - int count = GET_NWINDOWS (); - - /* Flush the current window cache. */ - sparc32_swapout_regwin (current_cpu, GET_H_CWP ()); - - /* For each register window that is marked valid, flush it to memory. - We start at the current window and move upwards on the stack. */ - - for (i = 0, win = GET_H_CWP (); i < count; i++, win = PREV_WIN (win)) - { - /* Don't go passed an invalid window. */ - if (! WINDOW_VALID_P (win, GET_H_WIM ())) - break; - sparc32_flush_regwin (current_cpu, pc, win, no_errors_p); - } -} - -void -sparc32_flush_regwin (SIM_CPU *cpu, IADDR pc, int win, int no_errors_p) -{ - int i; - USI sp,fp,addr; - /* Fetch pointers to lregs and iregs for this frame. */ - SI *lregs = REAL_LREGS (cpu, win); - SI *iregs = REAL_IREGS (cpu, win); - SIM_DESC sd = CPU_STATE (cpu); - - /* Fetch values of sp,fp for this frame. */ - sp = REAL_OREGS (cpu, win) [6]; - fp = REAL_IREGS (cpu, win) [6]; - - /* Exit early if there'd be a memory fault but we can't have any errors. */ - if (no_errors_p) - { - /* Check if sp and fp indicate a proper save may not have been done. */ - if (fp <= sp - || fp - sp < 8 * sizeof (SI)) - return; - /* sp misaligned? */ - if (sp & 3) - return; - } - - /* Use sim_core_write_aligned_N here to handle endian conversions. */ - - addr = sp; - for (i = 0; i < 8; i++) - { - if (no_errors_p) - { - char reg[4]; - SETTSI (reg, lregs[i]); - if (sim_core_write_buffer (sd, cpu, write_map, reg, addr, 4) == 0) - return; - } - else - sim_core_write_aligned_4 (cpu, pc, write_map, addr, lregs[i]); - addr += 4; - } - for (i = 0; i < 8; i++) - { - if (no_errors_p) - { - char reg[4]; - SETTSI (reg, lregs[i]); - if (sim_core_write_buffer (sd, cpu, write_map, reg, addr, 4) == 0) - return; - } - else - sim_core_write_aligned_4 (cpu, pc, write_map, addr, iregs[i]); - addr += 4; - } -} - -void -sparc32_load_regwin (SIM_CPU *cpu, IADDR pc, int win) -{ - int i; - /* Fetch value of sp for this frame. */ - SI addr = REAL_OREGS (cpu, win) [6]; - /* Fetch pointers to lregs and iregs for this frame. */ - SI *lregs = REAL_LREGS (cpu, win); - SI *iregs = REAL_IREGS (cpu, win); - - /* Use sim_core_read_aligned_N here to handle endian conversions. */ - - for (i = 0; i < 8; i++) - { - lregs[i] = sim_core_read_aligned_4 (cpu, pc, read_map, addr); - addr += 4; - } - for (i = 0; i < 8; i++) - { - iregs[i] = sim_core_read_aligned_4 (cpu, pc, read_map, addr); - addr += 4; - } -} - -/* Save/restore insns. */ - -/* Handle the save instruction. */ - -SI -sparc32_do_save (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SI rd; - int oldwin,newwin,wim; - - /* FIXME: Watch for stack overflow if user prog. */ - - /* Determine new window number and see if its bit is set in the - Window Invalid Mask. */ - oldwin = GET_H_CWP (); - newwin = NEXT_WIN (oldwin); - wim = GET_H_WIM (); - if (! WINDOW_VALID_P (newwin, wim)) - sparc32_window_overflow (current_cpu, pc); - - /* `rs1' and `rs2_simm13' are based on the old window (which we want) */ - rd = rs1 + rs2_simm13; - - /* Switch to the new window. */ - sparc32_save_regwin (current_cpu); - - if (TRACE_INSN_P (current_cpu)) /* FIXME */ - { - trace_result (current_cpu, "sp", 'x', GET_H_GR (H_GR__SP)); - trace_result (current_cpu, "fp", 'x', GET_H_GR (H_GR__FP)); - trace_result (current_cpu, "cwp", 'x', GET_H_CWP ()); - } - - /* `rd' will be saved in the new window by the semantic code. */ - return rd; -} - -/* Handle the restore instruction. */ - -SI -sparc32_do_restore (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SI rd; - int oldwin,newwin,wim; - - /* Determine new window number and see if its bit is set in the - Window Invalid Mask. */ - oldwin = GET_H_CWP (); - newwin = PREV_WIN (oldwin); - wim = GET_H_WIM (); - if (! WINDOW_VALID_P (newwin, wim)) - sparc32_window_underflow (current_cpu, pc); - - /* `rs1' and `rs2_simm13' are based on the old window (which we want) */ - rd = rs1 + rs2_simm13; - - /* Switch to the previous window. */ - sparc32_restore_regwin (current_cpu); - - if (TRACE_INSN_P (current_cpu)) /* FIXME */ - { - trace_result (current_cpu, "sp", 'x', GET_H_GR (H_GR__SP)); - trace_result (current_cpu, "fp", 'x', GET_H_GR (H_GR__FP)); - trace_result (current_cpu, "cwp", 'x', GET_H_CWP ()); - } - - /* `rd' will be saved in the new window by the semantic code. */ - return rd; -} - -/* ASI accesses. */ - -#define DEFINE_GETMEM(mode, size) \ -mode \ -XCONCAT3 (GETMEM,mode,ASI) (SIM_CPU *cpu, IADDR pc, ADDR a, INT asi) \ -{ \ - return 0; /* FIXME:wip */ \ -} - -DEFINE_GETMEM (QI, 1) -DEFINE_GETMEM (UQI, 1) -DEFINE_GETMEM (HI, 2) -DEFINE_GETMEM (UHI, 2) -DEFINE_GETMEM (SI, 4) -DEFINE_GETMEM (USI, 4) -DEFINE_GETMEM (DI, 8) -DEFINE_GETMEM (UDI, 8) - -#undef DEFINE_GETMEM - -#define DEFINE_SETMEM(mode, size) \ -void \ -XCONCAT3 (SETMEM,mode,ASI) (SIM_CPU *cpu, IADDR pc, ADDR a, INT asi, mode newval) \ -{ \ - return; /* FIXME:wip */ \ -} - -DEFINE_SETMEM (QI, 1) -DEFINE_SETMEM (UQI, 1) -DEFINE_SETMEM (HI, 2) -DEFINE_SETMEM (UHI, 2) -DEFINE_SETMEM (SI, 4) -DEFINE_SETMEM (USI, 4) -DEFINE_SETMEM (DI, 8) -DEFINE_SETMEM (UDI, 8) - -#undef SETMEM - -/* ldstub, swap insns */ - -void -sparc32_do_ldstub (SIM_CPU *current_cpu, IADDR pc, INT rd_regno, - SI rs1, SI rs2_simm13, INT asi) -{ -} - -void -sparc32_do_swap (SIM_CPU *current_cpu, IADDR pc, INT rd_regno, - SI rs1, SI rs2_simm13, INT asi) -{ -} - -/* Profiling support. */ - -#if WITH_PROFILE_MODEL_P - -/* FIXME: Some of these should be inline or macros. Later. */ - -void -sparc32_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf) -{ -} - -void -sparc32_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf) -{ -} - -void -sparc32_model_mark_busy_reg (SIM_CPU *cpu, ARGBUF *abuf) -{ -} - -void -sparc32_model_mark_unbusy_reg (SIM_CPU *cpu, ARGBUF *abuf) -{ -} - -/* Initialize cycle counting for an insn. - FIRST_P is non-zero if this is the first insn in a set of parallel - insns. */ - -void -sparc32_model_insn_before (SIM_CPU *cpu, int first_p) -{ -} - -/* Record the cycles computed for an insn. - LAST_P is non-zero if this is the last insn in a set of parallel insns, - and we update the total cycle count. - CYCLES is the cycle count of the insn. */ - -void -sparc32_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) -{ -} - -int -sparc32_model_sparc32_def_u_exec (SIM_CPU *cpu, const IDESC *idesc, - int unit_num, int referenced) -{ - return idesc->timing->units[unit_num].done; -} - -#endif /* WITH_PROFILE_MODEL_P */ - -/* Debugging stuff. */ - -/* Pretty print the control and integer registers. - This can be invoked with the user-defined "dump" command in gdb. */ - -void -sim_debug_dump () -{ - extern SIM_DESC current_state; - host_callback *cb = STATE_CALLBACK (current_state); - SIM_CPU *current_cpu = STATE_CPU (current_state, 0); - - sim_cb_printf (cb, "CPU Registers\n"); - sim_cb_printf (cb, "CWP:%4d WIM:%4d\n", GET_H_CWP (), GET_H_WIM ()); -} diff --git a/sim/sparc/sparc64.c b/sim/sparc/sparc64.c deleted file mode 100644 index fb62187..0000000 --- a/sim/sparc/sparc64.c +++ /dev/null @@ -1,264 +0,0 @@ -/* sparc64 simulator support code - Copyright (C) 1999 Cygnus Solutions. */ - -#define WANT_CPU_SPARC64 - -#include "sim-main.h" -#include <signal.h> -#include "libiberty.h" -#include "bfd.h" -#include "cgen-mem.h" -#include "cgen-ops.h" -#include "targ-vals.h" -#include "trap64.h" - -/* Initialize the program counter. */ - -void -sparc64_init_pc (SIM_CPU *current_cpu, DI pc, DI npc) -{ - SET_H_PC (pc); - SET_H_NPC (npc); -} - -#if WITH_PROFILE_MODEL_P - -void -sparc64_model_mark_get_h_gr (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) -{ - if ((CPU_PROFILE_STATE (cpu)->h_gr & abuf->h_gr_get) != 0) - { - PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2; - if (TRACE_INSN_P (cpu)) - cgen_trace_printf (cpu, " ; Load stall of 2 cycles."); - } -} - -void -sparc64_model_mark_set_h_gr (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) -{ -} - -void -sparc64_model_mark_busy_reg (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) -{ - CPU_PROFILE_STATE (cpu)->h_gr = abuf->h_gr_set; -} - -void -sparc64_model_mark_unbusy_reg (SIM_CPU *cpu, SPARC64_ARGBUF *abuf) -{ - CPU_PROFILE_STATE (cpu)->h_gr = 0; -} - -#endif /* WITH_PROFILE_MODEL_P */ - -UDI -sparc64_h_gr_get (SIM_CPU *current_cpu, unsigned int regno) -{ - return GET_INT_REG (cpu, regno); -} - -void -sparc64_h_gr_set (SIM_CPU *current_cpu, unsigned int regno, UDI new_val) -{ - SET_INT_REG (cpu, regno, new_val); -} - -DI * -sparc64_h_gr_regno_get_addr (SIM_CPU *current_cpu, int regno) -{ -} - -DI -sparc64_h_gr_regno_get (SIM_CPU *current_cpu, int regno) -{ -} - -void -sparc64_h_gr_regno_set (SIM_CPU *current_cpu, int regno, DI new_val) -{ -} - -DI -sparc64_do_save (SIM_CPU *current_cpu, DI rs1, DI rs2_simm13) -{ - DI rd; - - /* If this is a user program, watch for stack overflow ... */ - -#if 0 - if (STATE_user_prog && GET_AREG (GET_REG (REG_SP)) < mem_end) - { - if (user_prog) - fprintf (stderr, "sim: stack space exhausted!\n"); - sim_signal (SIM_SIGACCESS); - return 0; - } -#endif - - if (GET_CANSAVE (current_cpu) == 0) - { - return trap (TRAP_SPILL); - } - if (GET_CLEANWIN (current_cpu) - GET_CANRESTORE (current_cpu) == 0) - { - return trap (TRAP_CLEAN_WINDOW); - } - - /* The calculation is done using the old window's values - [those passed in to us]. */ - - rd = ADDDI (rs1, rs2_simm13); - - /* Switch to a new window. */ - - save_window (); - - return rd; -} - -DI -sparc64_do_restore (SIM_CPU *current_cpu, DI rs1, DI rs2_simm13) -{ - DI rd; - - return rd; - -} - -/* Initialize the register window mechanism. */ - -void -sparc64_alloc_register_windows (SIM_CPU *cpu, int nwindows) -{ - int ag,i,r,w; - DI *(*v)[32]; - - cpu->greg_lookup_table = (DI *(*)[2][32]) xmalloc (nwindows * 2 * 32 * sizeof (void *)); - cpu->globals = (DI (*)[][8]) zalloc (2 * 8 * sizeof (DI)); - cpu->win_regs = (DI (*)[][16]) zalloc (nwindows * 16 * sizeof (DI)); - - v = &cpu->greg_lookup_table[0][0]; - for (w = 0; w < nwindows; w++) - { - for (ag = 0; ag < 2; ag++, v++) - { - /* Initialize pointers to the global registers ... */ - for (r = 0; r < 8; r++) - (*v)[r] = &cpu->globals[ag][r]; - - /* Initialize pointers to the output registers ... */ - for (r = 0; r < 8; r++) - (*v)[r + 8] = &cpu->win_regs[(w == nwindows - 1 ? 0 : ((w + 1) * 16)) + r]; - - /* Initialize pointers to the local registers ... */ - for (r = 0; r < 8; r++) - (*v)[r + 16] = &cpu->win_regs[(w * 16) + 8 + r]; - - /* Initialize pointers to the input registers ... */ - for (r = 0; r < 8; r++) - (*v)[r + 24] = &cpu->win_regs[(w * 16) + r]; - } - } -} - -void -sparc64_free_register_windows (SIM_CPU *cpu) -{ - free (cpu->win_regs); - cpu->win_regs = NULL; - free (cpu->globals); - cpu->globals = NULL; - free (cpu->greg_lookup_table); - cpu->greg_lookup_table = NULL; -} - -/* Assign a new value to CWP. - - The register windows are recorded in a seemingly backwards manner. - %i0-7 live at lower addresses in memory than %o0-7 (even though they - have higher register numbers). This is because the stack grows upwards - in the sense that CWP increases during a "push" operation. - - FIXME: True for v9, but also for v8? */ - -void -sparc64_set_cwp (SIM_CPU *current_cpu, int x) -{ - if (x < 0 || x >= GET_NWINDOWS (cpu)) - abort (); - - /* We can't use SET_CWP here because it uses us. */ - - cpu->cgen_cpu.cpu.h_cwp = x; - - cpu->current_greg_lookup_table = &cpu->greg_lookup_table[x][GET_AG (cpu)][0]; -} - -/* Create a new window. We assume there is room. - - WARNING: The following must always be true: - - CANSAVE + CANRESTORE + OTHERWIN == NWINDOWS - 2 - - We only watch for this during saves. */ - -void -sparc64_save_window (SIM_CPU *current_cpu) -{ - if (GET_CANSAVE (cpu) + GET_CANRESTORE (cpu) + GET_OTHERWIN (cpu) != GET_NWINDOWS (cpu) - 2) - abort (); - - SET_CWP (cpu, ROUND_WIN (GET_CWP (cpu) + 1)); - SET_CANSAVE (cpu, ROUND_WIN (GET_CANSAVE (cpu) - 1)); - SET_CANRESTORE (cpu, ROUND_WIN (GET_CANRESTORE (cpu) + 1)); -} - -/* Pop a window. We assume no traps possible. */ - -void -sparc64_restore_window (SIM_CPU *current_cpu) -{ - SET_CWP (cpu, ROUND_WIN (GET_CWP (cpu) - 1)); - SET_CANSAVE (cpu, ROUND_WIN (GET_CANSAVE (cpu) + 1)); - SET_CANRESTORE (cpu, ROUND_WIN (GET_CANRESTORE (cpu) - 1)); -} - -/* Flush the register windows to memory. - This is necessary, for example, when we want to walk the stack in gdb. - - We use restore_window() and save_window() to traverse the register windows. - This is the cleanest and simplest thing to do. */ - -void -sparc64_flush_windows (SIM_CPU *cpu) -{ - int i,count = GET_CANRESTORE (cpu) + 1; - - /* Save the register windows, changing the current one as we go ... */ - - for (i = 0; i < count; i++) - { - AI sp = GET_INT_REG (cpu, REG_SP) /*+ stack_bias*/; - flush_one_window (cpu, sp, CURRENT_LREGS (cpu), CURRENT_IREGS (cpu)); - if (i + 1 != count) /* don't restore window if there isn't one */ - restore_window (cpu); - } - - /* Restore the window state ... */ - - for (i = 1; i < count; i++) - save_window (cpu); -} - -void -sparc64_flush_one_window (SIM_CPU *current_cpu, AI addr, DI *lregs, DI *iregs) -{ - sim_core_write_buffer (CPU_STATE (cpu), cpu, - sim_core_write_map, - lregs, addr, 8 * sizeof (DI)); - sim_core_write_buffer (CPU_STATE (cpu), cpu, - sim_core_write_map, - iregs, addr + 8 * sizeof (DI), 8 * sizeof (DI)); -} diff --git a/sim/sparc/tconfig.in b/sim/sparc/tconfig.in deleted file mode 100644 index 1ca14135..0000000 --- a/sim/sparc/tconfig.in +++ /dev/null @@ -1,49 +0,0 @@ -/* Sparc target configuration file. -*- C -*- */ - -#ifndef SPARC_TCONFIG_H -#define SPARC_TCONFIG_H - -/* See sim-hload.c. We properly handle LMA. */ - -#define SIM_HANDLES_LMA 1 - -/* Device support. FIXME: revisit. */ -#define WITH_DEVICES 1 - -/* This is a global setting. Different cpu families can't mix-n-match -scache - and -pbb. However some cpu families may use -simple while others use - one of -scache/-pbb. */ -#define WITH_SCACHE_PBB 0 - -/* Simple-engine branch support. - Delay slots, annuling, and traps are (currently) handled by using the - simple engine and doing all the work in SEM_{,N}BRANCH_FINI. */ - -#define TARGET_SEM_BRANCH_FINI(vpc, bool_attrs, taken_p) \ -do { \ - IADDR npc = GET_H_NPC (); \ - if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_DELAY_SLOT) && taken_p) \ - { \ - SET_H_PC (npc); \ - SET_H_NPC (vpc); \ - } \ - else if (CGEN_BOOL_ATTR ((bool_attrs), CGEN_INSN_TRAP) && taken_p) \ - { \ - SET_H_PC (vpc); \ - SET_H_NPC ((vpc) + 4); \ - } \ - else \ - { \ - SET_H_PC (npc); \ - SET_H_NPC (npc + 4); \ - } \ -} while (0) - -#define TARGET_SEM_NBRANCH_FINI(vpc, bool_attrs) \ -do { \ - IADDR npc = GET_H_NPC (); \ - SET_H_PC (npc); \ - SET_H_NPC (npc + 4); \ -} while (0) - -#endif /* SPARC_TCONFIG_H */ diff --git a/sim/sparc/trap32.c b/sim/sparc/trap32.c deleted file mode 100644 index fb60281..0000000 --- a/sim/sparc/trap32.c +++ /dev/null @@ -1,308 +0,0 @@ -/* sparc32 trap support - Copyright (C) 1999 Cygnus Solutions. */ - -#define WANT_CPU sparc32 -#define WANT_CPU_SPARC32 - -#include "sim-main.h" -#include "targ-vals.h" - -/* Indicate a window overflow has occured. */ - -void -sparc32_window_overflow (SIM_CPU *cpu, IADDR pc) -{ - SIM_DESC sd = CPU_STATE (cpu); - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - sparc32_hw_trap (cpu, pc, TRAP32_WINDOW_OVERFLOW); - else - sparc32_hw_trap (cpu, pc, TRAP32_SIM_SPILL); -} - -/* Indicate a window underflow has occured. */ - -void -sparc32_window_underflow (SIM_CPU *cpu, IADDR pc) -{ - SIM_DESC sd = CPU_STATE (cpu); - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - sparc32_hw_trap (cpu, pc, TRAP32_WINDOW_UNDERFLOW); - else - sparc32_hw_trap (cpu, pc, TRAP32_SIM_FILL); -} - -void -sparc32_invalid_insn (SIM_CPU * cpu, IADDR pc) -{ - sparc32_hw_trap (cpu, pc, TRAP32_ILLEGAL_INSN); -} - -void -sparc32_core_signal (SIM_DESC sd, SIM_CPU *cpu, sim_cia pc, - unsigned int map, int nr_bytes, address_word addr, - transfer_type transfer, sim_core_signals sig) -{ - sparc32_hw_trap (cpu, pc, - map == exec_map - ? TRAP32_INSTRUCTION_ACCESS - : TRAP32_DATA_ACCESS); -} - -/* Handle hardware generated traps when --environment=operating. */ - -static void -sparc32_hw_trap_oper (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - IADDR new_pc = (GET_H_TBR () & 0xfffff000) | (trap << 4); - USI psr = GET_H_PSR (); - - psr &= ~PSR_ET; - psr = (psr & ~PSR_PS) | (psr & PSR_S ? PSR_PS : 0); - psr |= PSR_S; - psr = (psr & ~PSR_CWP) | NEXT_WIN (psr & PSR_CWP); - SET_H_PSR (psr); - SET_H_GR (H_GR__L1, GET_H_PC ()); - SET_H_GR (H_GR__L2, GET_H_NPC ()); - - SET_H_ANNUL_P (0); - - /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either - (??? doesn't *have* to be this way though). - Therefore we can't use SET_H_TBR here. */ - CPU (h_tbr) = new_pc; - SET_H_PC (new_pc); - SET_H_NPC (new_pc + 4); - - sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, new_pc); -} - -/* Handle hardware generated traps when --environment=user. */ - -static void -sparc32_hw_trap_user (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - - switch (trap) - { - case TRAP32_SIM_SPILL : - /* The CWP-1 window is invalid. */ - { - int win = NEXT_WIN (GET_H_CWP ()); - int next_win = NEXT_WIN (win); - int nwindows = GET_NWINDOWS (); - unsigned int mask = (1 << nwindows) - 1; - unsigned int wim = GET_H_WIM (); - - /* There's no need to flush `current_regs' here, `next_win' can't - refer to it. */ - sparc32_flush_regwin (current_cpu, pc, next_win, 0 /* error ok (?) */); - /* Rotate WIM right one. */ - wim = ((wim & mask) >> 1) | (wim << (nwindows - 1)); - SET_H_WIM (wim & mask); - return; - } - - case TRAP32_SIM_FILL : - /* The CWP+1 window is invalid. */ - { - int win = PREV_WIN (GET_H_CWP ()); - int nwindows = GET_NWINDOWS (); - unsigned int mask = (1 << nwindows) - 1; - unsigned int wim = GET_H_WIM (); - - /* Load caller's caller's window. - There's no need to flush `current_regs' as `win' can't - refer to it. */ - sparc32_load_regwin (current_cpu, pc, win); - /* Rotate WIM left one. */ - wim = (wim << 1) | ((wim & mask) >> (nwindows - 1)); - SET_H_WIM (wim & mask); - return; - } - } - - sim_io_eprintf (sd, "Received trap %d\n", trap); - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGABRT); -} - -/* Handle hardware generated traps. */ - -void -sparc32_hw_trap (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - sparc32_hw_trap_oper (current_cpu, pc, trap); - else - sparc32_hw_trap_user (current_cpu, pc, trap); -} - -/* Handle the trap insn when --environment=operating. */ - -static IADDR -sparc32_sw_trap_oper (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - int trap = 128 + ((rs1 + rs2_simm13) & 127); - IADDR new_pc; - - /* ??? Quick hack to have breakpoints work with gdb+"target sim" until - other things are working. */ - if (trap == TRAP32_BREAKPOINT) - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); - - if (! GET_H_ET ()) - { - /* Enter error mode. - ??? wip, need to remain compatible with erc32 for now. */ - int i0 = GET_H_GR (H_GR__I0); - int i1 = GET_H_GR (H_GR__I1); - - if (i1 == LIBGLOSS_EXIT_MAGIC) - sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, i0); - else - { - sim_io_eprintf (sd, "Unexpected program termination, pc=0x%x\n", - (int) pc); - sim_engine_halt (sd, current_cpu, NULL, pc, - sim_signalled, SIM_SIGABRT); - } - } - - SET_H_ET (0); - SET_H_PSR ((GET_H_PSR () & ~(PSR_CWP | PSR_PS)) - | PSR_S - | (GET_H_S () ? PSR_PS : 0) - | (NEXT_WIN (GET_H_CWP ()))); - SET_H_GR (H_GR__L1, GET_H_PC ()); - SET_H_GR (H_GR__L2, GET_H_NPC ()); - /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either - (??? doesn't *have* to be this way though). - Therefore we can't use SET_H_TBR here. */ - CPU (h_tbr) = new_pc = ((GET_H_TBR () & 0xfffff000) - | (trap << 4)); - return new_pc; -} - -/* Subroutine of sparc32_do_trap to read target memory. */ - -static int -syscall_read_mem (host_callback *cb, CB_SYSCALL *sc, - unsigned long taddr, char *buf, int bytes) -{ - SIM_DESC sd = (SIM_DESC) sc->p1; - SIM_CPU *cpu = (SIM_CPU *) sc->p2; - - return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); -} - -/* Subroutine of sparc32_do_trap to write target memory. */ - -static int -syscall_write_mem (host_callback *cb, CB_SYSCALL *sc, - unsigned long taddr, const char *buf, int bytes) -{ - SIM_DESC sd = (SIM_DESC) sc->p1; - SIM_CPU *cpu = (SIM_CPU *) sc->p2; - - return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); -} - -/* Handle the trap insn when --environment=user. */ - -static IADDR -sparc32_sw_trap_user (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - int trap = 128 + ((rs1 + rs2_simm13) & 127); - IADDR new_pc = pc + 4; - - switch (trap) - { - case TRAP32_SYSCALL : - /* FIXME: Later make trap number runtime selectable. */ - { - CB_SYSCALL s; - - CB_SYSCALL_INIT (&s); - s.func = a_sparc_h_gr_get (current_cpu, 8); - s.arg1 = a_sparc_h_gr_get (current_cpu, 9); - s.arg2 = a_sparc_h_gr_get (current_cpu, 10); - s.arg3 = a_sparc_h_gr_get (current_cpu, 11); - if (s.func == TARGET_SYS_exit) - { - /* Tell sim_resume program called exit(). */ - sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); - } - s.p1 = (PTR) sd; - s.p2 = (PTR) current_cpu; - s.read_mem = syscall_read_mem; - s.write_mem = syscall_write_mem; - cb_syscall (STATE_CALLBACK (CPU_STATE (current_cpu)), &s); - a_sparc_h_gr_set (current_cpu, 10, s.errcode); - a_sparc_h_gr_set (current_cpu, 8, s.result); - a_sparc_h_gr_set (current_cpu, 9, s.result2); - break; - } - - case TRAP32_BREAKPOINT : - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); - - case TRAP32_DIVIDE_0 : - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE); - - case TRAP32_FLUSH_REGWIN : - sparc32_flush_regwins (current_cpu, pc, 0 /* error ok */); - break; - - default : - sim_io_eprintf (sd, "Unsupported trap %d\n", trap); - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL); - } - - return new_pc; -} - -/* Called from the semantic code to handle the trap instruction. */ - -IADDR -sparc32_sw_trap (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - IADDR new_pc; - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - new_pc = sparc32_sw_trap_oper (current_cpu, pc, rs1, rs2_simm13); - else - new_pc = sparc32_sw_trap_user (current_cpu, pc, rs1, rs2_simm13); - return new_pc; -} - -/* Handle the rett insn. */ - -IADDR -sparc32_do_rett (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - int psr = GET_H_PSR (); - - /* FIXME: check for trap conditions. */ - - SET_H_PSR ((psr & ~(PSR_S + PSR_CWP)) - | ((psr & PSR_PS) ? PSR_S : 0) - | PSR_ET - | PREV_WIN (psr & PSR_CWP)); - - if (TRACE_INSN_P (current_cpu)) /* FIXME */ - { - trace_result (current_cpu, "sp", 'x', GET_H_GR (H_GR__SP)); - trace_result (current_cpu, "fp", 'x', GET_H_GR (H_GR__FP)); - trace_result (current_cpu, "cwp", 'x', GET_H_CWP ()); - } - - return rs1 + rs2_simm13; -} diff --git a/sim/sparc/trap32.h b/sim/sparc/trap32.h deleted file mode 100644 index 7f8fd2a..0000000 --- a/sim/sparc/trap32.h +++ /dev/null @@ -1,74 +0,0 @@ -/* sparc32 trap definitions - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef TRAP32_H -#define TRAP32_H - -typedef enum -{ - /* reset */ - TRAP32_RESET = 0, - /* unable to fetch instruction (e.g. bad mapping) */ - TRAP32_INSTRUCTION_ACCESS = 1, - /* illegal instruction */ - TRAP32_ILLEGAL_INSN = 2, - /* priviledged instruction */ - TRAP32_PRIVILEDGED_INSN = 3, - /* FPU disabled */ - TRAP32_FP_DIS = 4, - /* window overflow */ - TRAP32_WINDOW_OVERFLOW = 5, - /* window underflow */ - TRAP32_WINDOW_UNDERFLOW = 6, - /* unaligned memory access */ - TRAP32_UNALIGNED_ADDR = 7, - /* unable to access memory (e.g. bad mapping) */ - TRAP32_DATA_ACCESS = 9, - /* tag overflow (taddcctv, tsubcctv insns) */ - TRAP32_TAG_OVERFLOW = 10, - /* coprocessor disabled */ - TRAP32_CP_DIS = 36, - - /* Implementation dependent trap types. */ - /* ??? Borrowed concept from v9. */ - TRAP32_IMPDEP_EXCEPTION_0 = 96, /* n = 0..31 */ - - /* IMPDEP codes used by the simulator in ENVIRONMENT_USER. */ - TRAP32_SIM_UNIMPLEMENTED_OPCODE = 124, - TRAP32_SIM_RESERVED_INSN = 125, - TRAP32_SIM_SPILL = 126, - TRAP32_SIM_FILL = 127, - - /* Traps via the "trap" instruction. */ - TRAP32_INSTRUCTION = 128, /* n = 0..127 */ - /* System calls. */ - TRAP32_SYSCALL = 128, - /* The breakpoint trap, "ta 1". */ - TRAP32_BREAKPOINT = 129, - /* Divide by zero. */ - TRAP32_DIVIDE_0 = 130, - /* Flush register windows, "ta 3". */ - TRAP32_FLUSH_REGWIN = 131, - - TRAP32_MAX = 0xff -} TRAP32_TYPE; - -/* FIXME: revisit */ -#define MAX_NUM_TRAPS 256 - -#define TRAP32_TABLE_SIZE (32 * MAX_NUM_TRAPS) /* in bytes */ - -/* The libgloss _exit routine sets a magic number in %o1 to tell us its - him. This lets us defer tinkering with libgloss and remain compatible - with erc32. */ -#define LIBGLOSS_EXIT_MAGIC 0xdeadd00d - -void sparc32_window_overflow (SIM_CPU *, IADDR pc_); -void sparc32_window_underflow (SIM_CPU *, IADDR pc_); - -void sparc32_hw_trap (SIM_CPU *, IADDR pc_, TRAP32_TYPE trap_); -IADDR sparc32_sw_trap (SIM_CPU *, IADDR pc_, SI rs1_, SI rs2_simm13_); - -IADDR sparc32_do_rett (SIM_CPU *, IADDR pc_, SI rs1_, SI rs2_simm13_); - -#endif /* TRAP32_H */ diff --git a/sim/sparc/trap64.c b/sim/sparc/trap64.c deleted file mode 100644 index f87160f..0000000 --- a/sim/sparc/trap64.c +++ /dev/null @@ -1,308 +0,0 @@ -/* sparc64 trap support - Copyright (C) 1999 Cygnus Solutions. */ - -#define WANT_CPU sparc64 -#define WANT_CPU_SPARC64 - -#include "sim-main.h" -#include "targ-vals.h" - -/* Indicate a window overflow has occured. */ - -void -sparc64_window_overflow (SIM_CPU *cpu, IADDR pc) -{ - SIM_DESC sd = CPU_STATE (cpu); - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - sparc64_hw_trap (cpu, pc, TRAP32_WINDOW_OVERFLOW); - else - sparc64_hw_trap (cpu, pc, TRAP32_SIM_SPILL); -} - -/* Indicate a window underflow has occured. */ - -void -sparc64_window_underflow (SIM_CPU *cpu, IADDR pc) -{ - SIM_DESC sd = CPU_STATE (cpu); - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - sparc64_hw_trap (cpu, pc, TRAP32_WINDOW_UNDERFLOW); - else - sparc64_hw_trap (cpu, pc, TRAP32_SIM_FILL); -} - -void -sparc64_invalid_insn (SIM_CPU * cpu, IADDR pc) -{ - sparc64_hw_trap (cpu, pc, TRAP32_ILLEGAL_INSN); -} - -void -sparc64_core_signal (SIM_DESC sd, SIM_CPU *cpu, sim_cia pc, - unsigned int map, int nr_bytes, address_word addr, - transfer_type transfer, sim_core_signals sig) -{ - sparc64_hw_trap (cpu, pc, - map == exec_map - ? TRAP32_INSTRUCTION_ACCESS - : TRAP32_DATA_ACCESS); -} - -/* Handle hardware generated traps when --environment=operating. */ - -static void -sparc64_hw_trap_oper (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - IADDR new_pc = (GET_H_TBR () & 0xfffff000) | (trap << 4); - USI psr = GET_H_PSR (); - - psr &= ~PSR_ET; - psr = (psr & ~PSR_PS) | (psr & PSR_S ? PSR_PS : 0); - psr |= PSR_S; - psr = (psr & ~PSR_CWP) | NEXT_WIN (psr & PSR_CWP); - SET_H_PSR (psr); - SET_H_GR (H_GR__L1, GET_H_PC ()); - SET_H_GR (H_GR__L2, GET_H_NPC ()); - - SET_H_ANNUL_P (0); - - /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either - (??? doesn't *have* to be this way though). - Therefore we can't use SET_H_TBR here. */ - CPU (h_tbr) = new_pc; - SET_H_PC (new_pc); - SET_H_NPC (new_pc + 4); - - sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, new_pc); -} - -/* Handle hardware generated traps when --environment=user. */ - -static void -sparc64_hw_trap_user (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - - switch (trap) - { - case TRAP32_SIM_SPILL : - /* The CWP-1 window is invalid. */ - { - int win = NEXT_WIN (GET_H_CWP ()); - int next_win = NEXT_WIN (win); - int nwindows = GET_NWINDOWS (); - unsigned int mask = (1 << nwindows) - 1; - unsigned int wim = GET_H_WIM (); - - /* There's no need to flush `current_regs' here, `next_win' can't - refer to it. */ - sparc64_flush_regwin (current_cpu, pc, next_win, 0 /* error ok (?) */); - /* Rotate WIM right one. */ - wim = ((wim & mask) >> 1) | (wim << (nwindows - 1)); - SET_H_WIM (wim & mask); - return; - } - - case TRAP32_SIM_FILL : - /* The CWP+1 window is invalid. */ - { - int win = PREV_WIN (GET_H_CWP ()); - int nwindows = GET_NWINDOWS (); - unsigned int mask = (1 << nwindows) - 1; - unsigned int wim = GET_H_WIM (); - - /* Load caller's caller's window. - There's no need to flush `current_regs' as `win' can't - refer to it. */ - sparc64_load_regwin (current_cpu, pc, win); - /* Rotate WIM left one. */ - wim = (wim << 1) | ((wim & mask) >> (nwindows - 1)); - SET_H_WIM (wim & mask); - return; - } - } - - sim_io_eprintf (sd, "Received trap %d\n", trap); - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGABRT); -} - -/* Handle hardware generated traps. */ - -void -sparc64_hw_trap (SIM_CPU *current_cpu, IADDR pc, TRAP32_TYPE trap) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - sparc64_hw_trap_oper (current_cpu, pc, trap); - else - sparc64_hw_trap_user (current_cpu, pc, trap); -} - -/* Handle the trap insn when --environment=operating. */ - -static IADDR -sparc64_sw_trap_oper (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - int trap = 128 + ((rs1 + rs2_simm13) & 127); - IADDR new_pc; - - /* ??? Quick hack to have breakpoints work with gdb+"target sim" until - other things are working. */ - if (trap == TRAP32_BREAKPOINT) - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); - - if (! GET_H_ET ()) - { - /* Enter error mode. - ??? wip, need to remain compatible with erc32 for now. */ - int i0 = GET_H_GR (H_GR__I0); - int i1 = GET_H_GR (H_GR__I1); - - if (i1 == LIBGLOSS_EXIT_MAGIC) - sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, i0); - else - { - sim_io_eprintf (sd, "Unexpected program termination, pc=0x%x\n", - (int) pc); - sim_engine_halt (sd, current_cpu, NULL, pc, - sim_signalled, SIM_SIGABRT); - } - } - - SET_H_ET (0); - SET_H_PSR ((GET_H_PSR () & ~(PSR_CWP | PSR_PS)) - | PSR_S - | (GET_H_S () ? PSR_PS : 0) - | (NEXT_WIN (GET_H_CWP ()))); - SET_H_GR (H_GR__L1, GET_H_PC ()); - SET_H_GR (H_GR__L2, GET_H_NPC ()); - /* The wrtbr insn doesn't affect the tt part so SET_H_TBR doesn't either - (??? doesn't *have* to be this way though). - Therefore we can't use SET_H_TBR here. */ - CPU (h_tbr) = new_pc = ((GET_H_TBR () & 0xfffff000) - | (trap << 4)); - return new_pc; -} - -/* Subroutine of sparc64_do_trap to read target memory. */ - -static int -syscall_read_mem (host_callback *cb, CB_SYSCALL *sc, - unsigned long taddr, char *buf, int bytes) -{ - SIM_DESC sd = (SIM_DESC) sc->p1; - SIM_CPU *cpu = (SIM_CPU *) sc->p2; - - return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); -} - -/* Subroutine of sparc64_do_trap to write target memory. */ - -static int -syscall_write_mem (host_callback *cb, CB_SYSCALL *sc, - unsigned long taddr, const char *buf, int bytes) -{ - SIM_DESC sd = (SIM_DESC) sc->p1; - SIM_CPU *cpu = (SIM_CPU *) sc->p2; - - return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); -} - -/* Handle the trap insn when --environment=user. */ - -static IADDR -sparc64_sw_trap_user (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - int trap = 128 + ((rs1 + rs2_simm13) & 127); - IADDR new_pc = pc + 4; - - switch (trap) - { - case TRAP32_SYSCALL : - /* FIXME: Later make trap number runtime selectable. */ - { - CB_SYSCALL s; - - CB_SYSCALL_INIT (&s); - s.func = a_sparc_h_gr_get (current_cpu, 8); - s.arg1 = a_sparc_h_gr_get (current_cpu, 9); - s.arg2 = a_sparc_h_gr_get (current_cpu, 10); - s.arg3 = a_sparc_h_gr_get (current_cpu, 11); - if (s.func == TARGET_SYS_exit) - { - /* Tell sim_resume program called exit(). */ - sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); - } - s.p1 = (PTR) sd; - s.p2 = (PTR) current_cpu; - s.read_mem = syscall_read_mem; - s.write_mem = syscall_write_mem; - cb_syscall (STATE_CALLBACK (CPU_STATE (current_cpu)), &s); - a_sparc_h_gr_set (current_cpu, 10, s.errcode); - a_sparc_h_gr_set (current_cpu, 8, s.result); - a_sparc_h_gr_set (current_cpu, 9, s.result2); - break; - } - - case TRAP32_BREAKPOINT : - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); - - case TRAP32_DIVIDE_0 : - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE); - - case TRAP32_FLUSH_REGWIN : - sparc64_flush_regwins (current_cpu, pc, 0 /* error ok */); - break; - - default : - sim_io_eprintf (sd, "Unsupported trap %d\n", trap); - sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL); - } - - return new_pc; -} - -/* Called from the semantic code to handle the trap instruction. */ - -IADDR -sparc64_sw_trap (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - SIM_DESC sd = CPU_STATE (current_cpu); - IADDR new_pc; - - if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) - new_pc = sparc64_sw_trap_oper (current_cpu, pc, rs1, rs2_simm13); - else - new_pc = sparc64_sw_trap_user (current_cpu, pc, rs1, rs2_simm13); - return new_pc; -} - -/* Handle the rett insn. */ - -IADDR -sparc64_do_rett (SIM_CPU *current_cpu, IADDR pc, SI rs1, SI rs2_simm13) -{ - int psr = GET_H_PSR (); - - /* FIXME: check for trap conditions. */ - - SET_H_PSR ((psr & ~(PSR_S + PSR_CWP)) - | ((psr & PSR_PS) ? PSR_S : 0) - | PSR_ET - | PREV_WIN (psr & PSR_CWP)); - - if (TRACE_INSN_P (current_cpu)) /* FIXME */ - { - trace_result (current_cpu, "sp", 'x', GET_H_GR (H_GR__SP)); - trace_result (current_cpu, "fp", 'x', GET_H_GR (H_GR__FP)); - trace_result (current_cpu, "cwp", 'x', GET_H_CWP ()); - } - - return rs1 + rs2_simm13; -} diff --git a/sim/sparc/trap64.h b/sim/sparc/trap64.h deleted file mode 100644 index d51d8f1..0000000 --- a/sim/sparc/trap64.h +++ /dev/null @@ -1,86 +0,0 @@ -/* sparc64 trap definitions - Copyright (C) 1999 Cygnus Solutions. */ - -#ifndef TRAP64_H -#define TRAP64_H - -/* D1.2.4 page 107 */ - -typedef enum -{ - TRAP64_POWER_ON_RESET = 1, - TRAP64_WATCHDOG_RESET = 2, - TRAP64_EXTERNALLY_INITIATED_RESET = 3, - TRAP64_SOFTWARE_INITIATED_RESET = 4, - TRAP64_RED_STATE_EXCEPTION = 5, - TRAP64_INSN_ACCESS_EXCEPTION = 8, - TRAP64_INSN_ACCESS_MMU_MISS = 9, - TRAP64_INSN_ACCESS_ERROR = 10, - TRAP64_ILLEGAL_INSN = 16, - TRAP64_PRIVILEDGED_OPCODE = 17, - TRAP64_UNIMPLEMENTED_LDD = 18, - TRAP64_UNIMPLEMENTED_STD = 19, - TRAP64_FP_DISABLED = 32, - TRAP64_FP_EXCEPTION_IEEE_754 = 33, - TRAP64_FP_EXCEPTION_OTHER = 34, - TRAP64_TAG_OVERFLOW = 35, - TRAP64_CLEAN_WINDOW = 36, - TRAP64_DIVISION_BY_ZERO = 40, - TRAP64_INTERNAL_PROCESSOR_ERROR = 41, - TRAP64_DATA_ACCESS_EXCEPTION = 48, - TRAP64_DATA_ACCESS_MMU_MISS = 49, - TRAP64_DATA_ACCESS_ERROR = 50, - TRAP64_DATA_ACCESS_PROTECTION = 51, - TRAP64_MEM_ADDRESS_NOT_ALIGNED = 52, - TRAP64_LDDF_MEM_ADDRESS_NOT_ALIGNED = 53, /* impdep # 109 */ - TRAP64_STDF_MEM_ADDRESS_NOT_ALIGNED = 54, /* impdep # 110 */ - TRAP64_PRIVILEDGED_ACTION = 55, - TRAP64_LDQF_MEM_ADDRESS_NOT_ALIGNED = 56, /* impdep # 111 */ - TRAP64_STQF_MEM_ADDRESS_NOT_ALIGNED = 57, /* impdep # 112 */ - TRAP64_ASYNC_DATA_ERROR = 64, - TRAP64_INTERRUPT_LEVEL_0 = 65, /* n = 1..15 */ - TRAP64_IMPDEP_EXCEPTION_0 = 96, /* n = 0..31 */ - - /* IMPDEP codes used by the simulator in ENVIRONMENT_USER. */ - TRAP64_SIM_UNIMPLEMENTED_OPCODE = 124, - TRAP64_SIM_RESERVED_INSN = 125, - TRAP64_SIM_SPILL = 126, - TRAP64_SIM_FILL = 127, - - TRAP64_SPILL_0_NORMAL = 128, /* n = 0..7 */ - TRAP64_SPILL_0_OTHER = 160, /* n = 0..7 */ - TRAP64_FILL_0_NORMAL = 192, /* n = 0..7 */ - TRAP64_FILL_0_OTHER = 224, /* n = 0..7 */ - TRAP64_INSTRUCTION = 256, /* n = 0..127 */ - TRAP64_BREAKPOINT = 257, /* convention */ - TRAP64_MAX = 0x17f -} TRAP64_TYPE; - -#define MAX_NUM_TRAPS 1024 - -#define TRAP64_TABLE_SIZE (32 * MAX_NUM_TRAPS) /* in bytes */ - -/* We record the fact that the cpu is in error state by setting TL to be - something greater than MAXTL, usually MAXTL+1. */ - -#define ERROR_STATE_P() (GET_TL () > MAXTL) - -#if 0 -fastint trap (trap_type_e); -int trap_priority (trap_type_e); - -fastint reserved (void); -fastint deprecated (void); -fastint not_impl (void); -fastint illegal (void); -fastint priviledged (void); -fastint unimp_fpop (void); -fastint fp_disabled (void); - -/* When running user level programs, we supply all the necessary trap handlers. - These handlers run on the host, not in the emulation environment. */ - -typedef fastint (trap_handler_t) (void); -#endif - -#endif /* TRAP64_H */ |