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-rw-r--r--sim/sh/ChangeLog1
-rw-r--r--sim/sh/gencode.c7
2 files changed, 5 insertions, 3 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index ad4bd8f..2b6624d 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -4,6 +4,7 @@
2003-06-27 Michael Snyder <msnyder@redhat.com>
+ * gencode.c (op tab): Implement movca.l.
* gencode.c (op movsxy_tab): Fix an error in the bit pattern.
* gencode.c (gensim_caselist): The movy instructions use
registers R6 and R7 (not R4 and R5 like the movx insns).
diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index e8e780f..ea6d323 100644
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -750,9 +750,10 @@ op tab[] =
"R0 = ((i + 4 + PH2T (PC)) & ~0x3);",
},
- { "0", "", "movca.l @R0, <REG_N>", "0000nnnn11000011",
- "/* FIXME: Not implemented */",
- "RAISE_EXCEPTION (SIGILL);",
+ { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011",
+ "/* We don't simulate cache, so this insn is identical to mov. */",
+ "MA (1);",
+ "WLAT (R[n], R[0]);",
},
{ "n", "", "movt <REG_N>", "0000nnnn00101001",