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-rw-r--r--sim/riscv/sim-main.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index afdfcf5..4d20534 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -126,6 +126,7 @@ store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
case CSR_INSTRETH:
case CSR_TIMEH:
RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
+ ATTRIBUTE_FALLTHROUGH;
/* All the rest are immutable. */
default: