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-rwxr-xr-xsim/riscv/configure2
1 files changed, 0 insertions, 2 deletions
diff --git a/sim/riscv/configure b/sim/riscv/configure
index 9afaa1f2..aa123f5 100755
--- a/sim/riscv/configure
+++ b/sim/riscv/configure
@@ -11149,8 +11149,6 @@ fi
-
-
wire_endian="LITTLE"
default_endian=""
# Check whether --enable-sim-endian was given.