diff options
Diffstat (limited to 'sim/ppc/ppc-cache-rules')
| -rw-r--r-- | sim/ppc/ppc-cache-rules | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/sim/ppc/ppc-cache-rules b/sim/ppc/ppc-cache-rules index 270fb4a..2b5f472 100644 --- a/sim/ppc/ppc-cache-rules +++ b/sim/ppc/ppc-cache-rules @@ -20,6 +20,7 @@ cache:RA:RA:: cache:RA:rA:signed_word *:(cpu_registers(processor)->gpr + RA) cache:RA:RA_BITMASK:unsigned32:(1 << RA) +compute:RA:RA_is_0:int:(RA == 0) cache:RT:RT:: cache:RT:rT:signed_word *:(cpu_registers(processor)->gpr + RT) cache:RT:RT_BITMASK:unsigned32:(1 << RT) @@ -29,30 +30,30 @@ cache:RS:RS_BITMASK:unsigned32:(1 << RS) cache:RB:RB:: cache:RB:rB:signed_word *:(cpu_registers(processor)->gpr + RB) cache:RB:RB_BITMASK:unsigned32:(1 << RB) -compute:FRA:FRA:: +scratch:FRA:FRA:: cache:FRA:frA:unsigned64 *:(cpu_registers(processor)->fpr + FRA) cache:FRA:FRA_BITMASK:unsigned32:(1 << FRA) -compute:FRB:FRB:: +scratch:FRB:FRB:: cache:FRB:frB:unsigned64 *:(cpu_registers(processor)->fpr + FRB) cache:FRB:FRB_BITMASK:unsigned32:(1 << FRB) -compute:FRC:FRC:: +scratch:FRC:FRC:: cache:FRC:frC:unsigned64 *:(cpu_registers(processor)->fpr + FRC) cache:FRC:FRC_BITMASK:unsigned32:(1 << FRC) -compute:FRS:FRS:: +scratch:FRS:FRS:: cache:FRS:frS:unsigned64 *:(cpu_registers(processor)->fpr + FRS) cache:FRS:FRS_BITMASK:unsigned32:(1 << FRS) -compute:FRT:FRT:: +scratch:FRT:FRT:: cache:FRT:frT:unsigned64 *:(cpu_registers(processor)->fpr + FRT) cache:FRT:FRT_BITMASK:unsigned32:(1 << FRT) cache:SI:EXTS_SI:unsigned_word:((signed_word)(signed16)instruction) -compute:BI:BI:: +scratch:BI:BI:: cache:BI:BIT32_BI::BIT32(BI) cache:BF:BF:: cache:BF:BF_BITMASK:unsigned32:(1 << BF) -compute:BA:BA:: +scratch:BA:BA:: cache:BA:BIT32_BA::BIT32(BA) cache:BA:BA_BITMASK:unsigned32:(1 << BA) -compute:BB:BB:: +scratch:BB:BB:: cache:BB:BIT32_BB::BIT32(BB) cache:BB:BB_BITMASK:unsigned32:(1 << BB) cache:BT:BT:: @@ -61,3 +62,4 @@ cache:BD:EXTS_BD_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~3) cache:LI:EXTS_LI_0b00:unsigned_word:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3) cache:D:EXTS_D:unsigned_word:((signed_word)(signed16)(instruction)) cache:DS:EXTS_DS_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~0x3) +#compute:SPR:SPR_is_256:int:(SPR == 256) |