diff options
Diffstat (limited to 'sim/or1k')
-rw-r--r-- | sim/or1k/cpu.h | 32 | ||||
-rw-r--r-- | sim/or1k/decode.c | 239 | ||||
-rw-r--r-- | sim/or1k/decode.h | 82 | ||||
-rw-r--r-- | sim/or1k/model.c | 186 | ||||
-rw-r--r-- | sim/or1k/sem-switch.c | 281 | ||||
-rw-r--r-- | sim/or1k/sem.c | 293 |
6 files changed, 945 insertions, 168 deletions
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h index 9646c33..b847f53 100644 --- a/sim/or1k/cpu.h +++ b/sim/or1k/cpu.h @@ -4516,6 +4516,10 @@ union sem_fields { IADDR i_disp26; } sfmt_l_j; struct { /* */ + IADDR i_disp21; + UINT f_r1; + } sfmt_l_adrp; + struct { /* */ UINT f_r1; UINT f_r2; UINT f_uimm6; @@ -4614,6 +4618,17 @@ struct scache { f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc)); \ +#define EXTRACT_IFMT_L_ADRP_VARS \ + UINT f_opcode; \ + UINT f_r1; \ + USI f_disp21; \ + unsigned int length; +#define EXTRACT_IFMT_L_ADRP_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13)); \ + #define EXTRACT_IFMT_L_JR_VARS \ UINT f_opcode; \ UINT f_resv_25_10; \ @@ -4831,6 +4846,23 @@ struct scache { f_resv_10_7 = EXTRACT_LSB0_UINT (insn, 32, 10, 7); \ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ +#define EXTRACT_IFMT_L_MULD_VARS \ + UINT f_opcode; \ + UINT f_resv_25_5; \ + UINT f_r2; \ + UINT f_r3; \ + UINT f_resv_10_7; \ + UINT f_op_3_4; \ + unsigned int length; +#define EXTRACT_IFMT_L_MULD_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_resv_10_7 = EXTRACT_LSB0_UINT (insn, 32, 10, 7); \ + f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + #define EXTRACT_IFMT_L_EXTHS_VARS \ UINT f_opcode; \ UINT f_r1; \ diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c index bc99cc2..e62476f 100644 --- a/sim/or1k/decode.c +++ b/sim/or1k/decode.c @@ -47,6 +47,7 @@ static const struct insn_sem or1k32bf_insn_sem[] = { VIRTUAL_INSN_X_CHAIN, OR1K32BF_INSN_X_CHAIN, OR1K32BF_SFMT_EMPTY }, { VIRTUAL_INSN_X_BEGIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_SFMT_EMPTY }, { OR1K_INSN_L_J, OR1K32BF_INSN_L_J, OR1K32BF_SFMT_L_J }, + { OR1K_INSN_L_ADRP, OR1K32BF_INSN_L_ADRP, OR1K32BF_SFMT_L_ADRP }, { OR1K_INSN_L_JAL, OR1K32BF_INSN_L_JAL, OR1K32BF_SFMT_L_JAL }, { OR1K_INSN_L_JR, OR1K32BF_INSN_L_JR, OR1K32BF_SFMT_L_JR }, { OR1K_INSN_L_JALR, OR1K32BF_INSN_L_JALR, OR1K32BF_SFMT_L_JALR }, @@ -88,10 +89,12 @@ static const struct insn_sem or1k32bf_insn_sem[] = { OR1K_INSN_L_ADD, OR1K32BF_INSN_L_ADD, OR1K32BF_SFMT_L_ADD }, { OR1K_INSN_L_SUB, OR1K32BF_INSN_L_SUB, OR1K32BF_SFMT_L_ADD }, { OR1K_INSN_L_ADDC, OR1K32BF_INSN_L_ADDC, OR1K32BF_SFMT_L_ADDC }, - { OR1K_INSN_L_MUL, OR1K32BF_INSN_L_MUL, OR1K32BF_SFMT_L_ADD }, - { OR1K_INSN_L_MULU, OR1K32BF_INSN_L_MULU, OR1K32BF_SFMT_L_ADD }, + { OR1K_INSN_L_MUL, OR1K32BF_INSN_L_MUL, OR1K32BF_SFMT_L_MUL }, + { OR1K_INSN_L_MULD, OR1K32BF_INSN_L_MULD, OR1K32BF_SFMT_L_MULD }, + { OR1K_INSN_L_MULU, OR1K32BF_INSN_L_MULU, OR1K32BF_SFMT_L_MULU }, + { OR1K_INSN_L_MULDU, OR1K32BF_INSN_L_MULDU, OR1K32BF_SFMT_L_MULD }, { OR1K_INSN_L_DIV, OR1K32BF_INSN_L_DIV, OR1K32BF_SFMT_L_DIV }, - { OR1K_INSN_L_DIVU, OR1K32BF_INSN_L_DIVU, OR1K32BF_SFMT_L_DIV }, + { OR1K_INSN_L_DIVU, OR1K32BF_INSN_L_DIVU, OR1K32BF_SFMT_L_DIVU }, { OR1K_INSN_L_FF1, OR1K32BF_INSN_L_FF1, OR1K32BF_SFMT_L_FF1 }, { OR1K_INSN_L_FL1, OR1K32BF_INSN_L_FL1, OR1K32BF_SFMT_L_FF1 }, { OR1K_INSN_L_ANDI, OR1K32BF_INSN_L_ANDI, OR1K32BF_SFMT_L_MFSPR }, @@ -99,7 +102,7 @@ static const struct insn_sem or1k32bf_insn_sem[] = { OR1K_INSN_L_XORI, OR1K32BF_INSN_L_XORI, OR1K32BF_SFMT_L_XORI }, { OR1K_INSN_L_ADDI, OR1K32BF_INSN_L_ADDI, OR1K32BF_SFMT_L_ADDI }, { OR1K_INSN_L_ADDIC, OR1K32BF_INSN_L_ADDIC, OR1K32BF_SFMT_L_ADDIC }, - { OR1K_INSN_L_MULI, OR1K32BF_INSN_L_MULI, OR1K32BF_SFMT_L_ADDI }, + { OR1K_INSN_L_MULI, OR1K32BF_INSN_L_MULI, OR1K32BF_SFMT_L_MULI }, { OR1K_INSN_L_EXTHS, OR1K32BF_INSN_L_EXTHS, OR1K32BF_SFMT_L_EXTHS }, { OR1K_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTBS, OR1K32BF_SFMT_L_EXTHS }, { OR1K_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_SFMT_L_EXTHS }, @@ -128,8 +131,10 @@ static const struct insn_sem or1k32bf_insn_sem[] = { OR1K_INSN_L_SFNE, OR1K32BF_INSN_L_SFNE, OR1K32BF_SFMT_L_SFGTS }, { OR1K_INSN_L_SFNEI, OR1K32BF_INSN_L_SFNEI, OR1K32BF_SFMT_L_SFGTSI }, { OR1K_INSN_L_MAC, OR1K32BF_INSN_L_MAC, OR1K32BF_SFMT_L_MAC }, - { OR1K_INSN_L_MSB, OR1K32BF_INSN_L_MSB, OR1K32BF_SFMT_L_MAC }, { OR1K_INSN_L_MACI, OR1K32BF_INSN_L_MACI, OR1K32BF_SFMT_L_MACI }, + { OR1K_INSN_L_MACU, OR1K32BF_INSN_L_MACU, OR1K32BF_SFMT_L_MACU }, + { OR1K_INSN_L_MSB, OR1K32BF_INSN_L_MSB, OR1K32BF_SFMT_L_MAC }, + { OR1K_INSN_L_MSBU, OR1K32BF_INSN_L_MSBU, OR1K32BF_SFMT_L_MACU }, { OR1K_INSN_L_CUST1, OR1K32BF_INSN_L_CUST1, OR1K32BF_SFMT_L_MSYNC }, { OR1K_INSN_L_CUST2, OR1K32BF_INSN_L_CUST2, OR1K32BF_SFMT_L_MSYNC }, { OR1K_INSN_L_CUST3, OR1K32BF_INSN_L_CUST3, OR1K32BF_SFMT_L_MSYNC }, @@ -297,6 +302,38 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, case 61 : /* fall through */ case 62 : /* fall through */ case 63 : itype = OR1K32BF_INSN_L_JAL; goto extract_sfmt_l_jal; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : /* fall through */ + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : /* fall through */ + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : /* fall through */ + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : /* fall through */ + case 80 : /* fall through */ + case 81 : /* fall through */ + case 82 : /* fall through */ + case 83 : /* fall through */ + case 84 : /* fall through */ + case 85 : /* fall through */ + case 86 : /* fall through */ + case 87 : /* fall through */ + case 88 : /* fall through */ + case 89 : /* fall through */ + case 90 : /* fall through */ + case 91 : /* fall through */ + case 92 : /* fall through */ + case 93 : /* fall through */ + case 94 : /* fall through */ + case 95 : itype = OR1K32BF_INSN_L_ADRP; goto extract_sfmt_l_adrp; case 96 : /* fall through */ case 97 : /* fall through */ case 98 : /* fall through */ @@ -998,7 +1035,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, case 1436 : /* fall through */ case 1437 : /* fall through */ case 1438 : /* fall through */ - case 1439 : itype = OR1K32BF_INSN_L_MULI; goto extract_sfmt_l_addi; + case 1439 : itype = OR1K32BF_INSN_L_MULI; goto extract_sfmt_l_muli; case 1440 : /* fall through */ case 1441 : /* fall through */ case 1442 : /* fall through */ @@ -1212,6 +1249,14 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, if ((entire_insn & 0xffe007ff) == 0xc4000002) { itype = OR1K32BF_INSN_L_MSB; goto extract_sfmt_l_mac; } itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1571 : + if ((entire_insn & 0xffe007ff) == 0xc4000003) + { itype = OR1K32BF_INSN_L_MACU; goto extract_sfmt_l_macu; } + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1572 : + if ((entire_insn & 0xffe007ff) == 0xc4000004) + { itype = OR1K32BF_INSN_L_MSBU; goto extract_sfmt_l_macu; } + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1600 : if ((entire_insn & 0xfc0007ff) == 0xc8000000) { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; } @@ -1426,7 +1471,11 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1798 : if ((entire_insn & 0xfc0007ff) == 0xe0000306) - { itype = OR1K32BF_INSN_L_MUL; goto extract_sfmt_l_add; } + { itype = OR1K32BF_INSN_L_MUL; goto extract_sfmt_l_mul; } + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + case 1799 : + if ((entire_insn & 0xffe007ff) == 0xe0000307) + { itype = OR1K32BF_INSN_L_MULD; goto extract_sfmt_l_muld; } itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1800 : { @@ -1450,11 +1499,11 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1802 : if ((entire_insn & 0xfc0007ff) == 0xe000030a) - { itype = OR1K32BF_INSN_L_DIVU; goto extract_sfmt_l_div; } + { itype = OR1K32BF_INSN_L_DIVU; goto extract_sfmt_l_divu; } itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1803 : if ((entire_insn & 0xfc0007ff) == 0xe000030b) - { itype = OR1K32BF_INSN_L_MULU; goto extract_sfmt_l_add; } + { itype = OR1K32BF_INSN_L_MULU; goto extract_sfmt_l_mulu; } itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1804 : { @@ -1473,9 +1522,21 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } } case 1805 : - if ((entire_insn & 0xfc00ffff) == 0xe000000d) - { itype = OR1K32BF_INSN_L_EXTWS; goto extract_sfmt_l_exths; } - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + { + unsigned int val = (((insn >> 8) & (3 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xfc00ffff) == 0xe000000d) + { itype = OR1K32BF_INSN_L_EXTWS; goto extract_sfmt_l_exths; } + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xffe007ff) == 0xe000030d) + { itype = OR1K32BF_INSN_L_MULDU; goto extract_sfmt_l_muld; } + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; + } + } case 1806 : if ((entire_insn & 0xfc0007ff) == 0xe000000e) { itype = OR1K32BF_INSN_L_CMOV; goto extract_sfmt_l_cmov; } @@ -1633,6 +1694,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_l_adrp: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_adrp.f + UINT f_r1; + USI f_disp21; + + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13)); + + /* Record the fields for the semantic handler. */ + FLD (f_r1) = f_r1; + FLD (i_disp21) = f_disp21; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_adrp", "f_r1 0x%x", 'x', f_r1, "disp21 0x%x", 'x', f_disp21, (char *) 0)); + +#undef FLD + return idesc; + } + extract_sfmt_l_jal: { const IDESC *idesc = &or1k32bf_insn_data[itype]; @@ -1768,7 +1849,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &or1k32bf_insn_data[itype]; CGEN_INSN_WORD insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f UINT f_r1; f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); @@ -2215,6 +2296,72 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_l_mul: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_sll.f + UINT f_r1; + UINT f_r2; + UINT f_r3; + + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r3) = f_r3; + FLD (f_r1) = f_r1; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mul", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_l_muld: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_sll.f + UINT f_r2; + UINT f_r3; + + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r3) = f_r3; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_muld", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_l_mulu: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_sll.f + UINT f_r1; + UINT f_r2; + UINT f_r3; + + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r3) = f_r3; + FLD (f_r1) = f_r1; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mulu", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0)); + +#undef FLD + return idesc; + } + extract_sfmt_l_div: { const IDESC *idesc = &or1k32bf_insn_data[itype]; @@ -2238,6 +2385,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_l_divu: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_sll.f + UINT f_r1; + UINT f_r2; + UINT f_r3; + + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r3) = f_r3; + FLD (f_r1) = f_r1; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_divu", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0)); + +#undef FLD + return idesc; + } + extract_sfmt_l_ff1: { const IDESC *idesc = &or1k32bf_insn_data[itype]; @@ -2327,6 +2497,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_l_muli: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_lwz.f + UINT f_r1; + UINT f_r2; + INT f_simm16; + + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_simm16) = f_simm16; + FLD (f_r1) = f_r1; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_muli", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0)); + +#undef FLD + return idesc; + } + extract_sfmt_l_exths: { const IDESC *idesc = &or1k32bf_insn_data[itype]; @@ -2450,6 +2643,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_l_macu: + { + const IDESC *idesc = &or1k32bf_insn_data[itype]; + CGEN_INSN_WORD insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_l_sll.f + UINT f_r2; + UINT f_r3; + + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); + + /* Record the fields for the semantic handler. */ + FLD (f_r2) = f_r2; + FLD (f_r3) = f_r3; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_macu", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0)); + +#undef FLD + return idesc; + } + extract_sfmt_lf_add_s: { const IDESC *idesc = &or1k32bf_insn_data[itype]; diff --git a/sim/or1k/decode.h b/sim/or1k/decode.h index 019a0aa..b45e4f2 100644 --- a/sim/or1k/decode.h +++ b/sim/or1k/decode.h @@ -35,50 +35,52 @@ extern void or1k32bf_semf_init_idesc_table (SIM_CPU *); /* Enum declaration for instructions in cpu family or1k32bf. */ typedef enum or1k32bf_insn_type { OR1K32BF_INSN_X_INVALID, OR1K32BF_INSN_X_AFTER, OR1K32BF_INSN_X_BEFORE, OR1K32BF_INSN_X_CTI_CHAIN - , OR1K32BF_INSN_X_CHAIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_INSN_L_J, OR1K32BF_INSN_L_JAL - , OR1K32BF_INSN_L_JR, OR1K32BF_INSN_L_JALR, OR1K32BF_INSN_L_BNF, OR1K32BF_INSN_L_BF - , OR1K32BF_INSN_L_TRAP, OR1K32BF_INSN_L_SYS, OR1K32BF_INSN_L_MSYNC, OR1K32BF_INSN_L_PSYNC - , OR1K32BF_INSN_L_CSYNC, OR1K32BF_INSN_L_RFE, OR1K32BF_INSN_L_NOP_IMM, OR1K32BF_INSN_L_MOVHI - , OR1K32BF_INSN_L_MACRC, OR1K32BF_INSN_L_MFSPR, OR1K32BF_INSN_L_MTSPR, OR1K32BF_INSN_L_LWZ - , OR1K32BF_INSN_L_LWS, OR1K32BF_INSN_L_LWA, OR1K32BF_INSN_L_LBZ, OR1K32BF_INSN_L_LBS - , OR1K32BF_INSN_L_LHZ, OR1K32BF_INSN_L_LHS, OR1K32BF_INSN_L_SW, OR1K32BF_INSN_L_SB - , OR1K32BF_INSN_L_SH, OR1K32BF_INSN_L_SWA, OR1K32BF_INSN_L_SLL, OR1K32BF_INSN_L_SLLI - , OR1K32BF_INSN_L_SRL, OR1K32BF_INSN_L_SRLI, OR1K32BF_INSN_L_SRA, OR1K32BF_INSN_L_SRAI - , OR1K32BF_INSN_L_ROR, OR1K32BF_INSN_L_RORI, OR1K32BF_INSN_L_AND, OR1K32BF_INSN_L_OR - , OR1K32BF_INSN_L_XOR, OR1K32BF_INSN_L_ADD, OR1K32BF_INSN_L_SUB, OR1K32BF_INSN_L_ADDC - , OR1K32BF_INSN_L_MUL, OR1K32BF_INSN_L_MULU, OR1K32BF_INSN_L_DIV, OR1K32BF_INSN_L_DIVU - , OR1K32BF_INSN_L_FF1, OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI - , OR1K32BF_INSN_L_XORI, OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI - , OR1K32BF_INSN_L_EXTHS, OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ - , OR1K32BF_INSN_L_EXTWS, OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS - , OR1K32BF_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES - , OR1K32BF_INSN_L_SFGESI, OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS - , OR1K32BF_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES - , OR1K32BF_INSN_L_SFLESI, OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ - , OR1K32BF_INSN_L_SFEQI, OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC - , OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MACI, OR1K32BF_INSN_L_CUST1, OR1K32BF_INSN_L_CUST2 - , OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5, OR1K32BF_INSN_L_CUST6 - , OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_INSN_LF_SUB_S - , OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_INSN_LF_ITOF_S - , OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_INSN_LF_GE_S - , OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_INSN_LF_MADD_S - , OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX + , OR1K32BF_INSN_X_CHAIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_INSN_L_J, OR1K32BF_INSN_L_ADRP + , OR1K32BF_INSN_L_JAL, OR1K32BF_INSN_L_JR, OR1K32BF_INSN_L_JALR, OR1K32BF_INSN_L_BNF + , OR1K32BF_INSN_L_BF, OR1K32BF_INSN_L_TRAP, OR1K32BF_INSN_L_SYS, OR1K32BF_INSN_L_MSYNC + , OR1K32BF_INSN_L_PSYNC, OR1K32BF_INSN_L_CSYNC, OR1K32BF_INSN_L_RFE, OR1K32BF_INSN_L_NOP_IMM + , OR1K32BF_INSN_L_MOVHI, OR1K32BF_INSN_L_MACRC, OR1K32BF_INSN_L_MFSPR, OR1K32BF_INSN_L_MTSPR + , OR1K32BF_INSN_L_LWZ, OR1K32BF_INSN_L_LWS, OR1K32BF_INSN_L_LWA, OR1K32BF_INSN_L_LBZ + , OR1K32BF_INSN_L_LBS, OR1K32BF_INSN_L_LHZ, OR1K32BF_INSN_L_LHS, OR1K32BF_INSN_L_SW + , OR1K32BF_INSN_L_SB, OR1K32BF_INSN_L_SH, OR1K32BF_INSN_L_SWA, OR1K32BF_INSN_L_SLL + , OR1K32BF_INSN_L_SLLI, OR1K32BF_INSN_L_SRL, OR1K32BF_INSN_L_SRLI, OR1K32BF_INSN_L_SRA + , OR1K32BF_INSN_L_SRAI, OR1K32BF_INSN_L_ROR, OR1K32BF_INSN_L_RORI, OR1K32BF_INSN_L_AND + , OR1K32BF_INSN_L_OR, OR1K32BF_INSN_L_XOR, OR1K32BF_INSN_L_ADD, OR1K32BF_INSN_L_SUB + , OR1K32BF_INSN_L_ADDC, OR1K32BF_INSN_L_MUL, OR1K32BF_INSN_L_MULD, OR1K32BF_INSN_L_MULU + , OR1K32BF_INSN_L_MULDU, OR1K32BF_INSN_L_DIV, OR1K32BF_INSN_L_DIVU, OR1K32BF_INSN_L_FF1 + , OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI, OR1K32BF_INSN_L_XORI + , OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI, OR1K32BF_INSN_L_EXTHS + , OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ, OR1K32BF_INSN_L_EXTWS + , OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTSI + , OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES, OR1K32BF_INSN_L_SFGESI + , OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTSI + , OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFLESI + , OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI + , OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC, OR1K32BF_INSN_L_MACI + , OR1K32BF_INSN_L_MACU, OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MSBU, OR1K32BF_INSN_L_CUST1 + , OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5 + , OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S + , OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S + , OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S + , OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S + , OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX } OR1K32BF_INSN_TYPE; /* Enum declaration for semantic formats in cpu family or1k32bf. */ typedef enum or1k32bf_sfmt_type { - OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_JAL, OR1K32BF_SFMT_L_JR - , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_MSYNC - , OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR - , OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LWA - , OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS - , OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SWA - , OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND, OR1K32BF_SFMT_L_ADD - , OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_FF1, OR1K32BF_SFMT_L_XORI - , OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV - , OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI - , OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S - , OR1K32BF_SFMT_LF_MADD_S + OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_ADRP, OR1K32BF_SFMT_L_JAL + , OR1K32BF_SFMT_L_JR, OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP + , OR1K32BF_SFMT_L_MSYNC, OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC + , OR1K32BF_SFMT_L_MFSPR, OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS + , OR1K32BF_SFMT_L_LWA, OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ + , OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH + , OR1K32BF_SFMT_L_SWA, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND + , OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_MUL, OR1K32BF_SFMT_L_MULD + , OR1K32BF_SFMT_L_MULU, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_DIVU, OR1K32BF_SFMT_L_FF1 + , OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_MULI + , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI + , OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_MACU, OR1K32BF_SFMT_LF_ADD_S + , OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S } OR1K32BF_SFMT_TYPE; /* Function unit handlers (user written). */ diff --git a/sim/or1k/model.c b/sim/or1k/model.c index 35c6479..bf6b00b 100644 --- a/sim/or1k/model.c +++ b/sim/or1k/model.c @@ -51,6 +51,22 @@ model_or1200_l_j (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_adrp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_adrp.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_jal (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_j.f @@ -261,7 +277,7 @@ model_or1200_l_movhi (SIM_CPU *current_cpu, void *sem_arg) static int model_or1200_l_macrc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -723,6 +739,22 @@ model_or1200_l_mul (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_muld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_mulu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -739,6 +771,22 @@ model_or1200_l_mulu (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_muldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_div (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1347,6 +1395,38 @@ model_or1200_l_mac (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200_l_maci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_lwz.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200_l_macu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200_l_msb (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -1363,9 +1443,9 @@ model_or1200_l_msb (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200_l_maci (SIM_CPU *current_cpu, void *sem_arg) +model_or1200_l_msbu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_lwz.f +#define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1763,6 +1843,22 @@ model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_adrp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_adrp.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_jal (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_j.f @@ -1973,7 +2069,7 @@ model_or1200nd_l_movhi (SIM_CPU *current_cpu, void *sem_arg) static int model_or1200nd_l_macrc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2435,6 +2531,22 @@ model_or1200nd_l_mul (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_muld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -2451,6 +2563,22 @@ model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_muldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_div (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3059,6 +3187,38 @@ model_or1200nd_l_mac (SIM_CPU *current_cpu, void *sem_arg) } static int +model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_lwz.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_or1200nd_l_macu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_l_sll.f @@ -3075,9 +3235,9 @@ model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg) } static int -model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg) +model_or1200nd_l_msbu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_lwz.f +#define FLD(f) abuf->fields.sfmt_l_sll.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3471,6 +3631,7 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_X_CHAIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_X_BEGIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_J, model_or1200_l_j, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_ADRP, model_or1200_l_adrp, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JAL, model_or1200_l_jal, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JR, model_or1200_l_jr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JALR, model_or1200_l_jalr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, @@ -3513,7 +3674,9 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_L_SUB, model_or1200_l_sub, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_ADDC, model_or1200_l_addc, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MUL, model_or1200_l_mul, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULD, model_or1200_l_muld, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MULU, model_or1200_l_mulu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULDU, model_or1200_l_muldu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIV, model_or1200_l_div, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIVU, model_or1200_l_divu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_FF1, model_or1200_l_ff1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, @@ -3552,8 +3715,10 @@ static const INSN_TIMING or1200_timing[] = { { OR1K32BF_INSN_L_SFNE, model_or1200_l_sfne, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_SFNEI, model_or1200_l_sfnei, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MAC, model_or1200_l_mac, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_L_MSB, model_or1200_l_msb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MACI, model_or1200_l_maci, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MACU, model_or1200_l_macu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSB, model_or1200_l_msb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSBU, model_or1200_l_msbu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST1, model_or1200_l_cust1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST2, model_or1200_l_cust2, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST3, model_or1200_l_cust3, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } }, @@ -3589,6 +3754,7 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_X_CHAIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_X_BEGIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_J, model_or1200nd_l_j, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_ADRP, model_or1200nd_l_adrp, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JAL, model_or1200nd_l_jal, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JR, model_or1200nd_l_jr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_JALR, model_or1200nd_l_jalr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, @@ -3631,7 +3797,9 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_L_SUB, model_or1200nd_l_sub, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_ADDC, model_or1200nd_l_addc, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MUL, model_or1200nd_l_mul, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULD, model_or1200nd_l_muld, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MULU, model_or1200nd_l_mulu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MULDU, model_or1200nd_l_muldu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIV, model_or1200nd_l_div, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_DIVU, model_or1200nd_l_divu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_FF1, model_or1200nd_l_ff1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, @@ -3670,8 +3838,10 @@ static const INSN_TIMING or1200nd_timing[] = { { OR1K32BF_INSN_L_SFNE, model_or1200nd_l_sfne, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_SFNEI, model_or1200nd_l_sfnei, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MAC, model_or1200nd_l_mac, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, - { OR1K32BF_INSN_L_MSB, model_or1200nd_l_msb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_MACI, model_or1200nd_l_maci, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MACU, model_or1200nd_l_macu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSB, model_or1200nd_l_msb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, + { OR1K32BF_INSN_L_MSBU, model_or1200nd_l_msbu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST1, model_or1200nd_l_cust1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST2, model_or1200nd_l_cust2, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, { OR1K32BF_INSN_L_CUST3, model_or1200nd_l_cust3, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } }, diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c index 2f8e0f3..2045567 100644 --- a/sim/or1k/sem-switch.c +++ b/sim/or1k/sem-switch.c @@ -39,6 +39,7 @@ This file is part of the GNU simulators. { OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, { OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, { OR1K32BF_INSN_L_J, && case_sem_INSN_L_J }, + { OR1K32BF_INSN_L_ADRP, && case_sem_INSN_L_ADRP }, { OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL }, { OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR }, { OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR }, @@ -81,7 +82,9 @@ This file is part of the GNU simulators. { OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB }, { OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC }, { OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL }, + { OR1K32BF_INSN_L_MULD, && case_sem_INSN_L_MULD }, { OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU }, + { OR1K32BF_INSN_L_MULDU, && case_sem_INSN_L_MULDU }, { OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV }, { OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU }, { OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 }, @@ -120,8 +123,10 @@ This file is part of the GNU simulators. { OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE }, { OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI }, { OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC }, - { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB }, { OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI }, + { OR1K32BF_INSN_L_MACU, && case_sem_INSN_L_MACU }, + { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB }, + { OR1K32BF_INSN_L_MSBU, && case_sem_INSN_L_MSBU }, { OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 }, { OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 }, { OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 }, @@ -373,6 +378,25 @@ if (1) } NEXT (vpc); + CASE (sem, INSN_L_ADRP) : /* l.adrp $rD,${disp21} */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_l_adrp.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + USI opval = FLD (i_disp21); + SET_H_GPR (FLD (f_r1), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); @@ -690,7 +714,7 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16))); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1366,11 +1390,6 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } { - BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); - SET_H_SYS_SR_CY (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); - } - { USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_GPR (FLD (f_r1), opval); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); @@ -1385,7 +1404,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } NEXT (vpc); - CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */ + CASE (sem, INSN_L_MULD) : /* l.muld $rA,$rB */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -1395,12 +1414,35 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { -{ + DI tmp_result; + tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); { - BI opval = 0; - SET_H_SYS_SR_OV (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_l_sll.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ { BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_SYS_SR_CY (opval); @@ -1412,7 +1454,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); } } -if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } } @@ -1421,7 +1463,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } NEXT (vpc); - CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */ + CASE (sem, INSN_L_MULDU) : /* l.muldu $rA,$rB */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -1431,38 +1473,61 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { + DI tmp_result; + tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_l_sll.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { { { BI opval = 0; - SET_H_SYS_SR_CY (opval); - written |= (1 << 6); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); + SET_H_SYS_SR_OV (opval); + written |= (1 << 5); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } { SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_GPR (FLD (f_r1), opval); - written |= (1 << 5); + written |= (1 << 4); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); } } } else { +{ { BI opval = 1; - SET_H_SYS_SR_CY (opval); - written |= (1 << 6); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); - } -} - { - BI opval = 0; SET_H_SYS_SR_OV (opval); + written |= (1 << 5); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } -if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +if (GET_H_SYS_SR_OVE ()) { or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } } +} abuf->written = written; #undef FLD @@ -1478,39 +1543,34 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -{ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { { { BI opval = 0; SET_H_SYS_SR_CY (opval); - written |= (1 << 6); + written |= (1 << 5); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); } { USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_GPR (FLD (f_r1), opval); - written |= (1 << 5); + written |= (1 << 4); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); } } } else { +{ { BI opval = 1; SET_H_SYS_SR_CY (opval); - written |= (1 << 6); + written |= (1 << 5); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); } -} - { - BI opval = 0; - SET_H_SYS_SR_OV (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); - } -if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +if (GET_H_SYS_SR_OVE ()) { or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } } +} abuf->written = written; #undef FLD @@ -1703,11 +1763,6 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } { - USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); - SET_H_SYS_SR_CY (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); - } - { USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); SET_H_GPR (FLD (f_r1), opval); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); @@ -2256,10 +2311,97 @@ if (GET_H_SYS_SR_F ()) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI tmp_prod; +{ + DI tmp_prod; + DI tmp_mac; + DI tmp_result; + tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = ADDDI (tmp_prod, tmp_mac); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } + { + BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); + SET_H_SYS_SR_OV (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_l_lwz.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + DI tmp_prod; + DI tmp_mac; + DI tmp_result; + tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = ADDDI (tmp_mac, tmp_prod); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } + { + BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); + SET_H_SYS_SR_OV (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_L_MACU) : /* l.macu $rA,$rB */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_l_sll.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + DI tmp_prod; + DI tmp_mac; DI tmp_result; - tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); - tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod)); + tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = ADDDI (tmp_prod, tmp_mac); { SI opval = SUBWORDDISI (tmp_result, 0); SET_H_MAC_MACHI (opval); @@ -2270,6 +2412,15 @@ if (GET_H_SYS_SR_F ()) { SET_H_MAC_MACLO (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } + { + BI opval = ADDCFDI (tmp_prod, tmp_mac, 0); + SET_H_SYS_SR_CY (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} } #undef FLD @@ -2286,10 +2437,13 @@ if (GET_H_SYS_SR_F ()) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI tmp_prod; +{ + DI tmp_prod; + DI tmp_mac; DI tmp_result; - tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); - tmp_result = SUBDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod)); + tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = SUBDI (tmp_mac, tmp_prod); { SI opval = SUBWORDDISI (tmp_result, 0); SET_H_MAC_MACHI (opval); @@ -2300,26 +2454,38 @@ if (GET_H_SYS_SR_F ()) { SET_H_MAC_MACLO (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } + { + BI opval = SUBOFDI (tmp_mac, tmp_result, 0); + SET_H_SYS_SR_OV (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} } #undef FLD } NEXT (vpc); - CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */ + CASE (sem, INSN_L_MSBU) : /* l.msbu $rA,$rB */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_l_lwz.f +#define FLD(f) abuf->fields.sfmt_l_sll.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI tmp_prod; +{ + DI tmp_prod; + DI tmp_mac; DI tmp_result; - tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2))); - tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod)); + tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = SUBDI (tmp_mac, tmp_prod); { SI opval = SUBWORDDISI (tmp_result, 0); SET_H_MAC_MACHI (opval); @@ -2330,6 +2496,15 @@ if (GET_H_SYS_SR_F ()) { SET_H_MAC_MACLO (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } + { + BI opval = SUBCFDI (tmp_mac, tmp_result, 0); + SET_H_SYS_SR_CY (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} } #undef FLD diff --git a/sim/or1k/sem.c b/sim/or1k/sem.c index 6c052ac..f67e50e 100644 --- a/sim/or1k/sem.c +++ b/sim/or1k/sem.c @@ -228,6 +228,27 @@ if (1) #undef FLD } +/* l-adrp: l.adrp $rD,${disp21} */ + +static SEM_PC +SEM_FN_NAME (or1k32bf,l_adrp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_adrp.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + USI opval = FLD (i_disp21); + SET_H_GPR (FLD (f_r1), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + /* l-jal: l.jal ${disp26} */ static SEM_PC @@ -572,7 +593,7 @@ SEM_FN_NAME (or1k32bf,l_movhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (or1k32bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_slli.f +#define FLD(f) abuf->fields.sfmt_l_adrp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1305,11 +1326,6 @@ SEM_FN_NAME (or1k32bf,l_mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } { - BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); - SET_H_SYS_SR_CY (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); - } - { USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_GPR (FLD (f_r1), opval); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); @@ -1324,6 +1340,36 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); #undef FLD } +/* l-muld: l.muld $rA,$rB */ + +static SEM_PC +SEM_FN_NAME (or1k32bf,l_muld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + DI tmp_result; + tmp_result = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + /* l-mulu: l.mulu $rD,$rA,$rB */ static SEM_PC @@ -1338,11 +1384,6 @@ SEM_FN_NAME (or1k32bf,l_mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { { { - BI opval = 0; - SET_H_SYS_SR_OV (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); - } - { BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_SYS_SR_CY (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); @@ -1353,7 +1394,7 @@ SEM_FN_NAME (or1k32bf,l_mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); } } -if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } } @@ -1362,6 +1403,36 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); #undef FLD } +/* l-muldu: l.muldu $rA,$rB */ + +static SEM_PC +SEM_FN_NAME (or1k32bf,l_muldu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ + DI tmp_result; + tmp_result = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } +} + + return vpc; +#undef FLD +} + /* l-div: l.div $rD,$rA,$rB */ static SEM_PC @@ -1373,39 +1444,34 @@ SEM_FN_NAME (or1k32bf,l_div) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -{ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { { { BI opval = 0; - SET_H_SYS_SR_CY (opval); - written |= (1 << 6); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); + SET_H_SYS_SR_OV (opval); + written |= (1 << 5); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } { SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_GPR (FLD (f_r1), opval); - written |= (1 << 5); + written |= (1 << 4); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); } } } else { +{ { BI opval = 1; - SET_H_SYS_SR_CY (opval); - written |= (1 << 6); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); - } -} - { - BI opval = 0; SET_H_SYS_SR_OV (opval); + written |= (1 << 5); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } -if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +if (GET_H_SYS_SR_OVE ()) { or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } } +} abuf->written = written; return vpc; @@ -1423,39 +1489,34 @@ SEM_FN_NAME (or1k32bf,l_divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -{ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) { { { BI opval = 0; SET_H_SYS_SR_CY (opval); - written |= (1 << 6); + written |= (1 << 5); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); } { USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); SET_H_GPR (FLD (f_r1), opval); - written |= (1 << 5); + written |= (1 << 4); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); } } } else { +{ { BI opval = 1; SET_H_SYS_SR_CY (opval); - written |= (1 << 6); + written |= (1 << 5); CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); } -} - { - BI opval = 0; - SET_H_SYS_SR_OV (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); - } -if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +if (GET_H_SYS_SR_OVE ()) { or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); } } +} abuf->written = written; return vpc; @@ -1664,11 +1725,6 @@ SEM_FN_NAME (or1k32bf,l_muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); } { - USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); - SET_H_SYS_SR_CY (opval); - CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); - } - { USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16))); SET_H_GPR (FLD (f_r1), opval); CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); @@ -2273,10 +2329,13 @@ SEM_FN_NAME (or1k32bf,l_mac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI tmp_prod; +{ + DI tmp_prod; + DI tmp_mac; DI tmp_result; - tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); - tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod)); + tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = ADDDI (tmp_prod, tmp_mac); { SI opval = SUBWORDDISI (tmp_result, 0); SET_H_MAC_MACHI (opval); @@ -2287,6 +2346,103 @@ SEM_FN_NAME (or1k32bf,l_mac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SET_H_MAC_MACLO (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } + { + BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); + SET_H_SYS_SR_OV (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} +} + + return vpc; +#undef FLD +} + +/* l-maci: l.maci $rA,${simm16} */ + +static SEM_PC +SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_lwz.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + DI tmp_prod; + DI tmp_mac; + DI tmp_result; + tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (FLD (f_simm16))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = ADDDI (tmp_mac, tmp_prod); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } + { + BI opval = ADDOFDI (tmp_prod, tmp_mac, 0); + SET_H_SYS_SR_OV (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} +} + + return vpc; +#undef FLD +} + +/* l-macu: l.macu $rA,$rB */ + +static SEM_PC +SEM_FN_NAME (or1k32bf,l_macu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_l_sll.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +{ +{ + DI tmp_prod; + DI tmp_mac; + DI tmp_result; + tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = ADDDI (tmp_prod, tmp_mac); + { + SI opval = SUBWORDDISI (tmp_result, 0); + SET_H_MAC_MACHI (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval); + } + { + SI opval = SUBWORDDISI (tmp_result, 1); + SET_H_MAC_MACLO (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); + } + { + BI opval = ADDCFDI (tmp_prod, tmp_mac, 0); + SET_H_SYS_SR_CY (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} } return vpc; @@ -2305,10 +2461,13 @@ SEM_FN_NAME (or1k32bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI tmp_prod; +{ + DI tmp_prod; + DI tmp_mac; DI tmp_result; - tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3))); - tmp_result = SUBDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod)); + tmp_prod = MULDI (EXTSIDI (GET_H_GPR (FLD (f_r2))), EXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = SUBDI (tmp_mac, tmp_prod); { SI opval = SUBWORDDISI (tmp_result, 0); SET_H_MAC_MACHI (opval); @@ -2319,28 +2478,40 @@ SEM_FN_NAME (or1k32bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SET_H_MAC_MACLO (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } + { + BI opval = SUBOFDI (tmp_mac, tmp_result, 0); + SET_H_SYS_SR_OV (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} } return vpc; #undef FLD } -/* l-maci: l.maci $rA,${simm16} */ +/* l-msbu: l.msbu $rA,$rB */ static SEM_PC -SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +SEM_FN_NAME (or1k32bf,l_msbu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_l_lwz.f +#define FLD(f) abuf->fields.sfmt_l_sll.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - SI tmp_prod; +{ + DI tmp_prod; + DI tmp_mac; DI tmp_result; - tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2))); - tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod)); + tmp_prod = MULDI (ZEXTSIDI (GET_H_GPR (FLD (f_r2))), ZEXTSIDI (GET_H_GPR (FLD (f_r3)))); + tmp_mac = JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()); + tmp_result = SUBDI (tmp_mac, tmp_prod); { SI opval = SUBWORDDISI (tmp_result, 0); SET_H_MAC_MACHI (opval); @@ -2351,6 +2522,15 @@ SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SET_H_MAC_MACLO (opval); CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval); } + { + BI opval = SUBCFDI (tmp_mac, tmp_result, 0); + SET_H_SYS_SR_CY (opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval); + } +} +if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) { +or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE); +} } return vpc; @@ -2814,6 +2994,7 @@ static const struct sem_fn_desc sem_fns[] = { { OR1K32BF_INSN_X_CHAIN, SEM_FN_NAME (or1k32bf,x_chain) }, { OR1K32BF_INSN_X_BEGIN, SEM_FN_NAME (or1k32bf,x_begin) }, { OR1K32BF_INSN_L_J, SEM_FN_NAME (or1k32bf,l_j) }, + { OR1K32BF_INSN_L_ADRP, SEM_FN_NAME (or1k32bf,l_adrp) }, { OR1K32BF_INSN_L_JAL, SEM_FN_NAME (or1k32bf,l_jal) }, { OR1K32BF_INSN_L_JR, SEM_FN_NAME (or1k32bf,l_jr) }, { OR1K32BF_INSN_L_JALR, SEM_FN_NAME (or1k32bf,l_jalr) }, @@ -2856,7 +3037,9 @@ static const struct sem_fn_desc sem_fns[] = { { OR1K32BF_INSN_L_SUB, SEM_FN_NAME (or1k32bf,l_sub) }, { OR1K32BF_INSN_L_ADDC, SEM_FN_NAME (or1k32bf,l_addc) }, { OR1K32BF_INSN_L_MUL, SEM_FN_NAME (or1k32bf,l_mul) }, + { OR1K32BF_INSN_L_MULD, SEM_FN_NAME (or1k32bf,l_muld) }, { OR1K32BF_INSN_L_MULU, SEM_FN_NAME (or1k32bf,l_mulu) }, + { OR1K32BF_INSN_L_MULDU, SEM_FN_NAME (or1k32bf,l_muldu) }, { OR1K32BF_INSN_L_DIV, SEM_FN_NAME (or1k32bf,l_div) }, { OR1K32BF_INSN_L_DIVU, SEM_FN_NAME (or1k32bf,l_divu) }, { OR1K32BF_INSN_L_FF1, SEM_FN_NAME (or1k32bf,l_ff1) }, @@ -2895,8 +3078,10 @@ static const struct sem_fn_desc sem_fns[] = { { OR1K32BF_INSN_L_SFNE, SEM_FN_NAME (or1k32bf,l_sfne) }, { OR1K32BF_INSN_L_SFNEI, SEM_FN_NAME (or1k32bf,l_sfnei) }, { OR1K32BF_INSN_L_MAC, SEM_FN_NAME (or1k32bf,l_mac) }, - { OR1K32BF_INSN_L_MSB, SEM_FN_NAME (or1k32bf,l_msb) }, { OR1K32BF_INSN_L_MACI, SEM_FN_NAME (or1k32bf,l_maci) }, + { OR1K32BF_INSN_L_MACU, SEM_FN_NAME (or1k32bf,l_macu) }, + { OR1K32BF_INSN_L_MSB, SEM_FN_NAME (or1k32bf,l_msb) }, + { OR1K32BF_INSN_L_MSBU, SEM_FN_NAME (or1k32bf,l_msbu) }, { OR1K32BF_INSN_L_CUST1, SEM_FN_NAME (or1k32bf,l_cust1) }, { OR1K32BF_INSN_L_CUST2, SEM_FN_NAME (or1k32bf,l_cust2) }, { OR1K32BF_INSN_L_CUST3, SEM_FN_NAME (or1k32bf,l_cust3) }, |