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-rw-r--r--sim/moxie/interp.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 2be561c..dd87648 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -460,6 +460,7 @@ sim_resume (sd, step, siggnal)
TRACE("gsr");
cpu.asregs.regs[a] = cpu.asregs.sregs[v];
}
+ break;
case 0x03: /* ssr */
{
int a = (inst >> 8) & 0xf;
@@ -467,6 +468,7 @@ sim_resume (sd, step, siggnal)
TRACE("ssr");
cpu.asregs.sregs[v] = cpu.asregs.regs[a];
}
+ break;
default:
TRACE("SIGILL2");
cpu.asregs.exception = SIGILL;