diff options
Diffstat (limited to 'sim/mn10300')
| -rw-r--r-- | sim/mn10300/ChangeLog | 74 | ||||
| -rw-r--r-- | sim/mn10300/Makefile.in | 2 | ||||
| -rw-r--r-- | sim/mn10300/am33.igen | 8683 | ||||
| -rw-r--r-- | sim/mn10300/mn10300.igen | 808 | ||||
| -rw-r--r-- | sim/mn10300/mn10300_sim.h | 7 |
5 files changed, 9574 insertions, 0 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index cc37c7b..23f3ca6 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -59,6 +59,15 @@ Tue Feb 16 23:57:17 1999 Jeffrey A Law (law@cygnus.com) generation. (mn103int_finish): Install it as ioctl handler. * dv-mn103tim.c: Support timer 6 specially. Endianness fixes. +Wed Oct 14 12:11:05 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Allow autoincrement stores using the same register + for source and destination operands. + +Mon Aug 31 10:19:55 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Reverse HI/LO outputs of 4 operand "mul" and "mulu". + Fri Aug 28 14:40:49 1998 Joyce Janczyn <janczyn@cygnus.com> * interp.c (sim_open): Check for invalid --board option, fix @@ -73,6 +82,21 @@ Mon Aug 24 11:50:09 1998 Joyce Janczyn <janczyn@cygnus.com> * sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA. +Wed Aug 12 12:36:07 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Handle case where first DSP operation modifies a + register used in the second DSP operation correctly. + +Tue Jul 28 10:10:25 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Detect cases where two operands must not match for + DSP instructions too. + +Mon Jul 27 12:04:17 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Detect cases where two operands must not match in + non-DSP instructions. + Fri Jul 24 18:15:21 1998 Joyce Janczyn <janczyn@cygnus.com> * op_utils.c (do_syscall): Rewrite to use common/syscall.c. @@ -83,21 +107,71 @@ Fri Jul 24 18:15:21 1998 Joyce Janczyn <janczyn@cygnus.com> * mn10300.igen: Change C++ style comments to C style comments. Check for divide by zero in div and divu ops. +Fri Jul 24 12:49:28 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen (translate_xreg): New function. Use it as needed. + +Thu Jul 23 10:05:28 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Add some missing instructions. + + * am33.igen: Autoincrement loads/store fixes. + +Tue Jul 21 09:48:14 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Add mov_lCC DSP instructions. + + * am33.igen: Add most am33 DSP instructions. + Thu Jul 9 10:06:55 1998 Jeffrey A Law (law@cygnus.com) * mn10300.igen: Fix Z bit for addc and subc instructions. Minor fixes in multiply/divide patterns. + * am33.igen: Add missing mul[u] imm32,Rn. Fix condition code + handling for many instructions. Fix sign extension for some + 24bit immediates. + + * am33.igen: Fix Z bit for remaining addc/subc instructions. + Do not sign extend immediate for mov imm,XRn. + More random mul, mac & div fixes. + Remove some unused variables. + Sign extend 24bit displacement in memory addresses. + + * am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn. Various + fixes to 2 register multiply, divide and mac instructions. Set + Z,N correctly for sat16. Sign extend 24 bit immediate for add, + and sub instructions. + + * am33.igen: Add remaining non-DSP instructions. + +Wed Jul 8 16:29:12 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen (translate_rreg): New function. Use it as appropriate. + + * am33.igen: More am33 instructions. Fix "div". + +Mon Jul 6 15:39:22 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.igen: Add am33 support. + + * Makefile.in: Use multi-sim to support both a mn10300 and am33 + simulator. + + * am33.igen: Add many more am33 instructions. Wed Jul 1 17:07:09 1998 Jeffrey A Law (law@cygnus.com) * mn10300_sim.h (FETCH24): Define. + * mn10300_sim.h: Add defines for some registers found on the AM33. + * am33.igen: New file with some am33 support. Tue Jun 30 11:23:20 1998 Jeffrey A Law (law@cygnus.com) * mn10300_sim.h: Include bfd.h (struct state): Add more room for processor specific registers. + (REG_E0): Define. Thu Jun 25 10:12:03 1998 Joyce Janczyn <janczyn@cygnus.com> diff --git a/sim/mn10300/Makefile.in b/sim/mn10300/Makefile.in index 612576c..4d02e5b 100644 --- a/sim/mn10300/Makefile.in +++ b/sim/mn10300/Makefile.in @@ -113,6 +113,8 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen ../igen/igen \ $(IGEN_TRACE) \ -G gen-direct-access \ + -M mn10300,am33 -G gen-multi-sim=am33 \ + -I $(srcdir) \ -i $(IGEN_INSN) \ -o $(IGEN_DC) \ -x \ diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen new file mode 100644 index 0000000..31bbc73 --- /dev/null +++ b/sim/mn10300/am33.igen @@ -0,0 +1,8683 @@ +// Helper: +// +// Given an extended register number, translate it into an index into the +// register array. This is necessary as the upper 8 extended registers are +// actually synonyms for the d0-d3/a0-a3 registers. +// +// + +:function:::int:translate_rreg:int rreg +{ + + /* The higher register numbers actually correspond to the + basic machine's address and data registers. */ + if (rreg > 7 && rreg < 12) + return REG_A0 + rreg - 8; + else if (rreg > 11 && rreg < 16) + return REG_D0 + rreg - 12; + else + return REG_E0 + rreg; +} + +:function:::int:translate_xreg:int xreg +{ + switch (xreg) + { + case 0: + return REG_SP; + case 1: + return REG_MDRQ; + case 2: + return REG_MCRH; + case 3: + return REG_MCRL; + case 4: + return REG_MCVF; + default: + abort (); + } +} + +// 1111 0000 0010 00An; mov USP,An +8.0xf0+4.0x2,00,2.AN0:D0m:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[REG_USP]; +} + + +// 1111 0000 0010 01An; mov SSP,An +8.0xf0+4.0x2,01,2.AN0:D0n:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[REG_SSP]; +} + + +// 1111 0000 0010 10An; mov MSP,An +8.0xf0+4.0x2,10,2.AN0:D0o:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[REG_MSP]; +} + + +// 1111 0000 0010 11An; mov PC,An +8.0xf0+4.0x2,11,2.AN0:D0p:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = PC; +} + + +// 1111 0000 0011 Am00; mov Am,USP +8.0xf0+4.0x3,2.AM1,00:D0q:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_USP] = State.regs[REG_A0 + AM1]; +} + +// 1111 0000 0011 Am01; mov Am,SSP +8.0xf0+4.0x3,2.AM1,01:D0r:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_SSP] = State.regs[REG_A0 + AM1]; +} + +// 1111 0000 0011 Am10; mov Am,MSP +8.0xf0+4.0x3,2.AM1,10:D0s:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_MSP] = State.regs[REG_A0 + AM1]; +} + + +// 1111 0000 1110 imm4; syscall +8.0xf0+4.0xe,IMM4:D0t:::syscall +"syscall" +*am33 +{ + unsigned int sp, next_pc; + + PC = cia; + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 2; + store_word (sp - 4, next_pc); + store_word (sp - 8, PSW); + State.regs[REG_PC] = 0x40000000 + IMM4 * 8; + nia = PC; +} + + +// 1111 0010 1110 11Dn; mov EPSW,Dn +8.0xf2+4.0xe,11,2.DN0:D0u:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_D0 + DN0] = PSW; +} + + +// 1111 0010 1111 Dm01; mov Dm,EPSW +8.0xf2+4.0xf,2.DM1,01:D0v:::mov +"mov" +*am33 +{ + PC = cia; + PSW = State.regs[REG_D0 + DM1]; +} + +// 1111 0101 00Am Rn; mov Am,Rn +8.0xf5+00,2.AM1,4.RN0:D0w:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RN0); + + PC = cia; + State.regs[destreg] = State.regs[REG_A0 + AM1]; +} + +// 1111 0101 01Dm Rn; mov Dm,Rn +8.0xf5+01,2.DM1,4.RN0:D0x:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RN0); + + PC = cia; + State.regs[destreg] = State.regs[REG_D0 + DM1]; +} + +// 1111 0101 10Rm An; mov Rm,An +8.0xf5+10,4.RM1,2.AN0:D0y:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RM1); + + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[destreg]; +} + +// 1111 0101 11Rm Dn; mov Rm,Dn +8.0xf5+11,4.RM1,2.DN0:D0z:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RM1); + + PC = cia; + State.regs[REG_D0 + DN0] = State.regs[destreg]; +} + + +// 1111 1000 1100 1110 regs....; movm (USP),regs +8.0xf8+8.0xce+8.REGS:D1a:::movm +"movm" +*am33 +{ + unsigned long usp = State.regs[REG_USP]; + unsigned long mask; + + PC = cia; + mask = REGS; + + if (mask & 0x8) + { + usp += 4; + State.regs[REG_LAR] = load_word (usp); + usp += 4; + State.regs[REG_LIR] = load_word (usp); + usp += 4; + State.regs[REG_MDR] = load_word (usp); + usp += 4; + State.regs[REG_A0 + 1] = load_word (usp); + usp += 4; + State.regs[REG_A0] = load_word (usp); + usp += 4; + State.regs[REG_D0 + 1] = load_word (usp); + usp += 4; + State.regs[REG_D0] = load_word (usp); + usp += 4; + } + + if (mask & 0x10) + { + State.regs[REG_A0 + 3] = load_word (usp); + usp += 4; + } + + if (mask & 0x20) + { + State.regs[REG_A0 + 2] = load_word (usp); + usp += 4; + } + + if (mask & 0x40) + { + State.regs[REG_D0 + 3] = load_word (usp); + usp += 4; + } + + if (mask & 0x80) + { + State.regs[REG_D0 + 2] = load_word (usp); + usp += 4; + } + + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + if (mask & 0x1) + { + /* Need to restore MDQR, MCRH, MCRL, and MCVF */ + usp += 16; + State.regs[REG_E0 + 1] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 0] = load_word (usp); + usp += 4; + } + + if (mask & 0x2) + { + State.regs[REG_E0 + 7] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 6] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 5] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 4] = load_word (usp); + usp += 4; + } + + if (mask & 0x4) + { + State.regs[REG_E0 + 3] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 2] = load_word (usp); + usp += 4; + } + } + + /* And make sure to update the stack pointer. */ + State.regs[REG_USP] = usp; +} + +// 1111 1000 1100 1111 regs....; movm (USP),regs +8.0xf8+8.0xcf+8.REGS:D1b:::movm +"movm" +*am33 +{ + unsigned long usp = State.regs[REG_USP]; + unsigned long mask; + + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + if (mask & 0x4) + { + usp -= 4; + store_word (usp, State.regs[REG_E0 + 2]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 3]); + } + + if (mask & 0x2) + { + usp -= 4; + store_word (usp, State.regs[REG_E0 + 4]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 5]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 6]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 7]); + } + + if (mask & 0x1) + { + usp -= 4; + store_word (usp, State.regs[REG_E0 + 0]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 1]); + usp -= 16; + /* Need to save MDQR, MCRH, MCRL, and MCVF */ + } + } + + if (mask & 0x80) + { + usp -= 4; + store_word (usp, State.regs[REG_D0 + 2]); + } + + if (mask & 0x40) + { + usp -= 4; + store_word (usp, State.regs[REG_D0 + 3]); + } + + if (mask & 0x20) + { + usp -= 4; + store_word (usp, State.regs[REG_A0 + 2]); + } + + if (mask & 0x10) + { + usp -= 4; + store_word (usp, State.regs[REG_A0 + 3]); + } + + if (mask & 0x8) + { + usp -= 4; + store_word (usp, State.regs[REG_D0]); + usp -= 4; + store_word (usp, State.regs[REG_D0 + 1]); + usp -= 4; + store_word (usp, State.regs[REG_A0]); + usp -= 4; + store_word (usp, State.regs[REG_A0 + 1]); + usp -= 4; + store_word (usp, State.regs[REG_MDR]); + usp -= 4; + store_word (usp, State.regs[REG_LIR]); + usp -= 4; + store_word (usp, State.regs[REG_LAR]); + usp -= 4; + } + + /* And make sure to update the stack pointer. */ + State.regs[REG_USP] = usp; +} + +// 1111 1100 1111 1100 imm32...; and imm32,EPSW +8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and +"and" +*am33 +{ + PC = cia; + PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1100 1111 1101 imm32...; or imm32,EPSW +8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or +"or" +*am33 +{ + PC = cia; + PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn) +8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = State.regs[srcreg]; +} + +// 1111 1001 0001 1000 Rn Rn; ext Rn +8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + if (State.regs[srcreg] & 0x80000000) + State.regs[REG_MDR] = -1; + else + State.regs[REG_MDR] = 0; +} + +// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn +8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb +"extb" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND8 (State.regs[srcreg]); +} + +// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn +8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu +"extbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = State.regs[srcreg] & 0xff; +} + +// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn +8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth +"exth" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND16 (State.regs[srcreg]); +} + +// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn +8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu +"exthu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = State.regs[srcreg] & 0xffff; +} + +// 1111 1001 0110 1000 Rn Rn; clr Rn +8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr +"clr" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = 0; + PSW |= PSW_Z; + PSW &= ~(PSW_V | PSW_C | PSW_N); +} + +// 1111 1001 0111 1000 Rm Rn; add Rm,Rn +8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add +"add" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + genericAdd (State.regs[srcreg], dstreg); +} + +// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn +8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc +"addc" +*am33 +{ + int srcreg, dstreg; + int z, c, n, v; + unsigned long reg1, reg2, sum; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + reg1 = State.regs[srcreg]; + reg2 = State.regs[dstreg]; + sum = reg1 + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < reg1) || (sum < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn +8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub +"sub" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + genericSub (State.regs[srcreg], dstreg); +} + +// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn +8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc +"subc" +*am33 +{ + int srcreg, dstreg; + int z, c, n, v; + unsigned long reg1, reg2, difference; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + reg1 = State.regs[srcreg]; + reg2 = State.regs[dstreg]; + difference = reg2 - reg1 - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1001 1011 1000 Rn Rn; inc Rn +8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc +"inc" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (1, dstreg); +} + +// 1111 1001 1101 1000 Rn Rn; inc Rn +8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4 +"inc4" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] += 4; +} + +// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn +8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp +"cmp" +*am33 +{ + int srcreg1, srcreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RN0); + srcreg2 = translate_rreg (SD_, RM2); + genericCmp (State.regs[srcreg2], State.regs[srcreg1]); +} + +// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn +8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov +"mov" +*am33 +{ + int dstreg, srcreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + srcreg = translate_xreg (SD_, XRM2); + + State.regs[dstreg] = State.regs[srcreg]; +} + +// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn +8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = State.regs[srcreg]; +} + +// 1111 1001 0000 1001 Rm Rn; and Rm,Rn +8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and +"and" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0001 1001 Rm Rn; or Rm,Rn +8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or +"or" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn +8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor +"xor" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0011 1001 Rn Rn; not Rn +8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not +"not" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = ~State.regs[dstreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn +8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr +"asr" +*am33 +{ + int srcreg, dstreg; + long temp; + int c, z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= State.regs[srcreg]; + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn +8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr +"lsr" +*am33 +{ + int srcreg, dstreg; + int z, n, c; + + PC = cia; + + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn +8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl +"asl" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0111 1001 Rn Rn; asl2 Rn +8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2 +"asl2" +*am33 +{ + int dstreg; + int n, z; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= 2; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1000 1001 Rn Rn; ror Rn +8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror +"ror" +*am33 +{ + int dstreg; + int c, n, z; + unsigned long value; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[dstreg]; + c = (value & 0x1); + + value >>= 1; + value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; + State.regs[dstreg] = value; + z = (value == 0); + n = (value & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 1001 1001 Rn Rn; rol Rn +8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol +"rol" +*am33 +{ + int dstreg; + int c, n, z; + unsigned long value; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[dstreg]; + c = (value & 0x80000000) ? 1 : 0; + + value <<= 1; + value |= ((PSW & PSW_C) != 0); + State.regs[dstreg] = value; + z = (value == 0); + n = (value & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn +8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul +"mul" +*am33 +{ + int srcreg, dstreg; + unsigned long long temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)State.regs[srcreg]); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn +8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu +"mulu" +*am33 +{ + int srcreg, dstreg; + unsigned long long temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64)State.regs[srcreg]); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1100 1001 Rm Rn; div Rm,Rn +8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div +"div" +*am33 +{ + int srcreg, dstreg; + long long temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[REG_MDR]; + temp <<= 32; + temp |= State.regs[dstreg]; + State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg]; + temp /= (signed32)State.regs[srcreg]; + State.regs[dstreg] = temp & 0xffffffff; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn +8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu +"divu" +*am33 +{ + int srcreg, dstreg; + unsigned long long temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[REG_MDR]; + temp <<= 32; + temp |= State.regs[dstreg]; + State.regs[REG_MDR] = temp % State.regs[srcreg]; + temp /= State.regs[srcreg]; + State.regs[dstreg] = temp & 0xffffffff; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + + +// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn +8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); +} + +// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn) +8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); +} + +// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn +8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg]); +} + +// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn) +8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg], State.regs[srcreg]); +} + +// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn +8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); +} + +// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn) +8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); +} + +// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn +8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += 4; +} + +// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+) +8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += 4; +} + +// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn +8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP]); +} + +// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp) +8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP], State.regs[srcreg]); +} + +// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn +8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP]); +} + +// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp) +8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP], State.regs[srcreg]); +} + +// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn +8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP]); +} + +// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp) +8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP], State.regs[srcreg]); +} + +// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn +8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[srcreg] += 2; +} + +// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+) +8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += 2; +} + + +// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn +8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac +"mac" +*am33 +{ + int srcreg1, srcreg2; + long long temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[srcreg2] + * (signed64)(signed32)State.regs[srcreg1]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn +8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu +"macu" +*am33 +{ + int srcreg1, srcreg2; + unsigned long long temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[srcreg2] + * (unsigned64)State.regs[srcreg1]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn +8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb +"macb" +*am33 +{ + int srcreg1, srcreg2; + long temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff) + * (signed32)(signed8)(State.regs[srcreg1] & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn +8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu +"macbu" +*am33 +{ + int srcreg1, srcreg2; + long long temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xff) + * (unsigned32)(State.regs[srcreg1] & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn +8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach +"mach" +*am33 +{ + int srcreg1, srcreg2; + long long temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff) + * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff)); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn +8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu +"machu" +*am33 +{ + int srcreg1, srcreg2; + long long temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned64)(State.regs[srcreg2] & 0xffff) + * (unsigned64)(State.regs[srcreg1] & 0xffff)); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn +8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach +"dmach" +*am33 +{ + int srcreg1, srcreg2; + long temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn +8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu +"dmachu" +*am33 +{ + int srcreg1, srcreg2; + unsigned long temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn +8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh +"dmulh" +*am33 +{ + int srcreg, dstreg; + long temp; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg] & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn +8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu +"dmachu" +*am33 +{ + int srcreg, dstreg; + unsigned long temp; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned32)(State.regs[dstreg] & 0xffff) + * (unsigned32)(State.regs[srcreg] & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg] >>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn +8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16 +"sat16" +*am33 +{ + int srcreg, dstreg; + int value, z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[srcreg]; + + if (value >= 0x7fff) + State.regs[dstreg] = 0x7fff; + else if (value <= 0xffff8000) + State.regs[dstreg] = 0xffff8000; + else + State.regs[dstreg] = value; + + n = (State.regs[dstreg] & 0x8000) != 0; + z = (State.regs[dstreg] == 0); + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn +8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste +"mcste" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + PSW &= ~(PSW_V | PSW_C); + PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); + + /* 32bit saturation. */ + if (State.regs[srcreg] == 0x20) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffff) + State.regs[dstreg] = 0x7fffffff; + else if (tmp < 0xffffffff80000000LL) + State.regs[dstreg] = 0x80000000; + else + State.regs[dstreg] = tmp; + } + /* 16bit saturation */ + else if (State.regs[srcreg] == 0x10) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fff) + State.regs[dstreg] = 0x7fff; + else if (tmp < 0xffffffffffff8000LL) + State.regs[dstreg] = 0x8000; + else + State.regs[dstreg] = tmp; + } + /* 8 bit saturation */ + else if (State.regs[srcreg] == 0x8) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7f) + State.regs[dstreg] = 0x7f; + else if (tmp < 0xffffffffffffff80LL) + State.regs[dstreg] = 0x80; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (State.regs[srcreg] == 0x9) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x80) + State.regs[dstreg] = 0x80; + else if (tmp < 0xffffffffffffff81LL) + State.regs[dstreg] = 0x81; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (State.regs[srcreg] == 0x30) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffffffffLL) + tmp = 0x7fffffffffffLL; + else if (tmp < 0xffff800000000000LL) + tmp = 0xffff800000000000LL; + + tmp >>= 16; + State.regs[dstreg] = tmp; + } +} + +// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn +8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap +"swap" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24) + | (((State.regs[srcreg] >> 8) & 0xff) << 16) + | (((State.regs[srcreg] >> 16) & 0xff) << 8) + | ((State.regs[srcreg] >> 24) & 0xff)); +} + +// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn +8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph +"swaph" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8) + | ((State.regs[srcreg] >> 8) & 0xff) + | (((State.regs[srcreg] >> 16) & 0xff) << 24) + | (((State.regs[srcreg] >> 24) & 0xff) << 16)); +} + +// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn +8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw +"swhw" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16) + | ((State.regs[srcreg] >> 16) & 0xffff)); +} + +// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn +8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch +"bsch" +*am33 +{ + int temp, c, i; + int srcreg, dstreg; + int start; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[srcreg]; + start = (State.regs[dstreg] & 0x1f) - 1; + if (start == -1) + start = 31; + + for (i = start; i >= 0; i--) + { + if (temp & (1 << i)) + { + c = 1; + State.regs[dstreg] = i; + break; + } + } + + if (i < 0) + { + c = 0; + State.regs[dstreg] = 0; + } + PSW &= ~(PSW_C); + PSW |= (c ? PSW_C : 0); +} + + +// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn +8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND8 (IMM8); +} + +// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn +8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu +"movu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = IMM8 & 0xff; +} + +// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn +8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add +"add" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (EXTEND8 (IMM8), dstreg); +} + +// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn +8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc +"addc" +*am33 +{ + int dstreg, imm; + int z, c, n, v; + unsigned long reg1, reg2, sum; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND8 (IMM8); + reg2 = State.regs[dstreg]; + sum = imm + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < imm) || (sum < reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn +8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub +"sub" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + genericSub (EXTEND8 (IMM8), dstreg); +} + +// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn +8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc +"subc" +*am33 +{ + int imm, dstreg; + int z, c, n, v; + unsigned long reg1, reg2, difference; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND8 (IMM8); + reg2 = State.regs[dstreg]; + difference = reg2 - imm - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (imm > reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn +8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp +"cmp" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericCmp (EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn +8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = IMM8; +} + +// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn +8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and +"and" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn +8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or +"or" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn +8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor +"xor" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn +8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr +"asr" +*am33 +{ + int dstreg; + long temp; + int c, z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= (IMM8 & 0xff); + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn +8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr +"lsr" +*am33 +{ + int dstreg; + int z, n, c; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn +8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl +"asl" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn +8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul +"mul" +*am33 +{ + int dstreg; + unsigned long long temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)EXTEND8 (IMM8)); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn +8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu +"mulu" +*am33 +{ + int dstreg; + unsigned long long temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64)(IMM8 & 0xff)); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn +8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst +"btst" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + genericBtst(IMM8, State.regs[srcreg]); +} + +// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn +8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8)); +} + +// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn) +8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov +"mov" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn +8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu +"movbu" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8)); +} + +// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn) +8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu +"movbu" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn +8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu +"movhu" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8)); +} + +// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn) +8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu +"movhu" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn +8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND8 (IMM8); +} + +// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+) +8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov +"mov" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += EXTEND8 (IMM8); +} + + +// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn +8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov +"mov" +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8)); +} + +// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn) +8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov +"mov" +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn +8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu +"movbu" +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8)); +} + +// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn) +8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu +"movbu" +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn +8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu +"movhu" +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8)); +} + +// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp) +8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu +"movhu" +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn +8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[srcreg] += EXTEND8 (IMM8); +} + +// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+) +8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu +"movhu" +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += EXTEND8 (IMM8); +} + + +// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn +8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac +"mac" +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)(signed32)EXTEND8 (IMM8) + * (signed64)(signed32)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn +8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu +"macu" +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (IMM8) + * (unsigned64)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn +8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb +"macb" +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)(signed8)EXTEND8 (IMM8) + * (signed64)(signed8)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn +8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu +"macbu" +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (IMM8) + * (unsigned64)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn +8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach +"mach" +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)(signed16)EXTEND8 (IMM8) + * (signed64)(signed16)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn +8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu +"machu" +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (IMM8) + * (unsigned64)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn +8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste +"mcste" +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + PSW &= ~(PSW_V | PSW_C); + PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); + + /* 32bit saturation. */ + if (IMM8 == 0x20) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffff) + State.regs[dstreg] = 0x7fffffff; + else if (tmp < 0xffffffff80000000LL) + State.regs[dstreg] = 0x80000000; + else + State.regs[dstreg] = tmp; + } + /* 16bit saturation */ + else if (IMM8 == 0x10) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fff) + State.regs[dstreg] = 0x7fff; + else if (tmp < 0xffffffffffff8000LL) + State.regs[dstreg] = 0x8000; + else + State.regs[dstreg] = tmp; + } + /* 8 bit saturation */ + else if (IMM8 == 0x8) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7f) + State.regs[dstreg] = 0x7f; + else if (tmp < 0xffffffffffffff80LL) + State.regs[dstreg] = 0x80; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (IMM8 == 0x9) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x80) + State.regs[dstreg] = 0x80; + else if (tmp < 0xffffffffffffff81LL) + State.regs[dstreg] = 0x81; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (IMM8 == 0x30) + { + long long tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffffffffLL) + tmp = 0x7fffffffffffLL; + else if (tmp < 0xffff800000000000LL) + tmp = 0xffff800000000000LL; + + tmp >>= 16; + State.regs[dstreg] = tmp; + } +} + +// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd +8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add +"add" +*am33 +{ + int z, c, n, v; + unsigned long sum, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + sum = source1 + source2; + State.regs[dstreg] = sum; + + z = (sum == 0); + n = (sum & 0x80000000); + c = (sum < source1) || (sum < source2); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd +8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc +"addc" +*am33 +{ + int z, c, n, v; + unsigned long sum, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + sum = source1 + source2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < source1) || (sum < source2); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd +8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub +"sub" +*am33 +{ + int z, c, n, v; + unsigned long difference, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + difference = source2 - source1; + State.regs[dstreg] = difference; + + z = (difference == 0); + n = (difference & 0x80000000); + c = (source1 > source1); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd +8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc +"subc" +*am33 +{ + int z, c, n, v; + unsigned long difference, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + difference = source2 - source1 - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (source1 > source2); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd +8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and +"and" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd +8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or +"or" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd +8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor +"xor" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd +8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr +"asr" +*am33 +{ + int z, c, n; + long temp; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = State.regs[srcreg2]; + c = temp & 1; + temp >>= State.regs[srcreg1]; + State.regs[dstreg] = temp; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd +8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr +"lsr" +*am33 +{ + int z, c, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + c = State.regs[srcreg2] & 1; + State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd +8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl +"asl" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2 +8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul +"mul" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed long long temp; + int n, z; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((signed64)(signed32)State.regs[srcreg1] + * (signed64)(signed32)State.regs[srcreg2]); + State.regs[dstreg2] = temp & 0xffffffff; + State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; + + z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); + n = (State.regs[dstreg1] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu +"mulu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed long long temp; + int n, z; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((unsigned64)State.regs[srcreg1] + * (unsigned64)State.regs[srcreg2]); + State.regs[dstreg2] = temp & 0xffffffff; + State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; + + z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); + n = (State.regs[dstreg1] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn +8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (IMM8); +} + +// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8) +8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (IMM8, State.regs[srcreg]); +} + +// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn +8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (IMM8); +} + +// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8) +8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (IMM8, State.regs[srcreg]); +} + +// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn +8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (IMM8); +} + +// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8) +8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (IMM8, State.regs[srcreg]); +} + +// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn +8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov +"mov" +*am33 +{ + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM0); + srcreg1 = translate_rreg (SD_, RI0); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]); +} + +// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm) +8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov +"mov" +*am33 +{ + int srcreg, dstreg1, dstreg2; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg1 = translate_rreg (SD_, RI0); + dstreg2 = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); +} + +// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn +8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu +"movbu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM0); + srcreg1 = translate_rreg (SD_, RI0); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]); +} + +// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm) +8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg1, dstreg2; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg1 = translate_rreg (SD_, RI0); + dstreg2 = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); +} + +// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn +8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu +"movhu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM0); + srcreg1 = translate_rreg (SD_, RI0); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]); +} + +// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm) +8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg1, dstreg2; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg1 = translate_rreg (SD_, RI0); + dstreg2 = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); +} + +// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac +"mac" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed long long temp; + unsigned long sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((signed64)(signed32)State.regs[srcreg1] + * (signed64)(signed32)State.regs[srcreg2]); + + sum = State.regs[dstreg2] + (temp & 0xffffffff); + c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); + State.regs[dstreg2] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[dstreg1] + temp + c; + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= (( v ? PSW_V : 0)); + } +} + +// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu +"macu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed long long temp; + unsigned long sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((unsigned64)State.regs[srcreg1] + * (unsigned64)State.regs[srcreg2]); + + sum = State.regs[dstreg2] + (temp & 0xffffffff); + c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); + State.regs[dstreg2] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[dstreg1] + temp + c; + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= (( v ? PSW_V : 0)); + } +} + +// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1 +8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb +"macb" +*am33 +{ + int srcreg1, srcreg2, dstreg; + long temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((signed32)(State.regs[srcreg2] & 0xff) + * (signed32)(State.regs[srcreg1] & 0xff)); + sum = State.regs[dstreg] + temp; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1 +8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu +"macbu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + long temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xff) + * (unsigned32)(State.regs[srcreg1] & 0xff)); + sum = State.regs[dstreg] + temp; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach +"mach" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long long temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD0); + + temp = ((signed32)(State.regs[srcreg2] & 0xffff) + * (signed32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] += (temp & 0xffffffff); + sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu +"machu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long long temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] += (temp & 0xffffffff); + sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1 +8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach +"dmach" +*am33 +{ + int srcreg1, srcreg2, dstreg; + long temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((signed32)(State.regs[srcreg2] & 0xffff) + * (signed32)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[dstreg]; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1 +8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu +"dmachu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + long temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[dstreg]; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh +"dmulh" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed long long temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((signed32)(State.regs[srcreg1] & 0xffff) + * (signed32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] = temp; + temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)((State.regs[srcreg1] >>16) & 0xffff)); + State.regs[dstreg1] = temp; +} + +// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu +"dmulhu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed long long temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((unsigned32)(State.regs[srcreg1] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] = temp; + temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff)); + State.regs[dstreg1] = temp; +} + +// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn +8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24 +"sat24" +*am33 +{ + int srcreg, dstreg; + int value, n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[srcreg]; + + if (value >= 0x7fffff) + State.regs[dstreg] = 0x7fffff; + else if (value <= 0xff800000) + State.regs[dstreg] = 0xff800000; + else + State.regs[dstreg] = value; + + n = (State.regs[dstreg] & 0x800000) != 0; + z = (State.regs[dstreg] == 0); + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1 +8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch +"bsch" +*am33 +{ + int temp, c, i; + int srcreg1, srcreg2, dstreg; + int start; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = State.regs[srcreg1]; + start = (State.regs[srcreg2] & 0x1f) - 1; + if (start == -1) + start = 31; + + for (i = start; i >= 0; i--) + { + if (temp & (1 << i)) + { + c = 1; + State.regs[dstreg] = i; + break; + } + } + + if (i < 0) + { + c = 0; + State.regs[dstreg] = 0; + } + PSW &= ~(PSW_C); + PSW |= (c ? PSW_C : 0); +} + +// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn +8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn +8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu +"movu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; +} + +// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn +8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add +"add" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); +} + +// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn +8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc +"addc" +*am33 +{ + int dstreg, z, n, c, v; + unsigned long sum, imm, reg2; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); + reg2 = State.regs[dstreg]; + sum = imm + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < imm) || (sum < reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn +8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub +"sub" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); +} + +// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn +8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc +"subc" +*am33 +{ + int dstreg, z, n, c, v; + unsigned long difference, imm, reg2; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); + reg2 = State.regs[dstreg]; + difference = reg2 - imm - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (imm > reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn +8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp +"cmp" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]); +} + +// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn +8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; +} + +// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn +8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and +"and" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn +8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or +"or" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn +8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor +"xor" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn +8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr +"asr" +*am33 +{ + int dstreg; + long temp; + int c, z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + + +// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn +8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr +"lsr" +*am33 +{ + int dstreg; + int z, n, c; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn +8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl +"asl" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn +8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul +"mul" +*am33 +{ + int dstreg; + unsigned long long temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn +8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu +"mulu" +*am33 +{ + int dstreg; + unsigned long long temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn +8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst +"btst" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + +// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn +8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn) +8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn +8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn) +8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn +8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn) +8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn +8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+) +8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + + +// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn +8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp) +8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn +8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp) +8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn +8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp) +8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn +8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+) +8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn +8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac +"mac" +*am33 +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (signed64)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn +8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu +"macu" +*am33 +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (unsigned64)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn +8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb +"macb" +*am33 +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (signed64)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn +8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu +"macbu" +*am33 +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (unsigned64)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn +8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach +"mach" +*am33 +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (signed64)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn +8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu +"machu" +*am33 +{ + int srcreg; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff) + * (unsigned64)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn +8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24) +8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + + +// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn +8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24) +8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + + +// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn +8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24) +8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + + +// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn +8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn +8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu +"movu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn +8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add +"add" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); +} + +// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn +8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc +"addc" +*am33 +{ + int dstreg; + unsigned int imm, reg2, sum; + int z, n, c, v; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + reg2 = State.regs[dstreg]; + sum = imm + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < imm) || (sum < reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn +8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub +"sub" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); +} + +// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn +8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc +"subc" +*am33 +{ + int dstreg; + unsigned int imm, reg2, difference; + int z, n, c, v; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + reg2 = State.regs[dstreg]; + difference = reg2 - imm - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (imm > reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn +8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp +"cmp" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn +8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn +8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and +"and" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn +8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or +"or" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn +8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor +"xor" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn +8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr +"asr" +*am33 +{ + int dstreg; + long temp; + int c, z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn +8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr +"lsr" +*am33 +{ + int dstreg; + int z, n, c; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn +8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl +"asl" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn +8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul +"mul" +*am33 +{ + int dstreg; + unsigned long long temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn +8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu +"mulu" +*am33 +{ + int dstreg; + unsigned long long temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn +8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst +"btst" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn +8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn) +8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn +8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn) +8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn +8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn) +8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn +8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+) +8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + + +// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn +8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp) +8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn +8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp) +8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn +8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp) +8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + + +// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn +8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+) +8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + + +// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn +8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac +"mac" +*am33 +{ + int srcreg, imm; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed64)(signed32)State.regs[srcreg] + * (signed64)(signed32)imm); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn +8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu +"macu" +*am33 +{ + int srcreg, imm; + long long temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned64)State.regs[srcreg] + * (unsigned64)imm); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn +8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb +"macb" +*am33 +{ + int srcreg, imm; + long temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff) + * (signed32)(signed8)(imm & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn +8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu +"macbu" +*am33 +{ + int srcreg, imm; + long temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[srcreg] & 0xff) + * (unsigned32)(imm & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn +8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach +"mach" +*am33 +{ + int srcreg, imm; + long temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) + * (signed32)(signed16)(imm & 0xffff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn +8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu +"machu" +*am33 +{ + int srcreg, imm; + long temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[srcreg] & 0xffff) + * (unsigned32)(imm & 0xffff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn +8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach +"dmach" +*am33 +{ + int srcreg, imm; + long temp, temp2, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) + * (signed32)(signed16)(imm & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff) + * (signed32)(signed16)((imm >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn +8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu +"dmachu" +*am33 +{ + int srcreg, imm; + long temp, temp2, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[srcreg] & 0xffff) + * (unsigned32)(imm & 0xffff)); + temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff) + * (unsigned32)((imm >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn +8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh +"dmulh" +*am33 +{ + int imm, dstreg; + long temp; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) + * (signed32)(signed16)(imm & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) + * (signed32)(signed16)((imm>>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn +8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu +"dmulhu" +*am33 +{ + int imm, dstreg; + long temp; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[dstreg] & 0xffff) + * (unsigned32)(imm & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) + * (unsigned32)((imm >>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn +8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32) +8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn +8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32) +8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn +8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32) +8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add +"add_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add +"add_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub +"add_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub +"add_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp +"add_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] += State.regs[srcreg1]; +} + +// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp +"add_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] += State.regs[srcreg1]; +} + +// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov +"add_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov +"add_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr +"add_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr +"add_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr +"add_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr +"add_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl +"add_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl +"add_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add +"cmp_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] += State.regs[srcreg2]; +} + +// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add +"cmp_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] += EXTEND4 (IMM4); +} + +// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub +"cmp_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] -= State.regs[srcreg2]; +} + +// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub +"cmp_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] -= EXTEND4 (IMM4); +} + +// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov +"cmp_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] = State.regs[srcreg2]; +} + +// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov +"cmp_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] = EXTEND4 (IMM4); +} + +// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr +"cmp_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr +"cmp_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr +"cmp_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] >>= State.regs[srcreg2]; +} + +// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr +"cmp_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] >>= IMM4; +} + + +// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl +"cmp_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] <<= State.regs[srcreg2]; +} + +// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl +"cmp_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] <<= IMM4; +} + +// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add +"sub_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add +"sub_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub +"sub_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub +"sub_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp +"sub_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] -= State.regs[srcreg1]; +} + +// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp +"sub_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] -= State.regs[srcreg1]; +} + +// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov +"sub_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov +"sub_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr +"sub_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr +"sub_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr +"sub_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr +"sub_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl +"sub_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl +"sub_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add +"mov_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add +"mov_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub +"mov_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub +"mov_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp +"mov_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp +"mov_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov +"mov_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov +"mov_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr +"mov_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr +"mov_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr +"mov_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr +"mov_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl +"mov_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl +"mov_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add +"add_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add +"add_add" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub +"add_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub +"add_sub" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp +"add_cmp" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] += EXTEND4 (IMM4A); +} + +// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp +"add_cmp" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] += EXTEND4 (IMM4A); +} + +// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov +"add_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov +"add_mov" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr +"add_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr +"add_asr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr +"add_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr +"add_lsr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl +"add_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl +"add_asl" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add +"cmp_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] += State.regs[srcreg2]; +} + +// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add +"cmp_add" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] += EXTEND4 (IMM4); +} + +// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub +"cmp_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] -= State.regs[srcreg2]; +} + +// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub +"cmp_sub" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] -= EXTEND4 (IMM4); +} + +// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov +"cmp_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] = State.regs[srcreg2]; +} + +// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov +"cmp_mov" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] = EXTEND4 (IMM4); +} + +// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr +"cmp_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr +"cmp_asr" +*am33 +{ + int dstreg1, dstreg2; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr +"cmp_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] >>= State.regs[srcreg2]; +} + +// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr +"cmp_lsr" +*am33 +{ + int dstreg1, dstreg2; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] >>= IMM4; +} + + +// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl +"cmp_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] <<= State.regs[srcreg2]; +} + +// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl +"cmp_asl" +*am33 +{ + int dstreg1, dstreg2; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] <<= IMM4; +} + +// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add +"sub_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add +"sub_add" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub +"sub_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub +"sub_sub" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp +"sub_cmp" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] -= EXTEND4 (IMM4A); +} + +// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp +"sub_cmp" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] -= EXTEND4 (IMM4A); +} + +// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov +"sub_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov +"sub_mov" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr +"sub_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr +"sub_asr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr +"sub_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr +"sub_lsr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl +"sub_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl +"sub_asl" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add +"mov_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add +"mov_add" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub +"mov_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub +"mov_sub" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp +"mov_cmp" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = EXTEND4 (IMM4A); +} + +// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp +"mov_cmp" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = EXTEND4 (IMM4A); +} + +// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov +"mov_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov +"mov_mov" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr +"mov_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr +"mov_asr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr +"mov_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr +"mov_lsr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl +"mov_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl +"mov_asl" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add +"and_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add +"and_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub +"and_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub +"and_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp +"and_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] &= State.regs[srcreg1]; +} + +// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp +"and_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] &= State.regs[srcreg1]; +} + +// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov +"and_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov +"and_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr +"and_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr +"and_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr +"and_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr +"and_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl +"and_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl +"and_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add +"dmach_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add +"dmach_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub +"dmach_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub +"dmach_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp +"dmach_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp +"dmach_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov +"dmach_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov +"dmach_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = sum; +} + +// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr +"dmach_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr +"dmach_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr +"dmach_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr +"dmach_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = sum; +} + + +// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl +"dmach_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl +"dmach_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + long temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add +"xor_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add +"xor_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub +"xor_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub +"xor_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp +"xor_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] ^= State.regs[srcreg1]; +} + +// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp +"xor_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] ^= State.regs[srcreg1]; +} + +// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov +"xor_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov +"xor_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr +"xor_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr +"xor_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr +"xor_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr +"xor_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl +"xor_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl +"xor_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add +"swhw_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add +"swhw_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub +"swhw_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub +"swhw_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp +"swhw_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); +} + +// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp +"swhw_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); +} + +// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov +"swhw_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov +"swhw_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr +"swhw_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr +"swhw_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr +"swhw_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr +"swhw_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl +"swhw_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl +"swhw_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add +"or_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add +"or_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub +"or_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub +"or_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp +"or_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] |= State.regs[srcreg1]; +} + +// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp +"or_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] |= State.regs[srcreg1]; +} + +// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov +"or_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov +"or_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr +"or_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr +"or_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr +"or_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr +"or_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl +"or_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl +"or_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add +"sat16_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add +"sat16_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub +"sat16_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub +"sat16_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp +"sat16_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + State.regs[dstreg1] = result1; + if (State.regs[srcreg1] >= 0x7fff) + State.regs[dstreg1] = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + State.regs[dstreg1] = 0xffff8000; + else + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp +"sat16_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + if (State.regs[srcreg1] >= 0x7fff) + State.regs[dstreg1] = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + State.regs[dstreg1] = 0xffff8000; + else + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov +"sat16_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov +"sat16_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr +"sat16_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr +"sat16_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr +"sat16_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr +"sat16_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl +"sat16_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl +"sat16_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt +"mov_llt" +*am33 +{ + int srcreg, dstreg; + int result1; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } + State.regs[dstreg] = result1; +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt +"mov_lgt" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge +"mov_lge" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle +"mov_lle" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if ((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs +"mov_lcs" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (PSW & PSW_C) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi +"mov_lhi" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc +"mov_lcc" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(PSW & PSW_C)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls +"mov_lls" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq +"mov_leq" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (PSW & PSW_Z) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne +"mov_lne" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(PSW & PSW_Z)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra +"mov_lra" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; +} diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen index 1b42db4..2ffa980 100644 --- a/sim/mn10300/mn10300.igen +++ b/sim/mn10300/mn10300.igen @@ -3,6 +3,7 @@ :option:::insn-specifying-widths:true :option:::hi-bit-nr:7 :model:::mn10300:mn10300: +:model:::am33:am33: // What do we do with an illegal instruction? :internal::::illegal: @@ -15,6 +16,7 @@ 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov "mov" *mn10300 +*am33 { /* OP_8000 (); */ signed32 immed = EXTEND8 (IMM8); @@ -26,6 +28,7 @@ 4.0x8,2.DM1,2.DN0!DM1:S0:::mov "mov" *mn10300 +*am33 { PC = cia; /* OP_80 (); */ @@ -37,6 +40,7 @@ 8.0xf1+1110,2.DM1,2.AN0:D0:::mov "mov" *mn10300 +*am33 { /* OP_F1E0 (); */ PC = cia; @@ -48,6 +52,7 @@ 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov "mov" *mn10300 +*am33 { /* OP_F1D0 (); */ PC = cia; @@ -59,6 +64,7 @@ 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov "mov" *mn10300 +*am33 { PC = cia; /* OP_9000 (); */ @@ -70,6 +76,7 @@ 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov "mov" *mn10300 +*am33 { PC = cia; /* OP_90 (); */ @@ -81,6 +88,7 @@ 4.0x3,11,2.AN0:S0b:::mov "mov" *mn10300 +*am33 { /* OP_3C (); */ PC = cia; @@ -92,6 +100,7 @@ 8.0xf2+4.0xf,2.AM1,00:D0b:::mov "mov" *mn10300 +*am33 { /* OP_F2F0 (); */ PC = cia; @@ -103,6 +112,7 @@ 8.0xf2+4.0xe,01,2.DN0:D0c:::mov "mov" *mn10300 +*am33 { /* OP_F2E4 (); */ PC = cia; @@ -114,6 +124,7 @@ 8.0xf2+4.0xf,2.DM1,11:D0d:::mov "mov" *mn10300 +*am33 { /* OP_F2F3 (); */ PC = cia; @@ -125,6 +136,7 @@ 8.0xf2+4.0xe,00,2.DN0:D0e:::mov "mov" *mn10300 +*am33 { /* OP_F2E0 (); */ PC = cia; @@ -136,6 +148,7 @@ 8.0xf2+4.0xf,2.DM1,10:D0f:::mov "mov" *mn10300 +*am33 { /* OP_F2F2 (); */ PC = cia; @@ -147,6 +160,7 @@ 4.0x7,2.DN1,2.AM0:S0c:::mov "mov" *mn10300 +*am33 { /* OP_70 (); */ PC = cia; @@ -158,6 +172,7 @@ 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov "mov" *mn10300 +*am33 { /* OP_F80000 (); */ PC = cia; @@ -170,6 +185,7 @@ 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov "mov" *mn10300 +*am33 { /* OP_FA000000 (); */ PC = cia; @@ -182,6 +198,7 @@ 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov "mov" *mn10300 +*am33 { /* OP_FC000000 (); */ PC = cia; @@ -195,6 +212,7 @@ 4.0x5,10,2.DN0+8.D8:S1:::mov "mov" *mn10300 +*am33 { /* OP_5800 (); */ PC = cia; @@ -206,6 +224,7 @@ 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov "mov" *mn10300 +*am33 { /* OP_FAB40000 (); */ PC = cia; @@ -218,6 +237,7 @@ 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov "mov" *mn10300 +*am33 { /* OP_FCB40000 (); */ PC = cia; @@ -230,6 +250,7 @@ 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov "mov" *mn10300 +*am33 { /* OP_F300 (); */ PC = cia; @@ -242,6 +263,7 @@ 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov "mov" *mn10300 +*am33 { /* OP_300000 (); */ PC = cia; @@ -252,6 +274,7 @@ 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov "mov" *mn10300 +*am33 { /* OP_FCA40000 (); */ PC = cia; @@ -263,6 +286,7 @@ 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov "mov" *mn10300 +*am33 { /* OP_F000 (); */ PC = cia; @@ -274,6 +298,7 @@ 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov "mov" *mn10300 +*am33 { /* OP_F82000 (); */ PC = cia; @@ -286,6 +311,7 @@ 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov "mov" *mn10300 +*am33 { /* OP_FA200000 (); */ PC = cia; @@ -299,6 +325,7 @@ 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov "mov" *mn10300 +*am33 { /* OP_FC200000 (); */ PC = cia; @@ -312,6 +339,7 @@ 4.0x5,11,2.AN0+8.D8:S1a:::mov "mov" *mn10300 +*am33 { /* OP_5C00 (); */ PC = cia; @@ -324,6 +352,7 @@ 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov "mov" *mn10300 +*am33 { /* OP_FAB00000 (); */ PC = cia; @@ -336,6 +365,7 @@ 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov "mov" *mn10300 +*am33 { /* OP_FCB00000 (); */ PC = cia; @@ -349,6 +379,7 @@ 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov "mov" *mn10300 +*am33 { /* OP_F380 (); */ PC = cia; @@ -362,6 +393,7 @@ 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov "mov" *mn10300 +*am33 { /* OP_FAA00000 (); */ PC = cia; @@ -373,6 +405,7 @@ 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov "mov" *mn10300 +*am33 { /* OP_FCA00000 (); */ PC = cia; @@ -385,6 +418,7 @@ 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov "mov" *mn10300 +*am33 { /* OP_F8F000 (); */ PC = cia; @@ -397,6 +431,7 @@ 4.0x6,2.DM1,2.AN0:S0d:::mov "mov" *mn10300 +*am33 { /* OP_60 (); */ PC = cia; @@ -408,6 +443,7 @@ 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov "mov" *mn10300 +*am33 { /* OP_F81000 (); */ PC = cia; @@ -420,6 +456,7 @@ 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov "mov" *mn10300 +*am33 { /* OP_FA100000 (); */ PC = cia; @@ -432,6 +469,7 @@ 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov "mov" *mn10300 +*am33 { /* OP_FC100000 (); */ PC = cia; @@ -445,6 +483,7 @@ 4.0x4,2.DM1,10+8.D8:S1b:::mov "mov" *mn10300 +*am33 { /* OP_4200 (); */ PC = cia; @@ -456,6 +495,7 @@ 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov "mov" *mn10300 +*am33 { /* OP_FA910000 (); */ PC = cia; @@ -468,6 +508,7 @@ 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov "mov" *mn10300 +*am33 { /* OP_FC910000 (); */ PC = cia; @@ -480,6 +521,7 @@ 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov "mov" *mn10300 +*am33 { /* OP_F340 (); */ PC = cia; @@ -492,6 +534,7 @@ 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov "mov" *mn10300 +*am33 { /* OP_10000 (); */ PC = cia; @@ -503,6 +546,7 @@ 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov "mov" *mn10300 +*am33 { /* OP_FC810000 (); */ PC = cia; @@ -515,6 +559,7 @@ 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov "mov" *mn10300 +*am33 { /* OP_F010 (); */ PC = cia; @@ -526,6 +571,7 @@ 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov "mov" *mn10300 +*am33 { /* OP_F83000 (); */ PC = cia; @@ -538,6 +584,7 @@ 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov "mov" *mn10300 +*am33 { /* OP_FA300000 (); */ PC = cia; @@ -550,6 +597,7 @@ 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov "mov" *mn10300 +*am33 { /* OP_FC300000 (); */ PC = cia; @@ -563,6 +611,9 @@ 4.0x4,2.AM1,11+8.D8:S1c:::mov "mov" *mn10300 + +*am33 + { /* OP_4300 (); */ PC = cia; @@ -574,6 +625,9 @@ 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov "mov" *mn10300 + +*am33 + { /* OP_FA900000 (); */ PC = cia; @@ -586,6 +640,9 @@ 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov "mov" *mn10300 + +*am33 + { /* OP_FC900000 (); */ PC = cia; @@ -598,6 +655,9 @@ 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov "mov" *mn10300 + +*am33 + { /* OP_F3C0 (); */ PC = cia; @@ -610,6 +670,9 @@ 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov "mov" *mn10300 + +*am33 + { /* OP_FA800000 (); */ PC = cia; @@ -622,6 +685,9 @@ 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov "mov" *mn10300 + +*am33 + { /* OP_FC800000 (); */ PC = cia; @@ -634,6 +700,9 @@ 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov "mov" *mn10300 + +*am33 + { /* OP_F8F400 (); */ PC = cia; @@ -646,6 +715,9 @@ 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov "mov" *mn10300 + +*am33 + { /* OP_2C0000 (); */ unsigned long value; @@ -660,6 +732,9 @@ 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov "mov" *mn10300 + +*am33 + { /* OP_FCCC0000 (); */ unsigned long value; @@ -674,6 +749,9 @@ 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov "mov" *mn10300 + +*am33 + { /* OP_240000 (); */ unsigned long value; @@ -688,6 +766,9 @@ 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov "mov" *mn10300 + +*am33 + { /* OP_FCDC0000 (); */ PC = cia; @@ -699,6 +780,9 @@ 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F040 (); */ PC = cia; @@ -711,6 +795,9 @@ 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F84000 (); */ PC = cia; @@ -723,6 +810,9 @@ 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FA400000 (); */ PC = cia; @@ -736,6 +826,9 @@ 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FC400000 (); */ PC = cia; @@ -749,6 +842,9 @@ 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F8B800 (); */ PC = cia; @@ -761,6 +857,9 @@ 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FAB80000 (); */ PC = cia; @@ -774,6 +873,9 @@ 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FCB80000 (); */ PC = cia; @@ -787,6 +889,9 @@ 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F400 (); */ PC = cia; @@ -800,6 +905,9 @@ 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu "movbu" *mn10300 + +*am33 + { /* OP_340000 (); */ PC = cia; @@ -811,6 +919,9 @@ 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FCA80000 (); */ PC = cia; @@ -823,6 +934,9 @@ 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F050 (); */ PC = cia; @@ -834,6 +948,9 @@ 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F85000 (); */ PC = cia; @@ -846,6 +963,9 @@ 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FA500000 (); */ PC = cia; @@ -858,6 +978,9 @@ 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FC500000 (); */ PC = cia; @@ -871,6 +994,9 @@ 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F89200 (); */ PC = cia; @@ -882,6 +1008,9 @@ 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FA920000 (); */ PC = cia; @@ -894,6 +1023,9 @@ 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FC920000 (); */ PC = cia; @@ -906,6 +1038,9 @@ 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu "movbu" *mn10300 + +*am33 + { /* OP_F440 (); */ PC = cia; @@ -918,6 +1053,9 @@ 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu "movbu" *mn10300 + +*am33 + { /* OP_20000 (); */ PC = cia; @@ -930,6 +1068,9 @@ 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu "movbu" *mn10300 + +*am33 + { /* OP_FC820000 (); */ PC = cia; @@ -942,6 +1083,9 @@ 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F060 (); */ PC = cia; @@ -954,6 +1098,9 @@ 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F86000 (); */ PC = cia; @@ -966,6 +1113,9 @@ 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FA600000 (); */ PC = cia; @@ -979,6 +1129,9 @@ 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FC600000 (); */ PC = cia; @@ -992,6 +1145,9 @@ 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F8BC00 (); */ PC = cia; @@ -1004,6 +1160,9 @@ 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FABC0000 (); */ PC = cia; @@ -1016,6 +1175,9 @@ 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FCBC0000 (); */ PC = cia; @@ -1028,6 +1190,9 @@ 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F480 (); */ PC = cia; @@ -1040,6 +1205,9 @@ 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu "movhu" *mn10300 + +*am33 + { /* OP_380000 (); */ PC = cia; @@ -1051,6 +1219,9 @@ 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FCAC0000 (); */ PC = cia; @@ -1063,6 +1234,9 @@ 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F070 (); */ PC = cia; @@ -1075,6 +1249,9 @@ 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F87000 (); */ PC = cia; @@ -1087,6 +1264,9 @@ 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FA700000 (); */ PC = cia; @@ -1099,6 +1279,9 @@ 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FC700000 (); */ PC = cia; @@ -1112,6 +1295,9 @@ 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F89300 (); */ PC = cia; @@ -1124,6 +1310,9 @@ 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FA930000 (); */ PC = cia; @@ -1136,6 +1325,9 @@ 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FC930000 (); */ PC = cia; @@ -1148,6 +1340,9 @@ 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu "movhu" *mn10300 + +*am33 + { /* OP_F4C0 (); */ PC = cia; @@ -1160,6 +1355,9 @@ 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu "movhu" *mn10300 + +*am33 + { /* OP_30000 (); */ PC = cia; @@ -1171,6 +1369,9 @@ 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu "movhu" *mn10300 + +*am33 + { /* OP_FC830000 (); */ PC = cia; @@ -1183,6 +1384,9 @@ 8.0xf2+4.0xd,00,2.DN0:D0:::ext "ext" *mn10300 + +*am33 + { /* OP_F2D0 (); */ PC = cia; @@ -1197,6 +1401,9 @@ 4.0x1,00,2.DN0:S0:::extb "extb" *mn10300 + +*am33 + { /* OP_10 (); */ PC = cia; @@ -1208,6 +1415,9 @@ 4.0x1,01,2.DN0:S0:::extbu "extbu" *mn10300 + +*am33 + { /* OP_14 (); */ PC = cia; @@ -1219,6 +1429,9 @@ 4.0x1,10,2.DN0:S0:::exth "exth" *mn10300 + +*am33 + { /* OP_18 (); */ PC = cia; @@ -1230,6 +1443,9 @@ 4.0x1,11,2.DN0:S0:::exthu "exthu" *mn10300 + +*am33 + { /* OP_1C (); */ PC = cia; @@ -1241,6 +1457,9 @@ 4.0x0,2.DN1,00:S0:::clr "clr" *mn10300 + +*am33 + { /* OP_0 (); */ PC = cia; @@ -1255,6 +1474,9 @@ 4.0xe,2.DM1,2.DN0:S0:::add "add" *mn10300 + +*am33 + { /* OP_E0 (); */ PC = cia; @@ -1265,6 +1487,9 @@ 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add "add" *mn10300 + +*am33 + { /* OP_F160 (); */ PC = cia; @@ -1276,6 +1501,9 @@ 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add "add" *mn10300 + +*am33 + { /* OP_F150 (); */ PC = cia; @@ -1287,6 +1515,9 @@ 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add "add" *mn10300 + +*am33 + { /* OP_F170 (); */ PC = cia; @@ -1298,6 +1529,9 @@ 4.0x2,10,2.DN0+8.IMM8:S1:::add "add" *mn10300 + +*am33 + { /* OP_2800 (); */ PC = cia; @@ -1309,6 +1543,9 @@ 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add "add" *mn10300 + +*am33 + { /* OP_FAC00000 (); */ PC = cia; @@ -1320,6 +1557,9 @@ 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add "add" *mn10300 + +*am33 + { /* OP_FCC00000 (); */ PC = cia; @@ -1331,6 +1571,9 @@ 4.0x2,00,2.AN0+8.IMM8:S1a:::add "add" *mn10300 + +*am33 + { /* OP_2000 (); */ PC = cia; @@ -1342,6 +1585,9 @@ 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add "add" *mn10300 + +*am33 + { /* OP_FAD00000 (); */ PC = cia; @@ -1353,6 +1599,9 @@ 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add "add" *mn10300 + +*am33 + { /* OP_FCD00000 (); */ PC = cia; @@ -1364,6 +1613,9 @@ 8.0xf8+8.0xfe+8.IMM8:D1:::add "add" *mn10300 + +*am33 + { /* OP_F8FE00 (); */ unsigned long imm; @@ -1379,6 +1631,9 @@ 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add "add" *mn10300 + +*am33 + { /* OP_FAFE0000 (); */ unsigned long imm; @@ -1394,6 +1649,9 @@ 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add "add" *mn10300 + +*am33 + { /* OP_FCFE0000 (); */ unsigned long imm; @@ -1409,6 +1667,9 @@ 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc "addc" *mn10300 + +*am33 + { /* OP_F140 (); */ int z, c, n, v; @@ -1436,6 +1697,9 @@ 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub "sub" *mn10300 + +*am33 + { /* OP_F100 (); */ PC = cia; @@ -1446,6 +1710,9 @@ 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub "sub" *mn10300 + +*am33 + { /* OP_F120 (); */ PC = cia; @@ -1457,6 +1724,9 @@ 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub "sub" *mn10300 + +*am33 + { /* OP_F110 (); */ PC = cia; @@ -1468,6 +1738,9 @@ 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub "sub" *mn10300 + +*am33 + { /* OP_F130 (); */ PC = cia; @@ -1479,6 +1752,9 @@ 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub "sub" *mn10300 + +*am33 + { /* OP_FCC40000 (); */ PC = cia; @@ -1490,6 +1766,9 @@ 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub "sub" *mn10300 + +*am33 + { /* OP_FCD40000 (); */ PC = cia; @@ -1501,6 +1780,9 @@ 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc "subc" *mn10300 + +*am33 + { /* OP_F180 (); */ int z, c, n, v; @@ -1528,6 +1810,9 @@ 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul "mul" *mn10300 + +*am33 + { /* OP_F240 (); */ unsigned long long temp; @@ -1549,6 +1834,9 @@ 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu "mulu" *mn10300 + +*am33 + { /* OP_F250 (); */ unsigned long long temp; @@ -1570,6 +1858,9 @@ 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div "div" *mn10300 + +*am33 + { /* OP_F260 (); */ signed64 temp; @@ -1604,6 +1895,9 @@ 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu "divu" *mn10300 + +*am33 + { /* OP_F270 (); */ unsigned64 temp; @@ -1637,6 +1931,9 @@ 4.0x4,2.DN1,00:S0:::inc "inc" *mn10300 + +*am33 + { /* OP_40 (); */ unsigned int imm; @@ -1651,6 +1948,9 @@ 4.0x4,2.AN1,01:S0a:::inc "inc" *mn10300 + +*am33 + { /* OP_41 (); */ PC = cia; @@ -1662,6 +1962,9 @@ 4.0x5,00,2.AN0:S0:::inc4 "inc4" *mn10300 + +*am33 + { /* OP_50 (); */ PC = cia; @@ -1673,6 +1976,9 @@ 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp "cmp" *mn10300 + +*am33 + { PC = cia; /* OP_A000 (); */ @@ -1684,6 +1990,9 @@ 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp "cmp" *mn10300 + +*am33 + { PC = cia; /* OP_A0 (); */ @@ -1695,6 +2004,9 @@ 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp "cmp" *mn10300 + +*am33 + { /* OP_F1A0 (); */ PC = cia; @@ -1706,6 +2018,9 @@ 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp "cmp" *mn10300 + +*am33 + { /* OP_F190 (); */ PC = cia; @@ -1717,6 +2032,9 @@ 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp "cmp" *mn10300 + +*am33 + { PC = cia; /* OP_B000 (); */ @@ -1729,6 +2047,9 @@ 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp "cmp" *mn10300 + +*am33 + { PC = cia; /* OP_B0 (); */ @@ -1740,6 +2061,9 @@ 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp "cmp" *mn10300 + +*am33 + { /* OP_FAC80000 (); */ PC = cia; @@ -1752,6 +2076,9 @@ 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp "cmp" *mn10300 + +*am33 + { /* OP_FCC80000 (); */ PC = cia; @@ -1764,6 +2091,9 @@ 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp "cmp" *mn10300 + +*am33 + { /* OP_FAD80000 (); */ PC = cia; @@ -1776,6 +2106,9 @@ 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp "cmp" *mn10300 + +*am33 + { /* OP_FCD80000 (); */ PC = cia; @@ -1788,6 +2121,9 @@ 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and "and" *mn10300 + +*am33 + { /* OP_F200 (); */ int n, z; @@ -1805,6 +2141,9 @@ 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and "and" *mn10300 + +*am33 + { /* OP_F8E000 (); */ int n, z; @@ -1822,6 +2161,9 @@ 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and "and" *mn10300 + +*am33 + { /* OP_FAE00000 (); */ int n, z; @@ -1839,6 +2181,9 @@ 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and "and" *mn10300 + +*am33 + { /* OP_FCE00000 (); */ int n, z; @@ -1857,6 +2202,9 @@ 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and "and" *mn10300 + +*am33 + { /* OP_FAFC0000 (); */ PC = cia; @@ -1869,6 +2217,9 @@ 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or "or" *mn10300 + +*am33 + { /* OP_F210 (); */ PC = cia; @@ -1880,6 +2231,9 @@ 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or "or" *mn10300 + +*am33 + { /* OP_F8E400 (); */ PC = cia; @@ -1891,6 +2245,9 @@ 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or "or" *mn10300 + +*am33 + { /* OP_FAE40000 (); */ PC = cia; @@ -1902,6 +2259,9 @@ 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or "or" *mn10300 + +*am33 + { /* OP_FCE40000 (); */ PC = cia; @@ -1913,6 +2273,9 @@ 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or "or" *mn10300 + +*am33 + { /* OP_FAFD0000 (); */ PC = cia; @@ -1924,6 +2287,9 @@ 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor "xor" *mn10300 + +*am33 + { /* OP_F220 (); */ PC = cia; @@ -1935,6 +2301,9 @@ 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor "xor" *mn10300 + +*am33 + { /* OP_FAE80000 (); */ PC = cia; @@ -1946,6 +2315,9 @@ 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor "xor" *mn10300 + +*am33 + { /* OP_FCE80000 (); */ PC = cia; @@ -1957,6 +2329,9 @@ 8.0xf2+4.0x3,00,2.DN0:D0:::not "not" *mn10300 + +*am33 + { /* OP_F230 (); */ int n, z; @@ -1974,6 +2349,9 @@ 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst "btst" *mn10300 + +*am33 + { /* OP_F8EC00 (); */ PC = cia; @@ -1985,6 +2363,9 @@ 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst "btst" *mn10300 + +*am33 + { /* OP_FAEC0000 (); */ PC = cia; @@ -1996,6 +2377,9 @@ 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst "btst" *mn10300 + +*am33 + { /* OP_FCEC0000 (); */ PC = cia; @@ -2008,6 +2392,9 @@ 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst "btst" *mn10300 + +*am33 + { /* OP_FE020000 (); */ PC = cia; @@ -2021,6 +2408,9 @@ 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst "btst" *mn10300 + +*am33 + { /* OP_FAF80000 (); */ PC = cia; @@ -2033,6 +2423,9 @@ 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset "bset" *mn10300 + +*am33 + { /* OP_F080 (); */ unsigned long temp; @@ -2053,6 +2446,9 @@ 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset "bset" *mn10300 + +*am33 + { /* OP_FE000000 (); */ unsigned long temp; @@ -2073,6 +2469,9 @@ 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset "bset" *mn10300 + +*am33 + { /* OP_FAF00000 (); */ unsigned long temp; @@ -2092,6 +2491,9 @@ 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr "bclr" *mn10300 + +*am33 + { /* OP_F090 (); */ unsigned long temp; @@ -2112,6 +2514,9 @@ 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr "bclr" *mn10300 + +*am33 + { /* OP_FE010000 (); */ unsigned long temp; @@ -2132,6 +2537,9 @@ 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr "bclr" *mn10300 + +*am33 + { /* OP_FAF40000 (); */ unsigned long temp; @@ -2151,6 +2559,9 @@ 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr "asr" *mn10300 + +*am33 + { /* OP_F2B0 (); */ long temp; @@ -2172,6 +2583,9 @@ 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr "asr" *mn10300 + +*am33 + { /* OP_F8C800 (); */ long temp; @@ -2193,6 +2607,9 @@ 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr "lsr" *mn10300 + +*am33 + { /* OP_F2A0 (); */ int z, n, c; @@ -2212,6 +2629,9 @@ 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr "lsr" *mn10300 + +*am33 + { /* OP_F8C400 (); */ int z, n, c; @@ -2230,6 +2650,9 @@ 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl "asl" *mn10300 + +*am33 + { /* OP_F290 (); */ int n, z; @@ -2248,6 +2671,9 @@ 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl "asl" *mn10300 + +*am33 + { /* OP_F8C000 (); */ int n, z; @@ -2265,6 +2691,9 @@ 4.0x5,01,2.DN0:S0:::asl2 "asl2" *mn10300 + +*am33 + { /* OP_54 (); */ int n, z; @@ -2282,6 +2711,9 @@ 8.0xf2+4.0x8,01,2.DN0:D0:::ror "ror" *mn10300 + +*am33 + { /* OP_F284 (); */ unsigned long value; @@ -2305,6 +2737,9 @@ 8.0xf2+4.0x8,00,2.DN0:D0:::rol "rol" *mn10300 + +*am33 + { /* OP_F280 (); */ unsigned long value; @@ -2328,6 +2763,9 @@ 8.0xc8+8.D8:S1:::beq "beq" *mn10300 + +*am33 + { /* OP_C800 (); */ PC = cia; @@ -2343,6 +2781,9 @@ 8.0xc9+8.D8:S1:::bne "bne" *mn10300 + +*am33 + { /* OP_C900 (); */ PC = cia; @@ -2358,6 +2799,9 @@ 8.0xc1+8.D8:S1:::bgt "bgt" *mn10300 + +*am33 + { /* OP_C100 (); */ PC = cia; @@ -2374,6 +2818,9 @@ 8.0xc2+8.D8:S1:::bge "bge" *mn10300 + +*am33 + { /* OP_C200 (); */ PC = cia; @@ -2389,6 +2836,9 @@ 8.0xc3+8.D8:S1:::ble "ble" *mn10300 + +*am33 + { /* OP_C300 (); */ PC = cia; @@ -2405,6 +2855,9 @@ 8.0xc0+8.D8:S1:::blt "blt" *mn10300 + +*am33 + { /* OP_C000 (); */ PC = cia; @@ -2420,6 +2873,9 @@ 8.0xc5+8.D8:S1:::bhi "bhi" *mn10300 + +*am33 + { /* OP_C500 (); */ PC = cia; @@ -2435,6 +2891,9 @@ 8.0xc6+8.D8:S1:::bcc "bcc" *mn10300 + +*am33 + { /* OP_C600 (); */ PC = cia; @@ -2450,6 +2909,9 @@ 8.0xc7+8.D8:S1:::bls "bls" *mn10300 + +*am33 + { /* OP_C700 (); */ PC = cia; @@ -2465,6 +2927,9 @@ 8.0xc4+8.D8:S1:::bcs "bcs" *mn10300 + +*am33 + { /* OP_C400 (); */ PC = cia; @@ -2480,6 +2945,9 @@ 8.0xf8+8.0xe8+8.D8:D1:::bvc "bvc" *mn10300 + +*am33 + { /* OP_F8E800 (); */ PC = cia; @@ -2495,6 +2963,9 @@ 8.0xf8+8.0xe9+8.D8:D1:::bvs "bvs" *mn10300 + +*am33 + { /* OP_F8E900 (); */ PC = cia; @@ -2510,6 +2981,9 @@ 8.0xf8+8.0xea+8.D8:D1:::bnc "bnc" *mn10300 + +*am33 + { /* OP_F8EA00 (); */ PC = cia; @@ -2525,6 +2999,9 @@ 8.0xf8+8.0xeb+8.D8:D1:::bns "bns" *mn10300 + +*am33 + { /* OP_F8EB00 (); */ PC = cia; @@ -2540,6 +3017,9 @@ 8.0xca+8.D8:S1:::bra "bra" *mn10300 + +*am33 + { /* OP_CA00 (); */ PC = cia; @@ -2552,6 +3032,9 @@ 8.0xd8:S0:::leq "leq" *mn10300 + +*am33 + { /* OP_D8 (); */ PC = cia; @@ -2567,6 +3050,9 @@ 8.0xd9:S0:::lne "lne" *mn10300 + +*am33 + { /* OP_D9 (); */ PC = cia; @@ -2582,6 +3068,9 @@ 8.0xd1:S0:::lgt "lgt" *mn10300 + +*am33 + { /* OP_D1 (); */ PC = cia; @@ -2598,6 +3087,9 @@ 8.0xd2:S0:::lge "lge" *mn10300 + +*am33 + { /* OP_D2 (); */ PC = cia; @@ -2613,6 +3105,9 @@ 8.0xd3:S0:::lle "lle" *mn10300 + +*am33 + { /* OP_D3 (); */ PC = cia; @@ -2629,6 +3124,9 @@ 8.0xd0:S0:::llt "llt" *mn10300 + +*am33 + { /* OP_D0 (); */ PC = cia; @@ -2644,6 +3142,9 @@ 8.0xd5:S0:::lhi "lhi" *mn10300 + +*am33 + { /* OP_D5 (); */ PC = cia; @@ -2659,6 +3160,9 @@ 8.0xd6:S0:::lcc "lcc" *mn10300 + +*am33 + { /* OP_D6 (); */ PC = cia; @@ -2674,6 +3178,9 @@ 8.0xd7:S0:::lls "lls" *mn10300 + +*am33 + { /* OP_D7 (); */ PC = cia; @@ -2689,6 +3196,9 @@ 8.0xd4:S0:::lcs "lcs" *mn10300 + +*am33 + { /* OP_D4 (); */ PC = cia; @@ -2704,6 +3214,9 @@ 8.0xda:S0:::lra "lra" *mn10300 + +*am33 + { /* OP_DA (); */ PC = cia; @@ -2716,6 +3229,9 @@ 8.0xdb:S0:::setlb "setlb" *mn10300 + +*am33 + { /* OP_DB (); */ PC = cia; @@ -2728,6 +3244,9 @@ 8.0xf0+4.0xf,01,2.AN0:D0:::jmp "jmp" *mn10300 + +*am33 + { /* OP_F0F4 (); */ PC = State.regs[REG_A0 + AN0]; @@ -2739,6 +3258,9 @@ 8.0xcc+8.D16A+8.D16B:S2:::jmp "jmp" *mn10300 + +*am33 + { /* OP_CC0000 (); */ PC = cia + EXTEND16(FETCH16(D16A, D16B)); @@ -2750,6 +3272,9 @@ 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp "jmp" *mn10300 + +*am33 + { /* OP_DC000000 (); */ PC = cia + FETCH32(D32A, D32B, D32C, D32D); @@ -2761,6 +3286,9 @@ 8.0xf0+4.0xf,00,2.AN0:D0:::calls "calls" *mn10300 + +*am33 + { /* OP_F0F0 (); */ unsigned int next_pc, sp; @@ -2779,6 +3307,9 @@ 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls "calls" *mn10300 + +*am33 + { /* OP_FAFF0000 (); */ unsigned int next_pc, sp; @@ -2797,6 +3328,9 @@ 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls "calls" *mn10300 + +*am33 + { /* OP_FCFF0000 (); */ unsigned int next_pc, sp; @@ -2815,6 +3349,9 @@ 8.0xf0+8.0xfc:D0:::rets "rets" *mn10300 + +*am33 + { /* OP_F0FC (); */ unsigned int sp; @@ -2829,6 +3366,9 @@ 8.0xf0+8.0xfd:D0:::rti "rti" *mn10300 + +*am33 + { /* OP_F0FD (); */ unsigned int sp; @@ -2845,6 +3385,9 @@ 8.0xf0+8.0xfe:D0:::trap "trap" *mn10300 + +*am33 + { /* OP_F0FE (); */ unsigned int sp, next_pc; @@ -2861,6 +3404,9 @@ 8.0xf0+8.0xff:D0:::rtm "rtm" *mn10300 + +*am33 + { /* OP_F0FF (); */ PC = cia; @@ -2872,6 +3418,9 @@ 8.0xcb:S0:::nop "nop" *mn10300 + +*am33 + { /* OP_CB (); */ PC = cia; @@ -2893,6 +3442,9 @@ 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx "getx" *mn10300 + +*am33 + { /* OP_F6F0 (); */ int z, n; @@ -2911,6 +3463,9 @@ 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq "mulq" *mn10300 + +*am33 + { /* OP_F600 (); */ unsigned long long temp; @@ -2932,6 +3487,9 @@ 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq "mulq" *mn10300 + +*am33 + { /* OP_F90000 (); */ unsigned long long temp; @@ -2953,6 +3511,9 @@ 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq "mulq" *mn10300 + +*am33 + { /* OP_FB000000 (); */ unsigned long long temp; @@ -2974,6 +3535,9 @@ 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq "mulq" *mn10300 + +*am33 + { /* OP_FD000000 (); */ unsigned long long temp; @@ -2995,6 +3559,9 @@ 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu "mulqu" *mn10300 + +*am33 + { /* OP_F610 (); */ unsigned long long temp; @@ -3016,6 +3583,9 @@ 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu "mulqu" *mn10300 + +*am33 + { /* OP_F91400 (); */ unsigned long long temp; @@ -3037,6 +3607,9 @@ 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu "mulqu" *mn10300 + +*am33 + { /* OP_FB140000 (); */ unsigned long long temp; @@ -3058,6 +3631,9 @@ 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu "mulqu" *mn10300 + +*am33 + { /* OP_FD140000 (); */ unsigned long long temp; @@ -3079,6 +3655,9 @@ 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16 "sat16" *mn10300 + +*am33 + { /* OP_F640 (); */ int temp; @@ -3095,6 +3674,9 @@ 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24 "sat24" *mn10300 + +*am33 + { /* OP_F650 (); */ int temp; @@ -3111,6 +3693,9 @@ 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch "bsch" *mn10300 + +*am33 + { /* OP_F670 (); */ int temp, c; @@ -3128,6 +3713,9 @@ 8.0xf0+8.0xc0:D0:::syscall "syscall" *mn10300 + +*am33 + { /* OP_F0C0 (); */ PC = cia; @@ -3139,6 +3727,9 @@ 8.0xff:S0:::break "break" *mn10300 + +*am33 + { /* OP_FF (); */ PC = cia; @@ -3149,6 +3740,9 @@ 8.0xce+8.REGS:S1:::movm "movm" *mn10300 + +*am33 + { /* OP_CE00 (); */ unsigned long sp = State.regs[REG_SP]; @@ -3200,6 +3794,38 @@ sp += 4; } + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + if (mask & 0x1) + { + /* Need to restore MDQR, MCRH, MCRL, and MCVF */ + sp += 16; + State.regs[REG_E0 + 1] = load_word (sp); + sp += 4; + State.regs[REG_E0 + 0] = load_word (sp); + sp += 4; + } + + if (mask & 0x2) + { + State.regs[REG_E0 + 7] = load_word (sp); + sp += 4; + State.regs[REG_E0 + 6] = load_word (sp); + sp += 4; + State.regs[REG_E0 + 5] = load_word (sp); + sp += 4; + State.regs[REG_E0 + 4] = load_word (sp); + sp += 4; + } + + if (mask & 0x4) + { + State.regs[REG_E0 + 3] = load_word (sp); + sp += 4; + State.regs[REG_E0 + 2] = load_word (sp); + sp += 4; + } + } /* And make sure to update the stack pointer. */ State.regs[REG_SP] = sp; @@ -3210,6 +3836,9 @@ 8.0xcf+8.REGS:S1a:::movm "movm" *mn10300 + +*am33 + { /* OP_CF00 (); */ unsigned long sp = State.regs[REG_SP]; @@ -3218,6 +3847,38 @@ PC = cia; mask = REGS; + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + if (mask & 0x4) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 2]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 3]); + } + + if (mask & 0x2) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 4]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 5]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 6]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 7]); + } + + if (mask & 0x1) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 0]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 1]); + sp -= 16; + /* Need to save MDQR, MCRH, MCRL, and MCVF */ + } + } if (mask & 0x80) { @@ -3271,6 +3932,9 @@ 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call "call" *mn10300 + +*am33 + { /* OP_CD000000 (); */ unsigned int next_pc, sp; @@ -3283,6 +3947,38 @@ mask = REGS; + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + if (mask & 0x4) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 2]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 3]); + } + + if (mask & 0x2) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 4]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 5]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 6]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 7]); + } + + if (mask & 0x1) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 0]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 1]); + sp -= 16; + /* Need to save MDQR, MCRH, MCRL, and MCVF */ + } + } if (mask & 0x80) { @@ -3342,6 +4038,9 @@ 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call "call" *mn10300 + +*am33 + { /* OP_DD000000 (); */ unsigned int next_pc, sp; @@ -3355,6 +4054,38 @@ mask = REGS; + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + if (mask & 0x4) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 2]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 3]); + } + + if (mask & 0x2) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 4]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 5]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 6]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 7]); + } + + if (mask & 0x1) + { + sp -= 4; + store_word (sp, State.regs[REG_E0 + 0]); + sp -= 4; + store_word (sp, State.regs[REG_E0 + 1]); + sp -= 16; + /* Need to save MDQR, MCRH, MCRL, and MCVF */ + } + } if (mask & 0x80) { @@ -3413,6 +4144,9 @@ 8.0xdf+8.REGS+8.IMM8:S2:::ret "ret" *mn10300 + +*am33 + { /* OP_DF0000 (); */ unsigned int sp, offset; @@ -3425,6 +4159,40 @@ offset = -4; mask = REGS; + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + + if (mask & 0x4) + { + State.regs[REG_E0 + 2] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 3] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x2) + { + State.regs[REG_E0 + 4] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 5] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 6] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 7] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x1) + { + /* Need to restore MDQR, MCRH, MCRL, and MCVF */ + offset -= 16; + State.regs[REG_E0 + 0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 1] = load_word (sp + offset); + offset -= 4; + } + + } if (mask & 0x80) { @@ -3478,6 +4246,9 @@ 8.0xde+8.REGS+8.IMM8:S2:::retf "retf" *mn10300 + +*am33 + { /* OP_DE0000 (); */ unsigned int sp, offset; @@ -3491,6 +4262,40 @@ offset = -4; mask = REGS; + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33) + { + + if (mask & 0x4) + { + State.regs[REG_E0 + 2] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 3] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x2) + { + State.regs[REG_E0 + 4] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 5] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 6] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 7] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x1) + { + /* Need to restore MDQR, MCRH, MCRL, and MCVF */ + offset -= 16; + State.regs[REG_E0 + 0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_E0 + 1] = load_word (sp + offset); + offset -= 4; + } + + } if (mask & 0x80) { @@ -3536,3 +4341,6 @@ nia = PC; } + +:include::am33:am33.igen + diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h index b794fd0..0e41943 100644 --- a/sim/mn10300/mn10300_sim.h +++ b/sim/mn10300/mn10300_sim.h @@ -115,6 +115,13 @@ extern struct simops Simops[]; #define REG_LIR 12 #define REG_LAR 13 #define REG_MDRQ 14 +#define REG_E0 15 +#define REG_SSP 23 +#define REG_MSP 24 +#define REG_USP 25 +#define REG_MCRH 26 +#define REG_MCRL 27 +#define REG_MCVF 28 #if WITH_COMMON /* These definitions conflict with similar macros in common. */ |