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Diffstat (limited to 'sim/mn10300/ChangeLog')
-rw-r--r-- | sim/mn10300/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 51efa7b..50db974 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,10 @@ +Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (load_mem): If we get a load from an out of range + address, abort. + (store_mem): Likewise for stores. + (max_mem): New variable. + Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com) * mn10300_sim.h: Fix ordering of bits in the PSW. |