diff options
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 5a6a0e0..8c192d2 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,10 @@ +Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * mips.igen (do_store_left, do_load_left): Compute nr of left and + right bits and then re-align left hand bytes to correct byte + lanes. Fix incorrect computation in do_store_left when loading + bytes from second word. + start-sanitize-tx3904 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> |