diff options
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/mips/interp.c | 9 |
2 files changed, 12 insertions, 2 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index c12ec65..6c8bc4a 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +1999-11-11 Andrew Haley <aph@cygnus.com> + + * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 + instructions. + Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com> * mips.igen (MULT): Correct previous mis-applied patch. diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 68ffd27..9c53ff9 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3124,9 +3124,14 @@ decode_coproc (SIM_DESC sd, CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) ERET Exception return (VR4100 = 01000010000000000000000000011000) */ - if (((code == 0x00) || (code == 0x04)) && tail == 0) + if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */ + || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */ + && tail == 0) { - /* M[TF]C0 - 32 bit word */ + /* Clear double/single coprocessor move bit. */ + code &= ~1; + + /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */ switch (rd) /* NOTEs: Standard CP0 registers */ { |