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-rw-r--r--sim/mips/mips3264r2.igen11
1 files changed, 11 insertions, 0 deletions
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index c52ec3b..e0b6d5b 100644
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -241,6 +241,17 @@
}
+011111,00000,5.RT,5.RD,00000,111011::32::RDHWR
+"rdhwr r<RT>, r<RD>"
+*mips32r2:
+*mips64r2:
+{
+ // Return 0 for all hardware registers currently
+ GPR[RT] = EXTEND32 (0);
+ TRACE_ALU_RESULT1 (GPR[RT]);
+}
+
+
011111,00000,5.RT,5.RD,00010,100000::32::WSBH
"wsbh r<RD>, r<RT>"
*mips32r2: